Wafer defect detection method and system based on lightweight multi-scale wafer defect detection model

Abstract

The invention provides a wafer defect detection method based on a lightweight multi-scale wafer defect detection model, and the method comprises the steps: firstly obtaining a to-be-detected wafer image, and carrying out the preprocessing of the to-be-detected wafer image; thirdly, constructing and training a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model comprises a lightweight Stem-Dense feature extraction module used for primary wafer image feature extraction and performing multi-scale feature extraction on the basis of primary wafer image feature extraction, the multi-scale feature extraction and fusion module is used for carrying out feature extraction on the first wafer image and carrying out feature fusion with the first wafer image; the CNN feature extraction module is used for carrying out feature extraction again; and finally, inputting the to-be-detected wafer image preprocessed in the step S1 into the trained lightweight multi-scale wafer defect detection model, and carrying out wafer defect detection. According to the invention, the wafer defect detection efficiency and the wafer defect type classification accuracy are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor detection, and more specifically relates to a wafer defect detection method and system based on a lightweight multi-scale wafer defect detection model. Background Art

[0002] With the continuous advancement of semiconductor manufacturing technology, the semiconductor manufacturing industry has an increasing demand for wafer materials. At the same time, the quality requirements for wafer materials are also getting higher and higher. The wafer production process is very complicated, and various defects will occur during the wafer production process, such as edge defects, center defects, and random defects. Wafer surface defects can significantly affect the yield and performance of semiconductor chips. Therefore, accurately identifying these defects is crucial to ensuring chip production quality.

[0003] Traditional defect detection relies on engineers to analyze defects in images through visual inspection. However, this manual method is inefficient when faced with massive amounts of data and is easily affected by subjective factors, resulting in missed detection or misjudgment. Moreover, as production lines expand, manual inspection alone can no longer meet the needs of efficient production. It is time-consuming, labor-intensive, and costly. In order to meet these challenges, the industry has begun to explore more efficient detection methods to improve the accuracy of defect identification and reduce operating costs.

[0004] In recent years, the rise of deep learning technology has provided new solutions for wafer defect detection. Defect detection models based on convolutional neural networks can automatically learn complex features in images and classify multiple defect types. In existing defect detection models, residual blocks are added to traditional convolutional neural networks to deepen the network depth and improve the feature extraction capability of convolutional neural networks. By alleviating the gradient vanishing problem, convolutional neural networks are more stable during training and easier to achieve better performance. Adding residual blocks will deepen the number of network layers, resulting in increased parameters and calculations in the defect detection process, reducing defect detection efficiency. At the same time, due to the imbalance of wafer defect data, the distribution of feature information of different types of wafer images in space and position is quite different, resulting in differences in the recognition effect of existing defect detection models on different defect types. The classification accuracy of some rare defect patterns is low, affecting the efficiency of wafer defect detection and the accuracy of classification. Summary of the invention

[0005] In order to solve the problems of low efficiency of wafer defect detection and insufficient classification accuracy of the current wafer defect detection model, the present invention proposes a wafer defect detection method based on a lightweight multi-scale wafer defect detection model to improve the efficiency of wafer defect detection and the accuracy of classification.

[0006] In order to achieve the above technical effects, the technical solution of the present invention is as follows:

[0007] S1: Acquire the wafer image to be inspected and perform preprocessing;

[0008] S2: construct and train a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module for performing multi-scale feature extraction based on the initial wafer image feature extraction and fusing it with the initial wafer image feature, a CNN feature extraction module for secondary feature extraction, and a defect classification module;

[0009] S3: Input the wafer image to be inspected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

[0010] Furthermore, in step S1, the preprocessing operation includes: filtering processing and image data enhancement.

[0011] Further, the Stem-Dense feature extraction module includes a first Stem feature extraction unit;

[0012] The first Stem feature extraction unit includes: a first Conv layer, a second Conv layer, a third Conv layer, a first Max Pooling layer, a first Concatenate layer, and a fourth Conv layer; the output end of the first Conv layer is respectively connected to the input ends of the second Conv layer and the first Max Pooling layer, the output end of the second Conv layer is connected to the input end of the third Conv layer, the output ends of the third Conv layer and the first Max Pooling layer are both connected to the input end of the first Concatenate layer, and the output end of the first Concatenate layer is connected to the input end of the fourth Conv layer.

[0013] Furthermore, the Stem-Dense feature extraction module further includes a first Dense Block feature extraction unit;

[0014] The first Dense Block feature extraction unit includes a fifth Conv layer, a sixth Conv layer, a second MaxPooling layer and a second Concatenate layer; the output end of the fifth Conv layer is connected to the input end of the sixth Conv layer, and the output ends of the sixth Conv layer and the second Max Pooling layer are both connected to the input end of the second Concatenate layer.

[0015] According to the above technical means, a lightweight architecture is used to perform initial feature extraction on the input wafer image. While reducing the computational complexity, preliminary feature information is efficiently extracted from the wafer image, thereby improving the efficiency of wafer defect detection and the accuracy of classification.

[0016] Furthermore, the multi-scale feature extraction fusion module includes: a first Conv1-SE unit, a second Conv1-SE unit, a third Conv1-SE unit and a first Upsampling unit connected in sequence; a fourth Conv1-SE unit, a fifth Conv1-SE unit and a second Upsampling unit connected in sequence; a sixth Conv1-SE unit and a third Upsampling unit connected in sequence; a fourth Upsampling unit; the output ends of the first Upsampling unit, the second Upsampling unit, the third Upsampling unit and the fourth Upsampling unit are all connected to the input end of the third Concatenate unit.

[0017] Furthermore, any one of the first Conv1-SE unit, the second Conv1-SE unit, the third Conv1-SE unit, the fourth Conv1-SE unit, the fifth Conv1-SE unit and the sixth Conv1-SE unit includes: a seventh Conv layer, a first ReLU layer, a first Batch Normal layer, a third Max Pooling layer, an eighth Conv layer, a second ReLU layer, a second Batch Normal layer and a first SE-Attention layer connected in sequence.

[0018] Furthermore, the first SE-Attention layer includes: a first Global Pooling operation, a first Fully Connected operation, a third ReLU operation, a second Fully Connected operation and a first Sigmol operation connected in sequence; the output end of the second Batch Normal operation and the output end of the first Sigmol module are both connected to the input end of the first Scale operation.

[0019] According to the above technical means, the multi-scale feature extraction and fusion module can capture the feature information of different scales in the wafer image, and enhance the correlation between features by fusing with the initial wafer image features, thus improving the model's ability to identify complex defects. At the same time, the SE-Attention layer is added to adaptively adjust the weights of each feature channel, so that the lightweight multi-scale wafer defect detection model pays more attention to key defect information, suppresses irrelevant features, enhances the representation ability of features, and further improves detection performance.

[0020] Further, the CNN feature extraction module includes: a first Conv2-SE unit, a second Conv2-SE unit and a third Conv2-SE unit connected in sequence;

[0021] Any Conv2-SE module among the first Conv2-SE unit, the second Conv2-SE unit and the third Conv2-SE unit includes: a ninth Conv layer, a fourth ReLU layer, a third Batch Normal layer, a fourth MaxPooling layer, an eighth Conv layer, a fifth ReLU layer, a fourth Batch Normal layer and a second SE-Attention layer connected in sequence.

[0022] Furthermore, the defect classification module includes: a first SPatial-DropOut unit, a first Flatten unit, a first Dense unit and a first SoftMax unit connected in sequence.

[0023] The present invention also provides a wafer defect detection system based on a lightweight multi-scale wafer defect detection model, comprising:

[0024] A data processing module, used to obtain the image of the wafer to be inspected and perform preprocessing;

[0025] A model building training module is used to build and train a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module that performs multi-scale feature extraction based on the initial wafer image feature extraction and fuses it with the initial wafer image feature, a CNN feature extraction module for secondary feature extraction, and a defect classification module;

[0026] The detection module is used to input the wafer image to be detected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

[0027] Compared with the prior art, the beneficial effects of this method are:

[0028] The present invention proposes a wafer defect detection method and system based on a lightweight multi-scale wafer defect detection model. First, the wafer image to be detected is obtained and preprocessed, and then the lightweight multi-scale wafer defect detection model is constructed and trained. Finally, the preprocessed wafer image to be detected is input into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection. Among them, the Stem-Dense feature extraction module in the lightweight multi-scale wafer defect detection model uses a lightweight architecture to efficiently extract preliminary feature information from the wafer image while reducing the computational complexity. The multi-scale feature extraction fusion module can capture feature information of different scales in the wafer image, and by fusing with the initial wafer image features, the correlation between features is enhanced, and the model's ability to recognize complex defects is improved. The present invention adopts a lightweight multi-scale wafer defect detection model as a whole to improve the efficiency of wafer defect detection and the accuracy of classification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A flowchart showing a wafer defect detection method based on a lightweight multi-scale wafer defect detection model proposed in an embodiment of the present invention;

[0030] Figure 2 An example diagram showing a wafer image of a WM-811K data set used in an embodiment of the present invention;

[0031] Figure 3 An example diagram showing a wafer image after filtering of a WM-811K data set used in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram showing the overall structure of a lightweight multi-scale wafer defect detection model proposed in an embodiment of the present invention;

[0033] Figure 5 A schematic diagram showing the structure of a Stem-Dense feature extraction module proposed in an embodiment of the present invention;

[0034] Figure 6 A schematic diagram showing the structure of a first Stem feature extraction unit proposed in an embodiment of the present invention;

[0035] Figure 7 A schematic diagram showing the structure of a first Dense Block feature extraction unit proposed in an embodiment of the present invention;

[0036] Figure 8 A schematic diagram showing the structure of a Conv1-SE unit proposed in an embodiment of the present invention;

[0037] Fig. 9 A schematic diagram showing the structure of the first SE-Attention layer proposed in an embodiment of the present invention;

[0038] Fig.10 A schematic diagram showing the structure of a Conv2-SE unit proposed in an embodiment of the present invention;

[0039] Fig.11 A structural diagram showing a wafer defect detection system based on a lightweight multi-scale wafer defect detection model proposed in an embodiment of the present invention;

[0040] Fig.12 The figure shows the test results of the lightweight multi-scale wafer defect detection model proposed in the embodiment of the present invention. DETAILED DESCRIPTION

[0041] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0042] In order to better illustrate the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the actual size;

[0043] It is understandable to those skilled in the art that descriptions of certain well-known contents in the drawings may be omitted.

[0044] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0045] The positional relationships described in the drawings are only for illustrative purposes and should not be construed as limiting the present patent;

[0046] Example 1

[0047] This embodiment proposes a wafer defect detection method based on a lightweight multi-scale wafer defect detection model. Figure 1 The flowchart of the method shown in FIG. 1 generally includes the following steps:

[0048] S1: Acquire the wafer image to be inspected and perform preprocessing;

[0049] S2: construct and train a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module for performing multi-scale feature extraction based on the initial wafer image feature extraction and fusing it with the initial wafer image feature, a CNN feature extraction module for secondary feature extraction, and a defect classification module;

[0050] S3: Input the wafer image to be inspected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

[0051] This embodiment first obtains the wafer image to be detected and preprocesses it, then builds and trains a lightweight multi-scale wafer defect detection model, and finally inputs the preprocessed image into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection. Using the method proposed in this embodiment to detect wafer images can improve the efficiency of detection and accurately classify wafer defect types.

[0052] Example 2

[0053] This embodiment specifically describes the wafer defect detection method based on the lightweight multi-scale wafer defect detection model proposed in Embodiment 1:

[0054] In this implementation, the wafer images use images from the WM-811K dataset, such as Figure 2 An example image of a wafer image from the WM-811K dataset is shown. The WM-811K dataset is a large public dataset for semiconductor manufacturing and research. The dataset consists of 811,457 wafer images, including 172,950 labeled images. These images cover a variety of wafer defect categories, such as local, random, nearly full, scratches, and other defect categories.

[0055] The wafer image to be inspected is preprocessed including filtering and image data enhancement. The median filtering method is used to filter the wafer image to suppress image noise and enhance image details, such as Figure 3 The wafer image shown is after filtering. Image data enhancement includes vertical or horizontal flipping of the image, vertical or horizontal movement of the image, rotation and scaling of the image. By performing image transformation on the wafer image, the model's recognition ability for minority wafer defect images is improved.

[0056] The composition of the lightweight multi-scale wafer defect detection model is described in detail below. In this embodiment, Figure 4 The overall structural diagram of the lightweight multi-scale wafer defect detection model is shown. The lightweight multi-scale wafer defect detection model consists of four modules: Stem-Dense feature extraction module, multi-scale feature extraction fusion module, CNN feature extraction and defect classification module.

[0057] like Figure 5 The structural schematic diagram of the Stem-Dense feature extraction module shown in the figure includes a first Stem feature extraction unit, a first Dense Block feature extraction unit and a first Transition unit.

[0058] like Figure 6The structural schematic diagram of the first Stem feature extraction unit shown in the figure includes: a first Conv layer, a second Conv layer, a third Conv layer, a first Max Pooling layer, a first Concatenate layer, and a fourth Conv layer; the output end of the first Conv layer is respectively connected to the input ends of the second Conv layer and the first Max Pooling layer, the output end of the second Conv layer is connected to the input end of the third Conv layer, the output ends of the third Conv layer and the first Max Pooling layer are both connected to the input end of the first Concatenate layer, and the output end of the first Concatenate layer is connected to the input end of the fourth Conv layer.

[0059] The image of size 224×224×3 is first input into the first Conv layer with stride 2, padding method same, convolution kernel size 3×3, and number of convolution kernels 32, and outputs a feature map of size 112×112×32. Then the feature map of size 112×112×32 is input into the second Conv layer with stride 2, convolution kernel size 1×1, and number of convolution kernels 16, and the first Max Pooling layer with stride 2 and convolution kernel size 2×2, and outputs feature maps of size 112×112×16 and 56×56×32 respectively. The feature map of size 112×112×16 is input into the third Conv layer with stride 2, padding method same, convolution kernel size 3×3, and number of convolution kernels 32, and outputs a feature map of size 56×56×32. The two sets of 56×56×32 feature maps are input into the first Concatenate layer to fuse and output a feature map of size 56×56×64; finally, the fused feature map is input into the fourth Conv layer with a stride of 2, a convolution kernel size of 1×1, and 32 convolution kernels to obtain an output feature map of 56×56×32.

[0060] In this embodiment, the expression of any one of the first Conv layer, the second Conv layer, the third Conv layer and the fourth Conv layer is:

[0061] X CONV =Conv2D(X ReLU ,k,k,f)

[0062] Where, X CONV Represents the output of the Conv layer, Conv2D(X ReLU ,k,k,f) represents the convolution operation, k represents the convolution kernel size, f represents the number of output channels, and ReLU represents the LeakyReLu activation function.

[0063] like Figure 7The structural schematic diagram of the first Dense Block feature extraction unit shown in the figure includes a fifth Conv layer, a sixth Conv layer, a second Max Pooling layer and a second Concatenate layer; the output end of the fifth Conv layer is connected to the input end of the sixth Conv layer, and the output ends of the sixth Conv layer and the second Max Pooling layer are both connected to the input end of the second Concatenate layer.

[0064] The feature map of size 56×56×32 obtained by the first Stem feature extraction unit is input into the first Dense Block feature extraction unit, and the first branch keeps the feature map of size 56×56×32 unchanged; the second branch inputs the feature map into the fifth Conv layer with a step size of 1, a padding method of the same, a convolution kernel size of 1×1, and a number of convolution kernels of 64, and outputs a feature map of size 56×56×64, and then inputs it into the sixth Conv layer with a step size of 1, a padding method of the same, a convolution kernel size of 3×3, and a number of convolution kernels of 32, and outputs a feature map of size 56×56×32; the third branch inputs the feature map into the second Max Pooling layer with a step size of 2 and a convolution kernel size of 2×2, and outputs a feature map of size 56×56×32, and the feature maps of the three branches are input into the second Concatenate layer for Concatenate fusion to obtain an output feature map of 56×56×96.

[0065] The first Transition unit includes a normalization layer BN, an activation function layer RELU (Rectified Linear Unit), and a convolution layer. The first Transition unit reduces the number of channels and spatial size of the feature map, thereby reducing the computational complexity of subsequent layers while maintaining the ability to extract important features.

[0066] For input features Figure X (Shape is H×W×C), the normalized BN process is as follows:

[0067] X BN =BatchNorm(X)

[0068] In the formula, BatchNorm(·) represents the normalization operation, X BN Represents the normalized feature map.

[0069] The normalized feature map will be transformed nonlinearly through the ReLU activation function:

[0070] X ReLU =ReLU(X BN )

[0071] In the formula, ReLU(·) represents the ReLU activation function, X ReLU Represents the feature map after the activation function.

[0072] In this embodiment, the multi-scale feature extraction fusion module includes: a first Conv1-SE unit, a second Conv1-SE unit, a third Conv1-SE unit and a first Upsampling unit connected in sequence; a fourth Conv1-SE unit, a fifth Conv1-SE unit and a second Upsampling unit connected in sequence; a sixth Conv1-SE unit and a third Upsampling unit connected in sequence; a fourth Upsampling unit; the output ends of the first Upsampling unit, the second Upsampling unit, the third Upsampling unit and the fourth Upsampling unit are all connected to the input end of the third Concatenate unit.

[0073] like Figure 8 The structural schematic diagram of the Conv1-SE unit shown in the figure, any one of the first Conv1-SE unit, the second Conv1-SE unit, the third Conv1-SE unit, the fourth Conv1-SE unit, the fifth Conv1-SE unit and the sixth Conv1-SE unit includes: a seventh Conv layer, a first ReLU layer, a first Batch Normal layer, a third Max Pooling layer, an eighth Conv layer, a second ReLU layer, a second Batch Normal layer and a first SE-Attention layer connected in sequence.

[0074] like Fig. 9 The structural schematic diagram of the first SE-Attention layer is shown, and the first SE-Attention layer includes: a first Global Pooling operation, a first Fully Connected operation, a third ReLU operation, a second Fully Connected operation and a first Sigmol operation connected in sequence; the output end of the second Batch Normal operation and the output end of the first Sigmol module are both connected to the input end of the first Scale operation.

[0075] The specific operation process of the first SE-Attention layer is as follows: the first path keeps the original feature map unchanged, the second path first inputs the first Global Pooling operation for pooling operation, and then inputs the pooling result into the first Fully Connected operation for full connection, and then after activation by the third ReLU operation, inputs the second Fully Connected operation for full connection, and then inputs the fully connected result into the first Sigmol operation to obtain a feature map of the same size as the original input, and the obtained feature map is scaled with the first input feature map, and finally a compressed and excited feature map is obtained.

[0076] The CNN feature extraction module includes: a first Conv2-SE unit, a second Conv2-SE unit, and a third Conv2-SE unit connected in sequence;

[0077] like Fig.10 The structural schematic diagram of the Conv2-SE unit shown in the figure shows that any Conv2-SE module in the first Conv2-SE unit, the second Conv2-SE unit and the third Conv2-SE unit includes: a ninth Conv layer, a fourth ReLU layer, a third Batch Normal layer, a fourth Max Pooling layer, an eighth Conv layer, a fifth ReLU layer, a fourth BatchNormal layer and a second SE-Attention layer connected in sequence.

[0078] The feature map with a size of 56×56×240 output by the third Concatenate unit is input into Conv2-SE for three convolution feature extractions. The convolution kernel sizes are 64, 64, and 128 respectively, and the feature map with an output size of 14×14×128 is obtained.

[0079] The defect classification module includes: a first SPatial-DropOut unit, a first Flatten unit, a first Dense unit and a first SoftMax unit connected in sequence.

[0080] The feature map with an output size of 14×14×128 is input into the first Spatial-Dropout unit for regularization, and then the feature map of 7×7×128 output by the first Spatial-Dropout unit is input into the first Flatten unit for flattening. The feature map with an output size of 6272 of the first Flatten unit is input into the first Dense unit to obtain a feature map of size 512, and finally input into the first SoftMax unit for 9 classifications.

[0081] The regularization process of the first Spatial-Dropout unit satisfies:

[0082] Set the probability of discarding the feature map to p, the probability of retaining it to 1-p, and for each channel C (C = 1, 2, ..., C), randomly select the retained channel. This process can be done by generating a binary mask:

[0083]

[0084] Where M C Indicates the value of the mask in the Cth channel

[0085] The output of the first Dense unit satisfies:

[0086] y=Wx+b

[0087] Among them, x represents the flattened feature map input vector, W represents the weight matrix, b represents the bias vector, and y represents the output vector.

[0088] The first SoftMax unit converts the output of the first Dense unit into a probability distribution. Its output value ranges between 0 and 1, and the sum of all outputs is 1. Its formula can be expressed as

[0089]

[0090] Where σ(z) j represents the output probability of the jth class, z j represents the j-th output of the first Dense unit, and m represents the number of output categories.

[0091] Example 3

[0092] like Fig.11 In the embodiment of the present invention, a wafer defect detection system based on a lightweight multi-scale wafer defect detection model is proposed:

[0093] A data processing module, used to obtain the image of the wafer to be inspected and perform preprocessing;

[0094] A model building training module is used to build and train a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module that performs multi-scale feature extraction based on the initial wafer image feature extraction and fuses it with the initial wafer image feature, a CNN feature extraction module for secondary feature extraction, and a defect classification module;

[0095] The detection module is used to input the wafer image to be detected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

[0096] Example 4

[0097] In this embodiment, when training the lightweight multi-scale wafer defect detection model, the basic platform and parameters are as follows:

[0098] The TensorFlow framework was used to build the network. The experimental environment included Windows 11 operating system, Cuda 11.8, Python 3.9, and TensorFlow 2.9.1. The hardware platform was NVIDIA RTX 4090 GPU. The training setting learning rate was 1e-3, the batch size was 100, and the size of the experimental image input was 224×224×3. 40 epochs were performed during the network training process, and the Adam gradient optimizer was selected as the optimizer. The preprocessed wafer images were divided into training set, validation set, and test set in a ratio of 16:3:3. The training set was used to train the lightweight multi-scale wafer defect detection model. During the training process, the validation set was used to verify the effectiveness of the lightweight multi-scale wafer defect detection model, and the trained lightweight multi-scale wafer defect detection model was obtained.

[0099] The trained lightweight multi-scale wafer defect detection model is tested on the test set, the test results are compared with the true labels, and the accuracy, precision, recall rate, and F1 score are calculated to verify the recognition accuracy of the model.

[0100] Accuracy refers to the ratio of the number of samples correctly predicted by the model to the total number of samples. The calculation expression is:

[0101]

[0102] Precision refers to the proportion of all true positive samples that are correctly predicted as positive samples by the model. The calculation expression is:

[0103]

[0104] Recall refers to the proportion of samples that are actually positive among the samples predicted by the model to be positive samples. The calculation expression is:

[0105]

[0106] F1-score refers to the harmonic mean of precision and recall, which is used to comprehensively consider the performance of both. The calculation expression is:

[0107]

[0108] In the formula, TP represents the number of samples predicted to be positive but actually are positive samples, FP represents the number of samples predicted to be positive but actually are negative samples, TN represents the number of samples predicted to be negative but actually are negative samples, FN represents the number of samples predicted to be negative but actually are positive samples, and the F1 score represents a weighted average of precision and recall.

[0109] The accuracy, precision, recall and F1-score of different models in detecting wafer defects on the WM-811K dataset are compared. The comparison results are shown in Table 1:

[0110] Table 1

[0111]

[0112] FLOPS provides a standardized way to quantify the computational complexity of a model. Comparing the FLOPS of different models can provide an understanding of computational efficiency. If the performance (such as accuracy) of two models is similar, the model with lower FLOPS is usually more efficient and achieves the same performance with fewer computing resources. Models with more parameters require computational complexity. The FLOPS and parameter count of different models for wafer defect detection on the WM-811K dataset are compared, and the comparison results are shown in Table 2:

[0113] Table 2

[0114]

[0115] like Fig.12 The test results of the lightweight multi-scale wafer defect detection model shown in the figure show that the lightweight multi-scale wafer defect detection model improves the efficiency of wafer defect detection and the accuracy of classification when detecting wafer defects.

[0116] The embodiments are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A wafer defect detection method based on a lightweight multi-scale wafer defect detection model, characterized in that: The following steps are involved: S1: Acquire the wafer image to be inspected and perform preprocessing; S2: construct and train a lightweight multi-scale wafer defect detection model; the lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module for performing multi-scale feature extraction based on the initial wafer image feature extraction and fusing it with the initial wafer image feature, a CNN feature extraction module for secondary feature extraction, and a defect classification module; S3: Input the wafer image to be inspected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

2. According to claim 1, a wafer defect detection method based on a lightweight multi-scale wafer defect detection model is characterized in that: In step S1, the preprocessing operations include: filtering and image data enhancement.

3. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 1, characterized in that: The Stem-Dense feature extraction module includes a first Stem feature extraction unit; The first Stem feature extraction unit includes: a first Conv layer, a second Conv layer, a third Conv layer, a first MaxPooling layer, a first Concatenate layer, and a fourth Conv layer; the output end of the first Conv layer is respectively connected to the input ends of the second Conv layer and the first Max Pooling layer, the output end of the second Conv layer is connected to the input end of the third Conv layer, the output ends of the third Conv layer and the first Max Pooling layer are both connected to the input end of the first Concatenate layer, and the output end of the first Concatenate layer is connected to the input end of the fourth Conv layer.

4. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 3 is characterized in that: The Stem-Dense feature extraction module also includes a first Dense Block feature extraction unit; The first Dense Block feature extraction unit includes a fifth Conv layer, a sixth Conv layer, a second MaxPooling layer and a second Concatenate layer; the output end of the fifth Conv layer is connected to the input end of the sixth Conv layer, and the output ends of the sixth Conv layer and the second Max Pooling layer are both connected to the input end of the second Concatenate layer.

5. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 1, characterized in that: The multi-scale feature extraction and fusion module includes: a first Conv1-SE unit, a second Conv1-SE unit, a third Conv1-SE unit and a first Upsampling unit connected in sequence; a fourth Conv1-SE unit, a fifth Conv1-SE unit and a second Upsampling unit connected in sequence; a sixth Conv1-SE unit and a third Upsampling unit connected in sequence; a fourth Upsampling unit; the output ends of the first Upsampling unit, the second Upsampling unit, the third Upsampling unit and the fourth Upsampling unit are all connected to the input end of the third Concatenate unit.

6. The wafer defect detection method based on the LMP-WDD-NET model according to claim 5, characterized in that: Any one of the first Conv1-SE unit, the second Conv1-SE unit, the third Conv1-SE unit, the fourth Conv1-SE unit, the fifth Conv1-SE unit and the sixth Conv1-SE unit includes: a seventh Conv layer, a first ReLU layer, a first Batch Normal layer, a third Max Pooling layer, an eighth Conv layer, a second ReLU layer, a second Batch Normal layer and a first SE-Attention layer connected in sequence.

7. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 6, characterized in that: The first SE-Attention layer includes: a first Global Pooling operation, a first Fully Connected operation, a third ReLU operation, a second Fully Connected operation and a first Sigmol operation connected in sequence; the output end of the second Batch Normal operation and the output end of the first Sigmol module are both connected to the input end of the first Scale operation.

8. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 1, characterized in that: The CNN feature extraction module includes: a first Conv2-SE unit, a second Conv2-SE unit and a third Conv2-SE unit connected in sequence; Any Conv2-SE module among the first Conv2-SE unit, the second Conv2-SE unit and the third Conv2-SE unit includes: a ninth Conv layer, a fourth ReLU layer, a third Batch Normal layer, a fourth Max Pooling layer, an eighth Conv layer, a fifth ReLU layer, a fourth Batch Normal layer and a second SE-Attention layer connected in sequence.

9. The wafer defect detection method based on a lightweight multi-scale wafer defect detection model according to claim 1, characterized in that: The defect classification module includes: a first SPatial-DropOut unit, a first Flatten unit, a first Dense unit and a first SoftMax unit which are connected in sequence.

10. A wafer defect detection system based on a lightweight multi-scale wafer defect detection model, characterized in that: include: A data processing module, used to obtain the image of the wafer to be inspected and perform preprocessing; Model building and training module, used to build and train lightweight multi-scale wafer defect detection models; The lightweight multi-scale wafer defect detection model includes: a lightweight Stem-Dense feature extraction module for initial wafer image feature extraction, a multi-scale feature extraction fusion module for performing multi-scale feature extraction based on the initial wafer image feature extraction and fusing it with the initial wafer image features, a CNN feature extraction module for secondary feature extraction, and a defect classification module; The detection module is used to input the wafer image to be detected after preprocessing in step S1 into the trained lightweight multi-scale wafer defect detection model to perform wafer defect detection.

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