Display device and display terminal

Abstract

The embodiment of the present application provides a display device and a display terminal, the display device comprises: a circuit board and a display driving chip; at least one target wire is embedded in the circuit board, a target test point on the target wire is arranged between two ends of the target wire and located on the surface of the circuit board, the target test point is covered with an insulating layer, and each target wire is connected with at least one output end of the display driving chip; after the insulating layer covering the target test point of any target wire is scraped off and the any target wire is disconnected from the position where the target test point is arranged, the output end connected with the any target wire in the display driving chip works abnormally. Therefore, the reverse analysis protection of the display device is realized, and the difficulty of reverse analysis of the display device is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display device and a display terminal. BACKGROUND

[0002] Display devices are widely used in mobile phones, televisions, notebook computers, desktop computers, wearable devices and various smart devices. With the rapid iteration of display technologies applied to display devices, the protection of display technologies is becoming increasingly important.

[0003] However, the protection of display technologies applied to display devices needs to be improved. SUMMARY

[0004] Therefore, embodiments of the present application provide a display device and a display terminal to at least partially solve the above problems.

[0005] According to a first aspect of embodiments of the present application, a display device is provided, comprising: a circuit board and a display driving chip; at least one target wire is embedded in the circuit board, a target test point on the target wire is arranged between two ends of the target wire and located on a surface of the circuit board, the target test point is covered with an insulating layer, and each target wire is connected to at least one output end of the display driving chip; after the insulating layer covering any target test point of any target wire is scraped off and the any target wire is disconnected from the position where the target test point is arranged, the output end of the display driving chip connected to the any target wire works abnormally.

[0006] According to a second aspect of embodiments of the present application, a display terminal is provided, comprising a terminal device body and a display device as described in the first aspect arranged on the terminal device body.

[0007] According to the display device provided by the embodiments of the present application, by arranging the target wire and the target test point, when the display device is reverse analyzed and the insulating layer of any target test point is scraped off, the target test point is small, and the target test point is arranged between the two ends of the corresponding target wire, so that the target wire is basically disconnected from the position where the target test point is arranged, so that the output end of the display driving chip connected to the target wire works abnormally, thereby achieving reverse analysis protection of the display device and improving the difficulty of reverse analysis of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art based on these drawings.

[0009] Figure 1 is a structural schematic diagram of a display device according to an embodiment of the present application;

[0010] Figure 2 is a structural schematic diagram of a display device according to another embodiment of the present application;

[0011] Figure 3 is a partial circuit diagram of a display device according to an embodiment of the present application;

[0012] Figure 4 is a partial circuit diagram of a display device according to another embodiment of the present application;

[0013] Figure 5 is a partial circuit diagram of a display device according to still another embodiment of the present application;

[0014] Figure 6 is a structural schematic diagram of a display terminal according to an embodiment of the present application.

[0015] Explanation of reference signs:

[0016] 1, circuit board; 2, display driving chip; 3, screen body; 31, first sub-screen; 32, second sub-screen. DETAILED DESCRIPTION

[0017] In order to make the technical solutions in the embodiments of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art should belong to the scope of protection of the embodiments of the present application.

[0018] The terms used in the embodiments of the present application are merely for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the embodiments of the present application means and includes any or all possible combinations of one or more associated listed items.

[0019] It should be understood that, in the description of the embodiments of the present application, the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship, and are only for the convenience of describing the solutions of the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the embodiments of the present application.

[0020] In addition, when an element or layer is referred to as being "on" or "connected to" or "joined to" another element or layer, it can be directly on, or directly connected to, or directly joined to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on", "directly connected to" or "directly joined to" another element or layer, there is no intervening element or layer present.

[0021] The terms first, second, etc. are used to describe various elements, components, regions, layers and / or sections, but these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section.

[0022] Unless otherwise clearly specified and limited, the terms "mount", "connect", "connection", "fixed", and the like should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0023] The specific implementation of the embodiments of the present application will be further described below in combination with the drawings of the embodiments of the present application.

[0024] Figure 1 is a structural schematic diagram of a display device according to an embodiment of the present application. As shown in the figure, Figure 1As shown, the display device comprises a circuit board 1 (for example, the circuit board 1 can be a flexible circuit board 1, etc.) and a display driving chip 2 (Display Driver Integrated Circuit, DDI C); at least one target wire is embedded in the circuit board 1, a target test point on the target wire is arranged between two ends of the target wire and located on the surface of the circuit board 1, an insulating layer is covered on the target test point, and each target wire is connected with at least one output end of the display driving chip 2; after the insulating layer covering the target test point of any target wire is scraped off and any target wire is disconnected from the position where the target test point is arranged, the output end of the display driving chip 2 connected with any target wire works abnormally.

[0025] Wherein, the display driving chip 2 is connected with the circuit board 1, the display driving chip 2 is used to control the screen body 3 of the display device to work through the signal (for example, the timing signal or the voltage signal, etc.) output by the output end of the display driving chip 2, the circuit board 1 is used to provide the peripheral circuit for the display driving chip 2, so as to carry out the voltage stabilization or filtering treatment on at least part of the output signal of the display driving chip 2, or is used to detect the working state of at least part of the port of the display driving chip 2, etc., the specific functions of the display driving chip 2 and the circuit board 1 are not limited in the embodiments of the present application; the target wire is a metal path on the circuit board 1 for transmitting electric signal; the target test point and the non-target test point in the following are both test points arranged on the circuit board 1, the test points arranged on the circuit board 1 can generally be pads or terminals, etc., which are not limited in the present application.

[0026] It should be noted that when the display device is analyzed reversely to obtain the working principle of the display device, the insulating layer of each test point on the circuit board 1 is generally scraped off, but when the insulating layer of any target test point is scraped off, since the test points (including the target test points) on the circuit board 1 are generally small, and the target test point is arranged between the two ends of the corresponding target wire, the target wire will be basically disconnected from the position where the target test point is arranged.

[0027] In the embodiments of the present application, by arranging the target wire and the target test point, when the display device is analyzed reversely and the insulating layer of any target test point is scraped off, since the target test point is small, and the target test point is arranged between the two ends of the corresponding target wire and the target test point, the target wire will be basically disconnected from the position where the target test point is arranged, so that the output end of the display driving chip 2 connected with the target wire works abnormally, thereby realizing the reverse analysis protection of the display device and improving the difficulty of the reverse analysis of the display device.

[0028] Optionally, as Figure 1As shown, the display device further comprises a screen body 3, the circuit board 1 is connected with the screen body 3, and the display driving chip 2 is arranged on the screen body 3.

[0029] For example, as shown in Figure 1 and Figure 2 , the screen body 3 included in the display device can include a first sub-screen 31 and a second sub-screen 32, the first sub-screen 31 is used for display, the second sub-screen 32 is connected with the circuit board 1 at an end away from the first sub-screen 31, and the circuit board 1 is connected on the second sub-screen 32; the screen body 3 is usually integrally formed, after obtaining the integrally formed screen body 3, the second sub-screen 32 can be bent to the back of the first sub-screen 31 relative to the first sub-screen 31 to obtain the screen body 3 after bending processing, the screen body 3 before bending can be as shown in the screen body 3 in Figure 2 , and the screen body 3 after bending can be as shown in the screen body 3 in Figure 1 .

[0030] Based on this, the at least one target wire can include a first target wire and / or a second target wire, that is, the display device can have at least two possible implementation manners as follows:

[0031] In a possible implementation manner, as shown in Figure 1 and Figure 3 , the at least one target wire includes a first target wire (such as the wire A in Figure 3 ), the display driving chip 2 includes a first output port (such as the port n in Figure 3 ) for outputting a timing signal (for example, a Gate Driven on Array (GOA) timing signal) for driving the screen body 3 to display, and the first output port is specifically used for outputting a timing signal for driving the first sub-screen 31 to display, the circuit board 1 is provided with a non-target test point (such as m in Figure 3 ) corresponding to the first output port, a first switch circuit is connected between the first output port and the non-target test point, and the first target wire is connected with the first switch circuit; the first switch circuit is used for conducting between the first output port and the non-target test point when the first target wire is not disconnected from the target test point (such as M1 in Figure 3 ), and is used for turning off between the first output port and the non-target test point after the first target wire is disconnected from the target test point.

[0032] The display driver chip 2 may include one or more first output ports, each of which may have a corresponding non-target test point. The at least one target wire may include one or more first target wires. Generally, one or more target test points may be set on a single first target wire. In this embodiment, the number of first output ports, the number of first target wires, and the number of target test points on a single first target wire are not limited. For example, only one first target wire may be set, only one target test point may be set on the first target wire, and multiple first output ports may be set. The first switching circuit between each first output port and its corresponding non-target test point may be connected to the first target wire. The non-target test points are generally used for testing, measuring, or debugging the display device during the development or reverse engineering of the display device. The non-target test points are also covered with an insulating layer.

[0033] In this embodiment, by setting a first switching circuit, when the first target wire is not disconnected from the target test point, the first switching circuit is connected between the first output port and the non-target test point, so that there is a path between the first output port and the non-target test point. Thus, the first output port can transmit signals normally to the non-target test point, that is, the first output port is working normally. At this time, the signal output by the first output port can be detected through the non-target test point, thereby enabling testing, measurement, or debugging of the display device through the non-target test point. After the first target wire is disconnected from the target test point, the first switching circuit is turned off between the first output port and the non-target test point, so that there is no path (i.e., open circuit) between the first output port and the non-target test point. Thus, the first output port cannot transmit signals normally to the non-target test point, that is, the first output port is working abnormally. At this time, the signal output by the first output port cannot be detected through the non-target test point, thereby making it impossible to test, measure, or debug the display device through the non-target test point, and also increasing the difficulty of reverse engineering the display device.

[0034] Optionally, such as Figure 1 and Figure 3 As shown, the first end of the first target conductor (e.g.) Figure 3 a1) is connected to a first resistor (e.g. Figure 3 R1 in the first resistor); the first end of the first resistor is connected to the power supply and the second end of the first target wire (e.g., R1 in the first resistor); Figure 3 In the first circuit, a2) is grounded, or the first end of the first resistor is grounded and the second end of the first target wire is connected to a power source; the second end of the first resistor is the end where the first resistor is connected to the first end of the first target wire; the first switching circuit includes a first transistor (such as...). Figure 3In T1); the source of the first transistor is connected to the first output port and the drain of the first transistor is connected to a non-target test point, or the source of the first transistor is connected to a non-target test point and the drain of the first transistor is connected to the first output port; the gate of the first transistor is connected to the first end of the first target wire, or the gate of the first transistor is connected to any node between the first end of the first target wire and the target test point of the first target wire.

[0035] For example, such as Figure 3 As shown, the first end of the first resistor is connected to a power supply, and the second end of the first target wire is grounded. The first transistor is a PMOS (P-type metal-oxide semiconductor). Based on this, when the first target wire is not disconnected from the target test point, under the action of the grounding of the second end of the first target wire, the gate of the first transistor receives a low-level signal, and the source and drain of the first transistor are in a conducting state, so that the first transistor is turned on between the first output port and the non-target test point; after the first target wire is disconnected from the target test point, under the action of the power supply connected to the first resistor, the gate of the first transistor receives a high-level signal, and the source and drain of the first transistor are in a turning-off state, so that the first transistor is turned off between the first output port and the non-target test point.

[0036] Therefore, by using a transistor, the first switching circuit can be turned on between the first output port and the non-target test point when the first target wire is not disconnected from the target test point, and can also be turned off between the first output port and the non-target test point after the first target wire is disconnected from the target test point. The structure is simple and cost-effective.

[0037] Optionally, the first transistor is disposed in the display driver chip 2 or the screen 3.

[0038] Compared to circuit board 1, display driver chip 2 and screen 3 originally have some other transistors. Adding the first transistor to display driver chip 2 and screen 3 is easier to implement and improves the production efficiency of display device.

[0039] Optionally, such as Figure 1 As shown, test point areas (such as...) are set on circuit board 1. Figure 1 In the test area (TA), both target test points and non-target test points are set within the test point area.

[0040] Therefore, by setting both target test points and non-target test points within the test point area on circuit board 1, it becomes difficult for personnel performing reverse engineering of the display device to distinguish between non-target test points and target test points, thereby increasing the concealment of target test points and thus increasing the difficulty of reverse engineering the display device.

[0041] Optionally, the target test point and the non-target test point have the same structure and size, so that the target test point and the non-target test point have almost the same appearance, making it difficult for personnel performing reverse analysis of the display device to distinguish between the non-target test point and the target test point, thereby increasing the concealment of the target test point and thus increasing the difficulty of reverse analysis of the display device.

[0042] In another possible implementation, such as Figure 1 and Figure 4 As shown, the aforementioned at least one target conductor includes a second target conductor (such as...). Figure 4 and Figure 5 The display driver chip 2 includes a second output port (such as wire B in the diagram) for outputting a voltage signal to drive the screen 3 for display. Figure 4 port p and Figure 5 The second output port (port q) is specifically used to output the voltage signal driving the first sub-screen 31 for display. The second output port is connected to the second target wire, which is connected to a power supply. The second target wire is used when the target wire is not connected to the set target test point (e.g., ...). Figure 4 and Figure 5 When the circuit is disconnected at point M2, it blocks the interference of the power supply output voltage on the voltage signal output from the second output port, and is used to stop the interference of the power supply output voltage on the voltage signal output from the second output port when the second target wire is disconnected from the target test point.

[0043] The display driver chip 2 may include one or more second output ports, and the aforementioned at least one target wire may include one or more second target wires. Generally, one or more target test points may be set on a single second target wire. In this application embodiment, the number of second output ports, the number of second target wires, and the number of target test points on a single second target wire are not limited. For example, only one second target wire may be set, only one target test point may be set on the second target wire, and multiple second output ports may be set. Each second output port may be connected to the second target wire. In this application embodiment, no limitation is made in this regard.

[0044] In this embodiment of the application, when the second target wire is not disconnected from the target test point, it can block the interference of the voltage output by the power supply to the voltage signal output by the second output port, so that the second output port can work normally; after the second target wire is disconnected from the target test point, it stops blocking the interference of the voltage output by the power supply to the voltage signal output by the second output port, so that the second output port can work abnormally, which increases the difficulty of reverse engineering of the display device.

[0045] In one specific implementation, such as Figure 4 As shown, the first end of the second target conductor (e.g.) Figure 4b1) is connected to a second resistor (such as b1) Figure 4 In the diagram, R2), the first end of the second resistor is connected to the power supply, and the second end of the second resistor is the end that connects the second resistor to the second end of the second target wire. The second end of the second target wire (e.g., R2) Figure 4 b2) is grounded, and a second switching circuit is connected between the second output port and the power supply. The second target wire is connected to the second switching circuit. The second switching circuit is used to turn off the connection between the second output port and the power supply when the second target wire is not disconnected from the target test point, and to turn on the connection between the second output port and the power supply after the second target wire is disconnected from the target test point.

[0046] In this embodiment, by setting a second switching circuit connected to the second target wire, when the first target wire is not disconnected from the target test point, the second switching circuit is turned off between the first output port and the non-target test point, so that there is no path (i.e., open circuit) between the second output port and the power supply. Therefore, the voltage output by the power supply will not interfere with the voltage signal output by the second output port, meaning the second output port works normally. After the first target wire is disconnected from the target test point, the second switching circuit is turned on between the second output port and the power supply, so that there is a path between the second output port and the power supply. Therefore, the voltage output by the power supply will interfere with the voltage signal output by the second output port. Thus, the second switching circuit can block and stop the interference of the power supply output voltage on the voltage signal output by the second output port without relying on other specific components connected to the second switching circuit, making it more versatile.

[0047] Optionally, such as Figure 4 As shown, the second switching circuit includes a second transistor (such as...). Figure 4 (T2 in the second transistor); the source of the second transistor is connected to the second output port and the drain of the second transistor is connected to the power supply, or the source of the second transistor is connected to the power supply and the drain of the second transistor is connected to the second output port; the gate of the second transistor is connected to the first end of the second target wire.

[0048] For example, such as Figure 4 As shown, the second transistor is an NMOS (N-type metal-oxide-semiconductor). Based on this, when the second target wire is not disconnected from the target test point, the gate of the second transistor receives a low-level signal due to the grounding of the second end of the second target wire. The source and drain of the second transistor are in a turn-off state, so that the second transistor is turned off between the second output port and the power supply. After the second target wire is disconnected from the target test point, the gate of the second transistor receives a high-level signal due to the power supply connected by the second resistor. The source and drain of the second transistor are in a conduction state, so that the second transistor is turned on between the second output port and the power supply.

[0049] Therefore, by using a transistor, the second switching circuit can be turned off between the second output port and the power supply when the second target wire is not disconnected from the target test point, and can also be turned on between the second output port and the power supply after the second target wire is disconnected from the target test point. The structure is simple and cost-effective.

[0050] Optionally, the second transistor is disposed in the display driver chip 2 or the screen 3.

[0051] Compared to circuit board 1, display driver chip 2 and screen 3 originally have some other transistors. Adding a second transistor to display driver chip 2 and screen 3 is easier to implement and improves the production efficiency of display devices.

[0052] In another specific implementation, such as Figure 5 As shown, the first end of the second target conductor (e.g.) Figure 5 b1) is connected to a third resistor (such as b1) Figure 5 In the diagram, R3), the first end of the third resistor is connected to the power supply, and the second end of the third resistor is the end that connects the third resistor to the second end of the second target wire. The second end of the second target wire (e.g., R3) Figure 5 b2) Grounding; The circuit board 1 is provided with a target device for filtering or regulating the signal output from the second output port. The first end of the target device is connected to the second output port, and the second end of the target device is connected to the first end of the second target wire. The target device is used to work normally when the second end of the target device is grounded, and to work abnormally when the second end of the target device is not grounded.

[0053] The target device is a filter capacitor or a voltage regulator capacitor (such as...). Figure 5 The present application does not limit the scope of C2), etc., and the target device can generally be set in the device area DA on the circuit board 1.

[0054] In the embodiment of the present application, when the second target lead is not disconnected at the target test point, the second end of the target device is grounded through the second target lead, so that the second target lead blocks the interference of the voltage output by the power supply on the voltage signal output by the second output port, and the target device works normally, so that the signal output by the second output port is normal, i.e., the second output port works normally; after the second target lead is disconnected at the target test point, the second end of the target device is not grounded under the action of the power supply, so that the second target lead stops blocking the interference of the voltage output by the power supply on the voltage signal output by the second output port, and the target device works abnormally, so that the signal output by the second output port is abnormal, i.e., the second output port works abnormally. Thus, without setting a switching circuit, the second target lead can directly block and stop blocking the interference of the voltage output by the power supply on the voltage signal output by the second output port, and the structure is simple and the cost is low.

[0055] It should be noted that in the above embodiment, i.e., the embodiment in which the first end of the second target lead is connected with the second resistor, the second output port can also be connected with the target device (such as C1 in Figure 4 The target device has been specifically described above, and the embodiment of the present application will not be described again. Based on this, the first end of the target device is connected with the second output port, and the second end of the target device is grounded, which is not limited by the embodiment of the present application.

[0056] The embodiment of the present application also provides a display terminal, which comprises a terminal device body and a display device arranged on the terminal device body. The display device can be the display device as described above.

[0057] An exemplary display terminal is shown in Figure 6 , which comprises a terminal device body 601 and a display device 602. The display device 602 is arranged on the terminal device body 601 and is electrically connected with the terminal device body 601. The display device 602 is the display device described in the above embodiment, which is used to display a static picture or a dynamic picture.

[0058] Exemplarily, the display terminal described above can be realized in the form of various electronic devices such as a mobile phone, a tablet computer, a palm computer, a PAD, etc.

[0059] The above embodiments are only used to illustrate the embodiments of the present application, and are not used to limit the embodiments of the present application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions belong to the scope of the embodiments of the present application, and the patent protection scope of the embodiments of the present application should be defined by the claims.

Claims

1. A display device, characterized in that, The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device.

2. The apparatus of claim 1, wherein, The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device.

3. The apparatus of claim 2, wherein, The application relates to a display driving chip and a display device.

4. A display device, characterized by comprising: The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. 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The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving chip and a display device. The application relates to a display driving The circuit board is embedded with at least one target conductor, the target conductor is provided with a target test point on the surface of the circuit board between two ends of the target conductor, the target test point is covered with an insulating layer, each target conductor is connected with at least one output end of the display driving chip, the circuit board is connected with the screen body, the display driving chip is arranged on the screen body, the at least one target conductor includes a second target conductor, the display driving chip includes a second output port for outputting a voltage signal for driving the screen body to display, the second output port is connected with the second target conductor, and the second target conductor is connected with a power supply; After the insulating layer covering the target test point of any target conductor is scraped off and the any target conductor is disconnected from the position where the target test point is arranged, the output end of the display driving chip connected with the any target conductor works abnormally; The second target conductor is used for blocking interference of the voltage output by the power supply on the voltage signal output by the second output port when the second target conductor is not disconnected from the position where the target test point is arranged, and is used for stopping the blocking of the interference of the voltage output by the power supply on the voltage signal output by the second output port when the second target conductor is disconnected from the position where the target test point is arranged.

5. The apparatus of claim 4, wherein, A first end of the second target conductor is connected with a second resistor, a first end of the second resistor is connected with the power supply, a second end of the second resistor is one end of the second resistor connected with a second end of the second target conductor, and the second end of the second target conductor is grounded; a second switch circuit is connected between the second output port and the power supply, and the second target conductor is connected with the second switch circuit; The second switch circuit is used for turning off between the second output port and the power supply when the second target conductor is not disconnected from the position where the target test point is arranged, and is used for turning on between the second output port and the power supply after the second target conductor is disconnected from the position where the target test point is arranged.

6. The apparatus of claim 5, wherein, The second switch circuit includes a second transistor; A source of the second transistor is connected with the second output port and a drain of the second transistor is connected with the power supply, or a source of the second transistor is connected with the power supply and a drain of the second transistor is connected with the second output port; a gate of the second transistor is connected with a first end of the second target conductor; 7. The apparatus of claim 6, wherein, The second transistor is arranged in the display driving chip or the screen body.

8. The apparatus of claim 4, wherein, A first end of the second target conductor is connected with a third resistor, a first end of the third resistor is connected with the power supply, and a second end of the third resistor is one end of the third resistor connected with a second end of the second target conductor; and the second end of the second target conductor is grounded. The circuit board is provided with a target device for filtering or voltage stabilizing the signal output by the second output port, a first end of the target device is connected with the second output port, a second end of the target device is connected with the first end of the second target lead, the target device is used for normal work when the second end of the target device is grounded, and the target device works abnormally when the second end of the target device is not grounded.

9. A display terminal, characterized by The display terminal comprises a terminal device body and the display device as claimed in any one of claims 1-3 or any one of claims 4-8 arranged on the terminal device body.

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