Gate driver and display device

Abstract

The invention relates to a gate driver and a display device. The gate driver comprises an input circuit, a pull-up circuit, a pull-down circuit, a QB node control circuit and a Q node control circuit. The input circuit transmits an input signal to the Q node in response to a first clock signal. The pull-up circuit pulls up the gate output signal to a high voltage in response to a signal of the QF node. The pull-down circuit pulls down the gate output signal to a first low voltage in response to a signal of the QB node. The QB node control circuit controls a signal of the QB node based on a QB control signal and a second clock signal. The Q node control circuit controls the signal of the Q node based on the signal of the QB node.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate driver and a display device including the gate driver. More particularly, embodiments of the present invention relate to a gate driver with reduced power consumption and a display device including the gate driver. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver. Summary of the invention

[0003] The display panel and the display panel driver of the display device may include P-type transistors or N-type transistors. In order to prevent current leakage, the display panel may include only N-type transistors. In a display device in which the display panel includes only N-type transistors and the gate driver integrated in the display panel includes P-type transistors, the manufacturing process may become complicated and current leakage may occur in the gate driver.

[0004] In addition, flicker may occur in the display panel due to current leakage, and thus the display quality of the display panel may be deteriorated.

[0005] Embodiments of the present invention provide a gate driver with reduced power consumption.

[0006] An embodiment of the present invention provides a display device including a gate driver.

[0007] In an embodiment of the gate driver according to the present invention, the gate driver includes an input circuit, a pull-up circuit, a pull-down circuit, a QB node control circuit, and a Q node control circuit. In such an embodiment, the input circuit transmits the input signal to the Q node in response to a first clock signal. In such an embodiment, the pull-up circuit pulls up the gate output signal to a high voltage in response to a signal at the QF node. In such an embodiment, the pull-down circuit pulls down the gate output signal to a first low voltage in response to a signal at the QB node. In such an embodiment, the QB node control circuit controls the signal of the QB node based on the QB control signal and the second clock signal. In such an embodiment, the Q node control circuit controls the signal of the Q node based on the signal of the QB node.

[0008] In an embodiment, the gate driver may further include: a carry pull-up circuit that pulls up the carry signal to a high voltage in response to a signal of the QF node; and a carry pull-down circuit that pulls down the carry signal to a second low voltage less than the first low voltage in response to a signal of the QB node.

[0009] In an embodiment, the carry pull-up circuit may include a fifth transistor including a control electrode connected to the QF node, a first electrode receiving a high voltage, and a second electrode connected to the carry output terminal. In such an embodiment, the carry pull-down circuit may include a sixth transistor including a control electrode connected to the QB node, a first electrode receiving a second low voltage, and a second electrode connected to the carry output terminal.

[0010] In an embodiment, the gate driver may further include a boost circuit configured to boost the QF node using the second clock signal in response to a signal of the QF node.

[0011] In an embodiment, the boost circuit may include: a fourth transistor, the fourth transistor including a control electrode connected to the QF node, a first electrode receiving a second clock signal, and a second electrode connected to the second electrode of the first capacitor; and a first capacitor, including a first electrode connected to the QF node, and a second electrode.

[0012] In an embodiment, the input circuit may include: a first first transistor, including a control electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a first intermediate node; and a second first transistor, including a control electrode receiving the first clock signal, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node.

[0013] In an embodiment, the gate driver may further include a third transistor including a control electrode receiving a high voltage, a first electrode connected to the Q node, and a second electrode connected to the QF node.

[0014] In an embodiment, the Q-node control circuit may include: a first second transistor, including a control electrode connected to the QB node, a first electrode connected to the second intermediate node, and a second electrode connected to the Q node; and a second second transistor, including a control electrode connected to the QB node, a first electrode receiving a second low voltage less than the first low voltage, and a second electrode connected to the second intermediate node.

[0015] In an embodiment, the second transistor may further include a second control electrode receiving a second low voltage.

[0016] In an embodiment, the gate driver may further include a thirteenth transistor that applies a second low voltage, which is lower than the first low voltage, to the QB node in response to a signal at the Q node.

[0017] In an embodiment, the gate driver may further include a reset circuit that applies a first low voltage to the Q node in response to a reset signal.

[0018] In an embodiment, the reset circuit may include: a second fifteenth transistor, including a control electrode receiving a reset signal, a first electrode receiving a first low voltage, and a second electrode connected to a fifteenth intermediate node; and a first fifteenth transistor, including a control electrode receiving a reset signal, a first electrode connected to the fifteenth intermediate node, and a second electrode connected to the Q node.

[0019] In an embodiment, the pull-up circuit may include: a seventh transistor, the seventh transistor including a control electrode connected to the QF node, a first electrode receiving a high voltage, and a second electrode connected to the gate output terminal; and a second capacitor connected to the control electrode of the seventh transistor and the second electrode of the seventh transistor.

[0020] In an embodiment, the QB node control circuit may include: a first ninth transistor, including a control electrode receiving a QB control signal, a first electrode connected to the control electrode of the tenth transistor, and a second electrode connected to the ninth intermediate node; a second ninth transistor, including a control electrode receiving the QB control signal, a first electrode connected to the ninth intermediate node, and a second electrode receiving the QB control signal; a tenth transistor, including a control electrode connected to the first electrode of the first ninth transistor, a first electrode receiving the QB control signal, and a second electrode connected to the first electrode of the eleventh transistor; and an eleventh transistor, including a control electrode receiving a second clock signal, a first electrode connected to the second electrode of the tenth transistor, and a second electrode connected to the QB node.

[0021] In an embodiment, the QB node control circuit may further include a third capacitor including a first electrode connected to the control electrode of the tenth transistor and a second electrode connected to the QB node.

[0022] In an embodiment, the gate driver may further include: a first first transistor, including a control electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a first intermediate node; a second first transistor, including a control electrode receiving a first clock signal, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; a first second transistor, including a control electrode connected to the QB node, a first electrode connected to the second intermediate node, and a second electrode connected to the Q node; a second second transistor, including a control electrode connected to the QB node, a first electrode receiving a second low voltage less than the first low voltage, and a second electrode connected to the second intermediate node; and a stabilization circuit, applying a high voltage to the first intermediate node and the second intermediate node in response to a signal at the Q node.

[0023] In an embodiment, a stabilization circuit may include: a second fourteenth transistor, including a control electrode connected to the Q node, a first electrode connected to the fourteenth intermediate node, and a second electrode connected to the first intermediate node and the second intermediate node; and a first fourteenth transistor, including a control electrode connected to the Q node, a first electrode receiving a high voltage, and a second electrode connected to the fourteenth intermediate node.

[0024] In an embodiment, the gate driver may further include a boost circuit that boosts the QF node using a second clock signal in response to a signal at the QF node. In such an embodiment, the boost circuit may include: a fourth transistor, the fourth transistor including a control electrode connected to the QF node, a first electrode receiving the second clock signal, and a second electrode connected to the second electrode of the first capacitor; and a first capacitor including a first electrode connected to the QF node, and a second electrode. In such an embodiment, the gate driver may further include a sixteenth transistor that applies a first low voltage to the second electrode of the fourth transistor in response to the first clock signal.

[0025] In an embodiment, all transistors in the gate driver may be N-type transistors.

[0026] In an embodiment, the QB control signal may be a high voltage.

[0027] In an embodiment, the QB control signal may not be a high voltage.

[0028] In an embodiment, the high level of the first clock signal may be a high voltage. In such an embodiment, the low level of the first clock signal may be a second low voltage that is less than the first low voltage.

[0029] In an embodiment, a high level of the first clock signal may be different from a high voltage, or a low level of the first clock signal may be different from a second low voltage that is less than the first low voltage.

[0030] In an embodiment of the gate driver according to the present invention, the gate driver includes an input circuit, a pull-up circuit, a pull-down circuit, a QB node control circuit, and a Q node control circuit. In such an embodiment, the input circuit transmits the input signal to the Q node in response to the first carry clock signal. In such an embodiment, the pull-up circuit outputs the second clock signal as the gate output signal in response to the signal of the Q node. In such an embodiment, the pull-down circuit pulls the gate output signal down to a low voltage in response to the signal of the QB node. In such an embodiment, the QB node control circuit controls the signal of the QB node based on the QB control signal. In such an embodiment, the Q node control circuit controls the signal of the Q node based on the signal of the QB node and the second carry clock signal.

[0031] In an embodiment, the QB node control circuit may include: a first ninth transistor, including a control electrode receiving a QB control signal and a first electrode connected to the control electrode of the tenth transistor; a second ninth transistor, including a control electrode receiving the QB control signal, a first electrode connected to the ninth intermediate node, and a second electrode receiving the QB control signal; and a tenth transistor, including a control electrode connected to the first electrode of the first ninth transistor, a first electrode receiving the QB control signal, and a second electrode connected to the QB node.

[0032] In an embodiment, the QB node control circuit may further include a third capacitor including a first electrode connected to the control electrode of the tenth transistor and a second electrode connected to the QB node.

[0033] In an embodiment, the Q-node control circuit may include: a seventeenth transistor, including a control electrode receiving a second carry clock signal, a first electrode connected to the Q node, and a second electrode connected to a seventeenth intermediate node; and an eighteenth transistor, including a control electrode connected to the QB node, a first electrode connected to the seventeenth intermediate node, and a second electrode connected to the carry output terminal.

[0034] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver and an emission driver. In such an embodiment, the display panel includes pixels. In such an embodiment, the gate driver outputs a gate signal to the pixel. In such an embodiment, the data driver outputs a data voltage to the pixel. In such an embodiment, the emission driver outputs an emission signal to the pixel. In such an embodiment, the gate driver includes an input circuit, a pull-up circuit, a pull-down circuit, a QB node control circuit and a Q node control circuit. In such an embodiment, the input circuit transmits the input signal to the Q node in response to a first clock signal. In such an embodiment, the pull-up circuit pulls up the gate output signal to a high voltage in response to a signal of the QF node. In such an embodiment, the pull-down circuit pulls down the gate output signal to a low voltage in response to a signal of the QB node. In such an embodiment, the QB node control circuit controls the signal of the QB node based on the QB control signal and the second clock signal. In such an embodiment, the Q node control circuit controls the signal of the Q node based on the signal of the QB node.

[0035] According to an embodiment of the gate driver and the display device including the gate driver, all transistors in the gate driver may be configured as N-type transistors. In such an embodiment, the gate driver may not include P-type transistors but only include N-type transistors.

[0036] In such an embodiment, in order to prevent current leakage, the display panel includes only N-type transistors, and the gate driver integrated in the display panel also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel can be enhanced.

[0037] In such an embodiment, the reliability and stability of the gate output signal may be enhanced and the power consumption may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other features of the embodiments of the present invention will become more apparent by describing the embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0039] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0040] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a gate driver;

[0041] Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of a gate driver stage;

[0042] Figure 4 It is shown Figure 2 A signal timing diagram of an input signal, a node signal and an output signal of a gate driver;

[0043] Figure 5 It is shown Figure 4 An example signal timing diagram of a first clock signal and a second clock signal;

[0044] Figure 6 It is shown Figure 4 An example signal timing diagram of a first clock signal and a second clock signal;

[0045] Figure 7 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0046] Figure 8 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0047] Fig. 9 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0048] Fig.10 It is shown Fig. 9 A signal timing diagram of an input signal, a node signal and an output signal of a gate driver;

[0049] Fig.11 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0050] Fig.12 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0051] Fig.13 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0052] Fig.14 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0053] Fig.15 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0054] Fig.16 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0055] Fig.17 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0056] Fig.18is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0057] Fig.19 It is shown Fig.18 A signal timing diagram of an input signal, a node signal and an output signal of a gate driver;

[0058] Fig. 20 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0059] Fig.21 is a circuit diagram showing a stage of a gate driver according to an embodiment of the present invention;

[0060] Fig. 22 is a block diagram showing an electronic device according to an embodiment of the present invention; and

[0061] Fig.23 It is shown Fig. 22 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0062] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are illustrated. However, the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals always indicate the same elements.

[0063] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element, or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0064] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer", or "first section" discussed below may be referred to as "second element", "second component", "second region", "second layer", or "second section".

[0065] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. Unless the context clearly states otherwise, "one", "a kind of", "the (said)" and "at least one" as used herein do not indicate the limitation of quantity, and are intended to include both singular and plural. Therefore, in the claim, the reference to "the (said)" element after the reference to "a (one)" element includes one element and multiple elements. For example, unless the context clearly states otherwise, "element" has the same meaning as "at least one element". "At least one (kind)" should not be interpreted as being limited to "one" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the term "including" and / or "comprising" or "containing" and / or "having" indicates the existence of stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or combinations thereof.

[0066] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device is turned over in one drawing, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one drawing, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below..." or "below..." can cover both upper and lower orientations.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0068] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0069] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0070] refer to Figure 1 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0071] The display panel 100 has a display area AA displaying an image and a peripheral area PA adjacent to the display area AA.

[0072] The display panel 100 may include a plurality of gate lines GWL, GIL, GBL, and GCL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWL, GIL, GBL, and GCL, the data lines DL, and the emission lines EL. The gate lines GWL, GIL, GBL, and GCL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0073] The drive controller 200 may receive input image data IMG and an input control signal CONT from an external device. In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. In an embodiment, for example, the input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0074] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0075] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0076] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0077] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0078] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0079] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0080] The gate driver 300 generates a gate signal for driving the gate lines GWL, GIL, GBL, and GCL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GWL, GIL, GBL, and GCL. In an embodiment, for example, the gate driver 300 may be integrated in the peripheral area PA of the display panel 100. In an embodiment, for example, the gate driver 300 may be mounted on the peripheral area PA of the display panel 100.

[0081] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF is used to convert the data signal DATA into a data voltage having an analog type.

[0082] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 , or in the data driver 500 .

[0083] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0084] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL. In an embodiment, for example, the emission driver 600 may be integrated in the peripheral area PA of the display panel 100. In an embodiment, for example, the emission driver 600 may be mounted on the peripheral area PA of the display panel 100.

[0085] Although for ease of illustration and description, Figure 1 100 and the emission driver 600 are disposed on a second side of the display panel 100 opposite to the first side, but the present invention may not be limited thereto. In an embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on the first side of the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be integrally formed as a single driver or circuit chip.

[0086] Figure 2 It is shown Figure 1 The gate driver 300 (see Figure 1 ) is a block diagram of an embodiment of the present invention.

[0087] refer to Figure 1 and Figure 2 , in an embodiment, the gate driver 300 may include a plurality of stages ST[1], ST[2], ST[3], and ST[4].

[0088] The high voltage VGH, the low voltage (or first low voltage) VGL, the second low voltage VGL2, the first clock signal CLK1, and the second clock signal CLK2 may be applied to each of the stages ST[1], ST[2], ST[3], and ST[4]. In addition, the reset signal RST may be applied to each of the stages ST[1], ST[2], ST[3], and ST[4].

[0089] In an embodiment, for example, the second low voltage VGL2 may have a level lower than that of the low voltage VGL.

[0090] The first clock signal CLK1 and the second clock signal CLK2 may be alternately applied to one input terminal of each of the stages ST[1], ST[2], ST[3], and ST[4]. In an embodiment, for example, the first clock signal CLK1 may be applied to the first clock terminal of the first stage ST[1] and the second clock signal CLK2 may be applied to the second clock terminal of the first stage ST[1]. In such an embodiment, the second clock signal CLK2 may be applied to the first clock terminal of the second stage ST[2] and the first clock signal CLK1 may be applied to the second clock terminal of the second stage ST[2].

[0091] Like the first stage ST[1], the first clock signal CLK1 may be applied to the first clock terminal of the third stage ST[3] and the second clock signal CLK2 may be applied to the second clock terminal of the third stage ST[3]. Like the second stage ST[2], the second clock signal CLK2 may be applied to the first clock terminal of the fourth stage ST[4] and the first clock signal CLK1 may be applied to the second clock terminal of the fourth stage ST[4].

[0092] The vertical start signal VS may be applied to the input terminal IT[1] of the first stage ST[1]. The first carry signal CR[1] of the first stage ST[1] may be applied to the input terminal IT[2] of the second stage ST[2]. The second carry signal CR[2] of the second stage ST[2] may be applied to the input terminal IT[3] of the third stage ST[3]. The third carry signal CR[3] of the third stage ST[3] may be applied to the input terminal IT[4] of the fourth stage ST[4].

[0093] The carry terminals CT[ 1 ] to CT[ 4 ] of the first to fourth stages ST[ 1 ] to ST[ 4 ] may output first to fourth carry signals CR[ 1 ] to CR[ 4 ], respectively.

[0094] The gate output terminals OT[ 1 ] to OT[ 4 ] of the first to fourth stages ST[ 1 ] to ST[ 4 ] may output first to fourth gate output signals OUT[ 1 ] to OUT[ 4 ], respectively.

[0095] Figure 3 It is shown Figure 2 The gate driver 300 (see Figure 1 )'s circuit diagram of an embodiment of the level. Figure 4 It is shown Figure 2 The gate driver 300 (see Figure 1 )’s input signals, node signals, and output signals.

[0096] refer to Figures 1 to 4, an embodiment of the stage of the gate driver 300 includes: a pull-up circuit that pulls up the gate output signal OUT[n] to a high voltage VGH in response to a signal at the QF node; a pull-down circuit that pulls down the gate output signal OUT[n] to a low voltage VGL in response to a signal at the QB node; and a QB node control circuit that controls the signal (or voltage) of the QB node based on a QB control signal (e.g., a high voltage VGH) and a second clock signal CLK2. In an embodiment, the QB control signal may be a high voltage VGH.

[0097] In an embodiment, for example, the pull-up circuit may include: a seventh transistor T7 including a control electrode connected to the QF node, a first electrode receiving a high voltage VGH, and a second electrode connected to the gate output terminal; and a second capacitor C2 connected to the control electrode of the seventh transistor T7 and the second electrode of the seventh transistor T7. The second capacitor C2 may be a boost capacitor that pulls up the gate output signal OUT[n] to the high voltage VGH.

[0098] In an embodiment, for example, the pull-down circuit may include an eighth transistor T8.

[0099] The QB node control circuit may include: a first ninth transistor T9-1, including a control electrode receiving a QB control signal (e.g., a high voltage VGH), a first electrode connected to the control electrode NC of the tenth transistor T10, and a second electrode connected to the ninth intermediate node; a second ninth transistor T9-2, including a control electrode receiving a QB control signal (e.g., a high voltage VGH), a first electrode connected to the ninth intermediate node, and a second electrode receiving the QB control signal (e.g., a high voltage VGH); a tenth transistor T10, including a control electrode NC connected to the first electrode of the first ninth transistor T9-1, a first electrode receiving the QB control signal (e.g., a high voltage VGH), and a second electrode connected to the first electrode NB of the eleventh transistor T11; and an eleventh transistor T11, including a control electrode receiving a second clock signal CLK2, a first electrode connected to the second electrode of the tenth transistor T10, and a second electrode connected to the QB node.

[0100] The QB node control circuit may further include a third capacitor C3 including a first electrode connected to the control electrode NC of the tenth transistor T10 and a second electrode connected to the QB node.

[0101] The third capacitor C3 may accelerate the turning on and off of the tenth transistor T10, so that the display device may operate quickly.

[0102] The stage of the gate driver 300 may further include a twelfth transistor T12 that applies the low voltage VGL to the control electrode NC of the tenth transistor T10 in response to the signal of the Q node.

[0103] When the signal of the Q node has a high level, the twelfth transistor T12 can be turned on, so that the low voltage VGL can be applied to the control electrode NC of the tenth transistor T10 through the twelfth transistor T12. When the low voltage VGL is applied to the control electrode NC of the tenth transistor T10, the tenth transistor T10 can be turned off. There is a period in which the signal of the Q node and the QB control signal (e.g., the high voltage VGH) both have a high level. In the period in which the signal of the Q node and the QB control signal (e.g., the high voltage VGH) both have a high level, the first ninth transistor T9-1, the second ninth transistor T9-2 and the twelfth transistor T12 can be turned on. When the first ninth transistor T9-1, the second ninth transistor T9-2 and the twelfth transistor T12 are turned on, due to the voltage drop of the resistance component of the first ninth transistor T9-1 and the second ninth transistor T9-2, the signal of the control electrode NC of the tenth transistor T10 can maintain the level of the low voltage VGL. Therefore, even if the signal of the Q node and the QB control signal (e.g., the high voltage VGH) both have a high level, the tenth transistor T10 can also be well kept in the off state. Herein, the first ninth transistor T9 - 1 and the second ninth transistor T9 - 2 may function as inverters including a diode connection.

[0104] In the embodiment, even if the eleventh transistor T11 is repeatedly turned on and off by the second clock signal CLK2 applied to the eleventh transistor T11, the signal of the QB node can be stably maintained at a low level by the third capacitor C3 and the parasitic capacitance of the eleventh transistor T11. Therefore, even if the eleventh transistor T11 is repeatedly turned on and off, the gate output signal OUT[n] and the carry signal CR[n] can stably output respective high levels.

[0105] The stage of the gate driver 300 may further include a carry pull-up circuit that pulls up the carry signal CR[n] to the high voltage VGH in response to a signal of the QF node, and a carry pull-down circuit that pulls down the carry signal CR[n] to a second low voltage VGL2 that is lower than the low voltage VGL in response to a signal of the QB node.

[0106] The carry pull-up circuit may include a fifth transistor T5 including a control electrode connected to the QF node, a first electrode receiving the high voltage VGH, and a second electrode connected to the carry output terminal.

[0107] The carry pull-down circuit may include a sixth transistor T6 including a control electrode connected to the QB node, a first electrode receiving the second low voltage VGL2 , and a second electrode connected to the carry output terminal.

[0108] The stage of the gate driver 300 may further include a boost circuit that boosts the QF node using the second clock signal CLK2 in response to the signal of the QF node.

[0109] The boost circuit may include: a fourth transistor T4 including a control electrode connected to the QF node, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the second electrode of the first capacitor C1; and a first capacitor C1 including a first electrode connected to the QF node, and a second electrode.

[0110] The stage of the gate driver 300 may further include an input circuit that transmits an input signal IN[n] to the Q node in response to the first clock signal CLK1 .

[0111] The input circuit may include: a first first transistor T1-1, including a control electrode receiving a first clock signal CLK1, a first electrode receiving an input signal IN[n], and a second electrode connected to a first intermediate node NA; and a second first transistor T1-2, including a control electrode receiving the first clock signal CLK1, a first electrode connected to the first intermediate node NA, and a second electrode connected to the Q node.

[0112] The stage of the gate driver 300 may further include a third transistor T3 including a control electrode receiving the high voltage VGH, a first electrode connected to the Q node, and a second electrode connected to the QF node.

[0113] The stage of the gate driver 300 may further include a Q-node control circuit that controls a signal of the Q node (applies the second low voltage VGL2 to the Q node) in response to a signal of the QB node.

[0114] The Q-node control circuit may include: a first second transistor T2-1, including a control electrode connected to the QB node, a first electrode connected to the second intermediate node NA, and a second electrode connected to the Q node; and a second second transistor T2-2, including a control electrode connected to the QB node, a first electrode receiving a second low voltage VGL2, and a second electrode connected to the second intermediate node NA.

[0115] The stage of the gate driver 300 may further include a thirteenth transistor T13 which applies the second low voltage VGL2 to the QB node in response to the signal of the Q node.

[0116] The stage of the gate driver 300 may further include a reset circuit that applies a low voltage VGL to the Q node in response to a reset signal RST.

[0117] The reset circuit may include: a second fifteenth transistor T15-2, including a control electrode receiving a reset signal RST, a first electrode receiving a low voltage VGL, and a second electrode connected to a fifteenth intermediate node NA; and a first fifteenth transistor T15-1, including a control electrode receiving a reset signal RST, a first electrode connected to the fifteenth intermediate node NA, and a second electrode connected to the Q node.

[0118] The reset signal RST may have an active level in an initial turn-on period of the display device. By the reset signal RST, unintentional or undesirable light emission may be effectively prevented in the initial turn-on period of the display device.

[0119] The stage of the gate driver 300 may further include a stabilization circuit that applies a high voltage VGH to the first and second intermediate nodes NA in response to a signal of the Q node. The stabilization circuit may also apply the high voltage VGH to a fifteenth intermediate node NA.

[0120] The stabilization circuit may include: a second fourteenth transistor T14-2, including a control electrode connected to the Q node, a first electrode connected to the fourteenth intermediate node, and a second electrode connected to the first intermediate node NA, the second intermediate node NA and the fifteenth intermediate node NA; and a first fourteenth transistor T14-1, including a control electrode connected to the Q node, a first electrode receiving a high voltage VGH, and a second electrode connected to the fourteenth intermediate node.

[0121] Figure 4 The vertical start signal VS, the first clock signal CLK1, the second clock signal CLK2, the signal of the Q node, the signal of the QF node, the signal of the QB node, the carry signal CR[1], and the gate output signals OUT[1], OUT[2], and OUT[3] in the first frame FR1 are shown. The waveforms of the above signals of the first frame FR1 may be repeated in the second frame.

[0122] Figure 5 It is shown Figure 4 1 and 2. FIG. 1 is a signal timing diagram of an example of a first clock signal CLK1 and a second clock signal CLK2. Figure 6 It is shown Figure 4 1 and 2. FIG. 1 is a signal timing diagram of an example of a first clock signal CLK1 and a second clock signal CLK2.

[0123] refer to Figures 1 to 5, the high level of the first clock signal CLK1 may be the high voltage VGH, and the low level of the first clock signal CLK1 may be the second low voltage VGL2 which is less than the first low voltage VGL. In addition, the high level of the second clock signal CLK2 may be the high voltage VGH, and the low level of the second clock signal CLK2 may be the second low voltage VGL2.

[0124] In such an embodiment, the high level and the low level of the first clock signal CLK1 and the second clock signal CLK2 are the high voltage VGH and the second low voltage VGL2 as the power supply voltage of the gate driver 300, so that the power supply voltage used in the display device can be simplified, and therefore, the circuit of the display device can be simplified.

[0125] refer to Figures 1 to 4 and Figure 6 , the high level of the first clock signal CLK1 may be a voltage different from the high voltage VGH (i.e., a high level VCH), and the low level of the first clock signal CLK1 may be a voltage different from the second low voltage VGL2 (i.e., a low level VCL). In addition, the high level of the second clock signal CLK2 may be a voltage different from the high voltage VGH (i.e., a high level VCH), and the low level of the second clock signal CLK2 may be a voltage different from the second low voltage VGL2 (i.e., a low level VCL).

[0126] In an embodiment, for example, a high level VCH of the first clock signal CLK1 and the second clock signal CLK2 may be less than the high voltage VGH. In an embodiment, for example, a low level VCL of the first clock signal CLK1 and the second clock signal CLK2 may be greater than the second low voltage VGL2.

[0127] In such an embodiment, the difference between the high level and the low level of the first clock signal CLK1 and the second clock signal CLK2 may be less than Figure 5 The difference between the high level and the low level of the first clock signal CLK1 and the second clock signal CLK2 of the embodiment can further reduce the power consumption of the display device.

[0128] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. The gate driver 300 may not include P-type transistors but only include N-type transistors.

[0129] In an embodiment, the display panel 100 includes only N-type transistors to prevent current leakage, and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented from occurring in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0130] In such an embodiment, the reliability and stability of the gate output signal OUT[n] may be enhanced and power consumption may be reduced.

[0131] Figure 7 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0132] In addition to the QB control signal GBI, Figure 7 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0133] refer to Figure 7 , in an embodiment, the QB control signal GBI may be different from the high voltage VGH. In an embodiment, for example, in a normal driving operation, the QB control signal GBI may have a high voltage VGH. In an initial turn-on period, the QB control signal GBI may have a voltage different from the high voltage VGH. In such an embodiment, the level of the QB control node GBI may be appropriately adjusted during the initial turn-on period, so that unintentional or undesirable light emission of the display panel 100 may be effectively prevented in the initial turn-on period of the display device.

[0134] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0135] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0136] In addition, reliability and stability of the gate output signal OUT[n] can be enhanced and power consumption can be reduced.

[0137] Figure 8 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0138] Except that the stage does not include stabilization circuits T14-1 and T14-2, Figure 8 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0139] refer to Figure 8 In an embodiment, the stage may not include Figure 3 The stabilization circuits T14-1 and T14-2.

[0140] In an embodiment, according to the characteristics of the display panel 100, the gate driver 300, and the display device, the stabilization circuits T14-1 and T14-2 may be omitted. In such an embodiment where the stage of the gate driver 300 does not include the stabilization circuits T14-1 and T14-2, the area of ​​the stage of the gate driver 300 may be reduced. Therefore, the useless space of the display device may be reduced.

[0141] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0142] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0143] In addition, reliability and stability of the gate output signal OUT[n] can be enhanced and power consumption can be reduced.

[0144] Fig. 9 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram. Fig.10 It is shown Fig. 9The gate driver 300 (see Figure 1 )’s input signals, node signals, and output signals.

[0145] Except that the stage does not include the second capacitor C2, Fig. 9 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0146] In addition to the fact that the carry signal CR[n] and the gate output signal OUT[n] increase in two steps (or levels) because the stage does not include the second capacitor C2, Fig.10 The embodiment of the input signal, node signal and output signal of the gate driver 300 shown in FIG. Figure 4 The input signals, node signals, and output signals of the gate driver 300 described in the embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above reference. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0147] In an embodiment, the second capacitor C2 may be a boost capacitor that quickly pulls up the gate output signal OUT[n]. Depending on the characteristics of the display panel 100, the gate driver 300, and the display device, the second capacitor C2 may be omitted. In such an embodiment where the stage of the gate driver 300 does not include the second capacitor C2, the area of ​​the stage of the gate driver 300 may be reduced, thereby reducing the useless space of the display device.

[0148] In such an embodiment, due to the threshold voltage of the third transistor T3, the voltage level of the signal of the QF node may be slightly lower than the voltage level of the signal of the Q node. In such an embodiment, the stage does not include the second capacitor C2, so that when the signal of the Q node has a high level and the signal of the QF node has a first high level, the fifth transistor T5 and the seventh transistor T7 may not be fully turned on. Therefore, when the signal of the Q node has a high level and the signal of the QF node has a first high level, the carry signal CR[n] and the gate output signal OUT[n] may increase to the first step (or stage).

[0149] Subsequently, when the signal of the QF node is boosted to a second high level by the fourth transistor T4 and the first capacitor C1 in synchronization with the high level of the second clock signal CLK2, the fifth transistor T5 and the seventh transistor T7 may be fully turned on. When the fifth transistor T5 and the seventh transistor T7 are fully turned on, the carry signal CR[n] and the gate output signal OUT[n] may increase to a second step (or level).

[0150] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0151] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0152] In addition, reliability and stability of the gate output signal OUT[n] can be enhanced and power consumption can be reduced.

[0153] Fig.11 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0154] Except that the stage does not include the third capacitor C3, Fig.11 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0155] In an embodiment, the third capacitor C3 can accelerate the turn-on and turn-off of the tenth transistor T10 to achieve high-speed driving of the display device. According to the characteristics of the display panel 100, the gate driver 300 and the display device, the third capacitor C3 can be omitted. In such an embodiment where the stage of the gate driver 300 does not include the third capacitor C3, the area of ​​the stage of the gate driver 300 can be reduced, thereby reducing the useless space of the display device.

[0156] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0157] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0158] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0159] Fig.12 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0160] Except that the stage does not include reset circuits T15-1 and T15-2, Fig.12 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0161] refer to Fig.12 In an embodiment, the stage may not include Figure 3 Reset circuits T15-1 and T15-2.

[0162] In an embodiment, the reset circuits T15-1 and T15-2 may be omitted according to the characteristics of the display panel 100, the gate driver 300, and the display device. In such an embodiment where the stage of the gate driver 300 does not include the reset circuits T15-1 and T15-2, the area of ​​the stage of the gate driver 300 may be reduced, thereby reducing the useless space of the display device.

[0163] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0164] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0165] In addition, reliability and stability of the gate output signal OUT[n] can be enhanced and power consumption can be reduced.

[0166] Fig.13 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0167] In addition to the stage further comprising a fourth capacitor C4 connected to the control electrode of the fifth transistor T5 and the second electrode of the fifth transistor T5, Fig.13 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0168] refer to Fig.13 In an embodiment, the fourth capacitor C4 can accelerate the pull-up of the carry signal CR[n].

[0169] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0170] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0171] In addition, reliability and stability of the gate output signal OUT[n] can be enhanced and power consumption can be reduced.

[0172] Fig.14 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0173] In addition to the stage further comprising a sixteenth transistor T16 connected to the second electrode of the first capacitor C1, Fig.14 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0174] refer to Fig.14 In an embodiment, the sixteenth transistor T16 may apply the low voltage VGL to the second electrode of the fourth transistor T4 in response to the first clock signal CLK1. The sixteenth transistor T16 may initialize the second electrode of the first capacitor C1 in response to the first clock signal CLK1.

[0175] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0176] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0177] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0178] Fig.15 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0179] In addition to the voltage applied to the first electrode of the twelfth transistor T12, Fig.15 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0180] refer to Fig.15In an embodiment, the stage of the gate driver 300 may include a twelfth transistor T12 that applies the second low voltage VGL2 to the control electrode NC of the tenth transistor T10 in response to a signal of the Q node.

[0181] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0182] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0183] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0184] Fig.16 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0185] In addition to some transistors in the stages of gate driver 300 including a second control electrode, Fig.16 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0186] refer to Fig.16 In an embodiment, the second second transistor T2-2 may further include a second control electrode. The second low voltage VGL2 may be applied to the second control electrode of the second second transistor T2-2. The second low voltage VGL2 is applied to the second control electrode of the second second transistor T2-2, so that the threshold voltage of the second second transistor T2-2 may be shifted in the positive direction, and thus the current leakage of the second second transistor T2-2 may be reduced. In addition, when the second low voltage VGL2 is applied to the second control electrode of the second second transistor T2-2, the cut-off characteristic of the second second transistor T2-2 may be enhanced.

[0187] In an embodiment, the fourth transistor T4 may further include a second control electrode. The second control electrode of the fourth transistor T4 may be connected to the control electrode of the fourth transistor T4.

[0188] In an embodiment, the fifth transistor T5 may further include a second control electrode. The second control electrode of the fifth transistor T5 may be connected to the control electrode of the fifth transistor T5.

[0189] In an embodiment, the sixth transistor T6 may further include a second control electrode. The second low voltage VGL2 may be applied to the second control electrode of the sixth transistor T6.

[0190] In an embodiment, the seventh transistor T7 may further include a second control electrode. The second control electrode of the seventh transistor T7 may be connected to the control electrode of the seventh transistor T7.

[0191] In an embodiment, the eighth transistor T8 may further include a second control electrode. The second control electrode of the eighth transistor T8 may be connected to the control electrode of the eighth transistor T8.

[0192] In an embodiment, the first ninth transistor T9 - 1 may further include a second control electrode. The second control electrode of the first ninth transistor T9 - 1 may be connected to the control electrode of the first ninth transistor T9 - 1.

[0193] In an embodiment, the second ninth transistor T9 - 2 may further include a second control electrode. The second control electrode of the second ninth transistor T9 - 2 may be connected to the control electrode of the second ninth transistor T9 - 2 .

[0194] In an embodiment, the tenth transistor T10 may further include a second control electrode. The second control electrode of the tenth transistor T10 may be connected to the control electrode NC of the tenth transistor T10.

[0195] In an embodiment, the twelfth transistor T12 may further include a second control electrode. The second control electrode of the twelfth transistor T12 may be connected to the control electrode of the twelfth transistor T12.

[0196] In an embodiment, the thirteenth transistor T13 may further include a second control electrode. The second control electrode of the thirteenth transistor T13 may be connected to the control electrode of the thirteenth transistor T13.

[0197] In an embodiment, the first fourteenth transistor T14-1 may further include a second control electrode. The second control electrode of the first fourteenth transistor T14-1 may be connected to the control electrode of the first fourteenth transistor T14-1.

[0198] In an embodiment, the second fourteenth transistor T14-2 may further include a second control electrode. The second control electrode of the second fourteenth transistor T14-2 may be connected to the control electrode of the second fourteenth transistor T14-2.

[0199] In an embodiment, the first fifteenth transistor T15-1 may further include a second control electrode. The second control electrode of the first fifteenth transistor T15-1 may be connected to the control electrode of the first fifteenth transistor T15-1.

[0200] In an embodiment, the second fifteenth transistor T15-2 may further include a second control electrode. The second control electrode of the second fifteenth transistor T15-2 may be connected to the control electrode of the second fifteenth transistor T15-2.

[0201] In an embodiment, Figure 3 As shown in , all transistors in the stage of gate driver 300 can be three-terminal elements. In another embodiment, as Fig.16 As shown in , some transistors in the stage of the gate driver 300 are four-terminal elements. In such an embodiment where the transistor is configured as a four-terminal element, the second control electrode of the four-terminal element can be connected to the control electrode of the four-terminal element. Alternatively, in an embodiment where the transistor is configured as a four-terminal element, the second control electrode of the four-terminal element can be connected to the first electrode or the second electrode of the four-terminal element. In an embodiment, for example, a low voltage VGL can be applied to the second control electrode of the four-terminal element. In an embodiment, for example, a second low voltage VGL2 can be applied to the second control electrode of the four-terminal element.

[0202] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0203] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0204] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0205] Fig.17 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0206] Except that the stage of the gate driver 300 does not include the third transistor T3, Fig.17 The embodiment of the gate driver 300 stage illustrated in FIG. Figure 3 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0207] In an embodiment, the high voltage VGH is constantly applied to Figure 3 The control electrode of the third transistor T3, thereby Figure 3 The threshold voltage of the third transistor T3 may be positively shifted, and therefore, Figure 3 The third transistor T3 may not operate normally. Therefore, in such an embodiment, the third transistor T3 may be removed to enhance the reliability of the gate driver 300. Therefore, in such an embodiment, the Q node may be the same as the QF node. In such an embodiment, for the reliability of the gate driver 300, it is desirable that the capacitance of the second capacitor C2 is large enough.

[0208] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0209] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0210] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0211] Fig.18 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram. Fig.19 It is shown Fig.18 The gate driver 300 (see Figure 1 )’s input signals, node signals, and output signals.

[0212] refer to Figure 1 , Figure 2 , Fig.18 and Fig.19 , an embodiment of the stage of the gate driver 300 includes: a pull-up circuit that outputs the second clock signal CLK2 as the gate output signal OUT[n] in response to the signal of the Q node; a pull-down circuit that pulls the gate output signal OUT[n] down to the low voltage VGL in response to the signal of the QB node; and a QB node control circuit that controls the signal of the QB node based on the QB control signal (e.g., the high voltage VGH). In such an embodiment, the QB control signal can be the high voltage VGH.

[0213] In an embodiment, for example, the pull-up circuit may include a seventh transistor T7 including a control electrode connected to the Q node, a first electrode receiving the second clock signal CLK2 , and a second electrode connected to the gate output terminal.

[0214] In an embodiment, for example, the pull-down circuit may include an eighth transistor T8.

[0215] The QB node control circuit may include: a first ninth transistor T9-1, including a control electrode receiving a QB control signal (e.g., a high voltage VGH), a first electrode connected to the control electrode NC of the tenth transistor T10, and a second electrode connected to the ninth intermediate node; a second ninth transistor T9-2, including a control electrode receiving a QB control signal (e.g., a high voltage VGH), a first electrode connected to the ninth intermediate node, and a second electrode receiving the QB control signal (e.g., a high voltage VGH); a tenth transistor T10, including a control electrode NC connected to the first electrode of the first ninth transistor T9-1, a first electrode receiving the QB control signal (e.g., a high voltage VGH), and a second electrode connected to the QB node.

[0216] The QB node control circuit may further include a third capacitor C3 including a first electrode connected to the control electrode NC of the tenth transistor T10 and a second electrode connected to the QB node.

[0217] The third capacitor C3 may accelerate the turning on and off of the tenth transistor T10, so that the display device may operate quickly.

[0218] In such an embodiment, the stage of the gate driver 300 may further include a twelfth transistor T12 that applies the low voltage VGL to the control electrode NC of the tenth transistor T10 in response to the signal of the Q node.

[0219] When the signal of the Q node has a high level, the twelfth transistor T12 can be turned on, so that the low voltage VGL can be applied to the control electrode NC of the tenth transistor T10 through the twelfth transistor T12. When the low voltage VGL is applied to the control electrode NC of the tenth transistor T10, the tenth transistor T10 can be turned off. There is a period in which both the signal of the Q node and the QB control signal (e.g., a high voltage VGH) have a high level. In the period in which both the signal of the Q node and the QB control signal (e.g., a high voltage VGH) have a high level, the first ninth transistor T9-1, the second ninth transistor T9-2, and the twelfth transistor T12 can be turned on. When the first ninth transistor T9-1, the second ninth transistor T9-2, and the twelfth transistor T12 are turned on, a voltage drop may occur in the resistance component of the first ninth transistor T9-1 and the second ninth transistor T9-2, so that the signal of the control electrode NC of the tenth transistor T10 can maintain the level of the low voltage VGL. Therefore, even if the signal of the Q node and the QB control signal (e.g., a high voltage VGH) both have a high level, the tenth transistor T10 can also be well kept in the off state. Herein, the first ninth transistor T9 - 1 and the second ninth transistor T9 - 2 may function as inverters including a diode connection.

[0220] In an embodiment, the stage of the gate driver 300 may further include: a carry pull-up circuit that outputs the second carry clock signal CRCLK2 as the carry signal CR[n] in response to the signal of the Q node; and a carry pull-down circuit that pulls the carry signal CR[n] down to the second low voltage VGL2.

[0221] The carry pull-up circuit may include a fifth transistor T5 including a control electrode connected to the Q node, a first electrode receiving the second carry clock signal CRCLK2 , and a second electrode connected to the carry output terminal.

[0222] The carry pull-up circuit may further include a first capacitor C1 including a first electrode connected to the Q node and a second electrode connected to the carry output terminal.

[0223] The carry pull-down circuit may include a sixth transistor T6 including a control electrode connected to the QB node, a first electrode receiving the second low voltage VGL2 , and a second electrode connected to the carry output terminal.

[0224] In an embodiment, the stage of the gate driver 300 may further include an input circuit that transmits the input signal IN[n] to the Q node in response to the first carry clock signal CRCLK1 .

[0225] The input circuit may include: a first first transistor T1-1, including a control electrode receiving a first carry clock signal CRCLK1, a first electrode receiving an input signal IN[n], and a second electrode connected to a first intermediate node NA; and a second first transistor T1-2, including a control electrode receiving the first carry clock signal CRCLK1, a first electrode connected to the first intermediate node NA, and a second electrode connected to the Q node.

[0226] In an embodiment, the stage of the gate driver 300 may further include a Q-node control circuit that controls a signal of the Q-node based on a signal of the QB node and the second carry clock signal CRCLK2 .

[0227] The Q-node control circuit may include: a seventeenth transistor T17, including a control electrode receiving a second carry clock signal CRCLK2, a first electrode connected to the Q node, and a second electrode connected to a seventeenth intermediate node; and an eighteenth transistor T18, including a control electrode connected to the QB node, a first electrode connected to the seventeenth intermediate node, and a second electrode connected to the carry output terminal.

[0228] In an embodiment, the stage of the gate driver 300 may further include a thirteenth transistor T13 that applies the second low voltage VGL2 to the QB node in response to the signal of the Q node.

[0229] In an embodiment, the stage of the gate driver 300 may further include a reset circuit that applies the low voltage VGL to the Q node in response to a reset signal RST.

[0230] The reset circuit may include: a second fifteenth transistor T15-2, including a control electrode receiving a reset signal RST, a first electrode receiving a low voltage VGL, and a second electrode connected to a fifteenth intermediate node NA; and a first fifteenth transistor T15-1, including a control electrode receiving a reset signal RST, a first electrode connected to the fifteenth intermediate node NA, and a second electrode connected to the Q node.

[0231] The reset signal RST may have an effective level in an initial turn-on period of the display device. In such an embodiment, unintentional or undesirable light emission may be effectively prevented in an initial turn-on period of the display device through the reset signal RST.

[0232] In an embodiment, the stage of the gate driver 300 may further include a stabilization circuit that applies the high voltage VGH to the first intermediate node NA in response to a signal of the Q node. The stabilization circuit may also apply the high voltage VGH to the fifteenth intermediate node NA.

[0233] The stabilization circuit may include: a second fourteenth transistor T14-2, including a control electrode connected to the Q node, a first electrode connected to the fourteenth intermediate node, and a second electrode connected to the first intermediate node NA and the fifteenth intermediate node NA; and a first fourteenth transistor T14-1, including a control electrode connected to the Q node, a first electrode receiving a high voltage VGH, and a second electrode connected to the fourteenth intermediate node.

[0234] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0235] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0236] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0237] Fig. 20 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0238] In addition to the QB control signal GBI, Fig. 20 The embodiment of the gate driver 300 stage illustrated in FIG. Fig.18 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Fig.18 and Fig.19 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0239] refer to Fig. 20 , in an embodiment, the QB control signal GBI may be different from the high voltage VGH. In an embodiment, for example, in a normal driving operation, the QB control signal GBI may have a high voltage VGH. In an initial turn-on period, the QB control signal GBI may have a voltage different from the high voltage VGH. In such an embodiment, the level of the QB control node GBI may be appropriately adjusted during the initial turn-on period, so that unintentional or undesirable light emission of the display panel 100 may be effectively prevented in the initial turn-on period of the display device.

[0240] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0241] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0242] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0243] Fig.21 FIG. 3 is a diagram showing a gate driver 300 according to an embodiment of the present invention (see FIG. Figure 1 ) level circuit diagram.

[0244] Except that the stage does not include stabilization circuits T14-1 and T14-2, Fig.21 The embodiment of the gate driver 300 stage illustrated in FIG. Fig.18 The embodiments of the stages of the gate driver 300 described are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above referenced embodiments. Fig.18 and Fig.19 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0245] refer to Fig.21 In an embodiment, the stage may not include Fig.18 The stabilization circuits T14-1 and T14-2.

[0246] According to the characteristics of the display panel 100, the gate driver 300, and the display device, the stabilization circuits T14-1 and T14-2 may be omitted. In such an embodiment where the stage of the gate driver 300 does not include the stabilization circuits T14-1 and T14-2, the area of ​​the stage of the gate driver 300 may be reduced. Therefore, the useless space of the display device may be reduced.

[0247] According to an embodiment, all transistors in the gate driver 300 may be configured as N-type transistors. In such an embodiment, the gate driver 300 may not include P-type transistors but only include N-type transistors.

[0248] In such an embodiment, in order to prevent current leakage, the display panel 100 includes only N-type transistors and the gate driver 300 integrated in the display panel 100 also includes only N-type transistors, so that the manufacturing process can be simplified and current leakage can be effectively prevented in the gate driver 300. In such an embodiment, flickering due to current leakage can be effectively prevented, so that the display quality of the display panel 100 can be enhanced.

[0249] In addition, the reliability and stability of the gate output signal OUT[n] can be enhanced and the power consumption can be reduced.

[0250] Fig. 22 is a block diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.23 It is shown Fig. 22 The electronic device 1000 is implemented as a diagram of an embodiment of a smart phone.

[0251] refer to Fig. 22 and Fig.23 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0252] In an embodiment, Fig.23 As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer monitor, a laptop computer, or a head mounted display (HMD) device, etc.

[0253] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0254] The processor 1010 may Figure 1 The driving controller 200 outputs the input image data IMG (see Figure 1 ) and the input control signal CONT (see Figure 1 ).

[0255] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device, etc.).

[0256] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, or a read-only compact disk memory (CD-ROM) device, etc. The I / O device 1040 may include an input device (such as a keyboard, a keypad, a mouse device, a touch pad or a touch screen, etc.) and an output device (such as a printer or a speaker, etc.). In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0257] In such an embodiment, the display device 1060 may include a gate driver including the stages according to the above-described embodiments, so that power consumption of the display device may be reduced and display quality of the display panel may be enhanced.

[0258] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0259] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A gate driver, wherein: The gate driver comprises: an input circuit, transmitting an input signal to the Q node in response to a first clock signal; A pull-up circuit, in response to a signal at a QF node, pulls up a gate output signal to a high voltage; a pull-down circuit, responsive to a signal at the QB node, pulling down the gate output signal to a first low voltage; A QB node control circuit controls the signal of the QB node based on a QB control signal and a second clock signal; and The Q node control circuit controls the signal of the Q node based on the signal of the QB node.

2. The gate driver according to claim 1, wherein: The gate driver further comprises: a carry pull-up circuit, responsive to the signal of the QF node, pulling up a carry signal to the high voltage; and The carry pull-down circuit pulls down the carry signal to a second low voltage lower than the first low voltage in response to the signal at the QB node.

3. The gate driver according to claim 2, wherein: The carry pull-up circuit includes a fifth transistor including a control electrode connected to the QF node, a first electrode receiving the high voltage, and a second electrode connected to a carry output terminal, and The carry pull-down circuit includes a sixth transistor, wherein the sixth transistor includes a control electrode connected to the QB node, a first electrode receiving the second low voltage, and a second electrode connected to the carry output terminal.

4. The gate driver according to claim 1, wherein: The gate driver further includes a boost circuit configured to boost the QF node using the second clock signal in response to the signal of the QF node.

5. The gate driver according to claim 4, wherein: The boost circuit comprises: a fourth transistor including a control electrode connected to the QF node, a first electrode receiving the second clock signal, and a second electrode connected to the second electrode of the first capacitor; and The first capacitor includes a first electrode connected to the QF node, and the second electrode.

6. The gate driver according to claim 1, wherein: The input circuit comprises: a first transistor including a control electrode receiving the first clock signal, a first electrode receiving the input signal, and a second electrode connected to a first intermediate node; and The second first transistor includes a control electrode receiving the first clock signal, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node.

7. The gate driver according to claim 1, wherein: The gate driver further includes a third transistor including a control electrode receiving the high voltage, a first electrode connected to the Q node, and a second electrode connected to the QF node.

8. The gate driver according to claim 1, wherein: The Q node control circuit comprises: A first second transistor including a control electrode connected to the QB node, a first electrode connected to a second intermediate node, and a second electrode connected to the Q node; and A second second transistor includes a control electrode connected to the QB node, a first electrode receiving a second low voltage less than the first low voltage, and a second electrode connected to the second intermediate node.

9. The gate driver according to claim 8, wherein: The second second transistor also includes a second control electrode receiving the second low voltage.

10. The gate driver according to claim 1, wherein: The gate driver also includes a thirteenth transistor that applies a second low voltage, which is less than the first low voltage, to the QB node in response to the signal of the Q node.

11. The gate driver according to claim 1, wherein: The gate driver further includes a reset circuit that applies the first low voltage to the Q node in response to a reset signal.

12. The gate driver according to claim 11, wherein: The reset circuit comprises: a second fifteenth transistor including a control electrode receiving the reset signal, a first electrode receiving the first low voltage, and a second electrode connected to a fifteenth intermediate node; and The first fifteenth transistor includes a control electrode receiving the reset signal, a first electrode connected to the fifteenth intermediate node, and a second electrode connected to the Q node.

13. The gate driver according to claim 1, wherein: The pull-up circuit comprises: a seventh transistor including a control electrode connected to the QF node, a first electrode receiving the high voltage, and a second electrode connected to a gate output terminal; and A second capacitor is connected to the control electrode of the seventh transistor and the second electrode of the seventh transistor.

14. The gate driver according to claim 1, wherein: The QB node control circuit comprises: a first ninth transistor including a control electrode receiving the QB control signal, a first electrode connected to the control electrode of the tenth transistor, and a second electrode connected to a ninth intermediate node; a second ninth transistor including a control electrode receiving the QB control signal, a first electrode connected to the ninth intermediate node, and a second electrode receiving the QB control signal; the tenth transistor including the control electrode connected to the first electrode of the first ninth transistor, a first electrode receiving the QB control signal, and a second electrode connected to the first electrode of the eleventh transistor; and The eleventh transistor includes a control electrode receiving the second clock signal, the first electrode connected to the second electrode of the tenth transistor, and a second electrode connected to the QB node.

15. The gate driver according to claim 14, wherein: The QB node control circuit further includes: A third capacitor includes a first electrode connected to the control electrode of the tenth transistor and a second electrode connected to the QB node.

16. The gate driver according to claim 1, wherein: The gate driver further comprises: a first transistor including a control electrode receiving the first clock signal, a first electrode receiving the input signal, and a second electrode connected to a first intermediate node; a second first transistor including a control electrode receiving the first clock signal, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; A first second transistor including a control electrode connected to the QB node, a first electrode connected to the second intermediate node, and a second electrode connected to the Q node; a second second transistor including a control electrode connected to the QB node, a first electrode receiving a second low voltage less than the first low voltage, and a second electrode connected to the second intermediate node; and A stabilization circuit applies the high voltage to the first intermediate node and the second intermediate node in response to the signal of the Q node.

17. The gate driver according to claim 16, wherein: The stabilization circuit comprises: a second fourteenth transistor including a control electrode connected to the Q node, a first electrode connected to a fourteenth intermediate node, and a second electrode connected to the first intermediate node and the second intermediate node; and The first fourteenth transistor includes a control electrode connected to the Q node, a first electrode receiving the high voltage, and a second electrode connected to the fourteenth intermediate node.

18. The gate driver according to claim 1, wherein: The gate driver further includes a boost circuit configured to boost the QF node using the second clock signal in response to the signal at the QF node. Wherein, the boost circuit comprises: a fourth transistor including a control electrode connected to the QF node, a first electrode receiving the second clock signal, and a second electrode connected to the second electrode of the first capacitor; and The first capacitor includes a first electrode connected to the QF node and the second electrode, and The gate driver further includes a sixteenth transistor, and the sixteenth transistor applies the first low voltage to the second electrode of the fourth transistor in response to the first clock signal.

19. The gate driver according to claim 1, wherein: All transistors in the gate driver are N-type transistors.

20. The gate driver according to claim 1, wherein The QB control signal is the high voltage.

21. The gate driver according to claim 1, wherein: The QB control signal is not the high voltage.

22. The gate driver according to claim 1, wherein: The high level of the first clock signal is the high voltage, and The low level of the first clock signal is a second low voltage which is lower than the first low voltage.

23. The gate driver according to claim 1, wherein: A high level of the first clock signal is different from the high voltage, or a low level of the first clock signal is different from a second low voltage that is smaller than the first low voltage.

24. A gate driver, wherein: The gate driver comprises: an input circuit, transmitting an input signal to a Q node in response to a first carry clock signal; a pull-up circuit, responsive to the signal of the Q node, outputting a second clock signal as a gate output signal; a pull-down circuit, responsive to a signal at a QB node, pulling down the gate output signal to a low voltage; A QB node control circuit controls the signal of the QB node based on a QB control signal; and The Q node control circuit controls the signal of the Q node based on the signal of the QB node and a second carry clock signal.

25. The gate driver according to claim 24, wherein: The QB node control circuit comprises: a first ninth transistor including a control electrode receiving the QB control signal and a first electrode connected to the control electrode of the tenth transistor; a second ninth transistor including a control electrode receiving the QB control signal, a first electrode connected to a ninth intermediate node, and a second electrode receiving the QB control signal; and The tenth transistor includes the control electrode connected to the first electrode of the first ninth transistor, a first electrode receiving the QB control signal, and a second electrode connected to the QB node.

26. The gate driver according to claim 25, wherein: The QB node control circuit also includes a third capacitor including a first electrode connected to the control electrode of the tenth transistor and a second electrode connected to the QB node.

27. The gate driver according to claim 24, wherein: The Q node control circuit comprises: a seventeenth transistor including a control electrode receiving the second carry clock signal, a first electrode connected to the Q node, and a second electrode connected to a seventeenth intermediate node; and An eighteenth transistor includes a control electrode connected to the QB node, a first electrode connected to the seventeenth intermediate node, and a second electrode connected to a carry output terminal.

28. A display device, wherein: The display device comprises: Display panel, including pixels; A gate driver, outputting a gate signal to the pixel; a data driver that outputs a data voltage to the pixel; and an emission driver, outputting an emission signal to the pixel, Wherein, the gate driver comprises: an input circuit, transmitting an input signal to the Q node in response to a first clock signal; A pull-up circuit, in response to a signal at a QF node, pulls up a gate output signal to a high voltage; a pull-down circuit, responsive to a signal at a QB node, pulling down the gate output signal to a low voltage; A QB node control circuit controls the signal of the QB node based on a QB control signal and a second clock signal; and The Q node control circuit controls the signal of the Q node based on the signal of the QB node.

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