Display driver, display driving method, and display device

Abstract

The application provides a display driver, a display driving method and a display device. The display driver is used for a display device, and comprises a storage unit, a receiving unit, a processing unit and a data voltage adjusting unit. The storage unit is configured to store a first charging duration control signal; the receiving unit is configured to receive a second charging duration control signal and image data; the processing unit is configured to determine a first charging duration according to the first charging duration control signal, determine a second charging duration according to the second charging duration control signal, and determine a first data voltage according to the image data; and the data voltage adjusting unit is configured to determine a second data voltage according to the first charging duration, the second charging duration and the first data voltage, and the product of the first data voltage and the first charging duration is equal to the product of the second data voltage and the second charging duration. The brightness of the display panel can be effectively adjusted.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driver, a display driving method and a display device. BACKGROUND

[0002] With the development of display technology, the host end (controller) may have a need to adjust the charging time of the sub-pixels of the display panel. If the charging time length of the sub-pixels set by the host end in a frame driving period is different from the charging time length of the sub-pixels originally burned and stored by the display driver, the brightness of the display panel will be abnormal, or the gamma value needs to be adjusted again. SUMMARY

[0003] The present application proposes a kind of … to solve the problems in the prior art in view of the shortcomings of the prior art.

[0004] The display driver provided by the embodiment of the present application is used for display device, the display device further includes controller and display panel, and the display panel includes sub-pixel;The display driver includes:

[0005] A storage unit is configured to store a first charging time length control signal of a sub-pixel in a frame driving period;

[0006] A receiving unit is configured to receive a second charging time length control signal of a sub-pixel in a frame driving period and image data sent by the controller;

[0007] A processing unit is configured to determine a first charging time length according to the first charging time length control signal, determine a second charging time length according to the second charging time length control signal, and determine a first data voltage according to the image data;

[0008] A data voltage adjusting unit is configured to determine a second data voltage according to the first charging time length, the second charging time length and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time length control signal, wherein the product of the first data voltage and the first charging time length is equal to the product of the second data voltage and the second charging time length.

[0009] In some embodiments, the data voltage adjusting unit includes:

[0010] A first digital-to-analog converter is connected to the processing unit and is configured to receive the first charging time length and convert the first charging time length into a first voltage;

[0011] A second digital-to-analog converter is connected to the processing unit and is configured to receive the second charging time length and convert the second charging time length into a second voltage.

[0012] a division operation circuit electrically connected with the output terminal of the first digital-to-analog converter and the output terminal of the second digital-to-analog converter, configured to generate a feedback signal according to the first voltage and the second voltage, wherein the feedback signal is equal to a ratio of the first voltage and the second voltage;

[0013] a first multiplier including a first input terminal and a second input terminal, wherein the first input terminal is connected with the processing unit for receiving the first data voltage, and the second input terminal is connected with the division operation circuit for receiving the feedback signal output by the division operation circuit, and the first multiplier is configured to generate the second data voltage according to the first data voltage and the feedback signal, wherein the second data voltage is equal to a product of the first data voltage and the feedback signal.

[0014] In some embodiments, the division operation circuit includes:

[0015] a second multiplier including a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is configured to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected with the second input terminal of the first multiplier;

[0016] an operational amplifier including a same direction input terminal, an opposite direction input terminal and a second output terminal, wherein the opposite direction input terminal is connected with the output terminal of the first digital-to-analog converter and the first output terminal of the second multiplier, the same direction input terminal is connected with a ground terminal, and the second output terminal is connected with the second input terminal of the first multiplier and the fourth input terminal of the second multiplier;

[0017] a first resistor and a second resistor, wherein the first resistor is connected between the output terminal of the first digital-to-analog converter and the opposite direction input terminal of the operational amplifier, and the second resistor is connected between the opposite direction input terminal of the operational amplifier and the first output terminal of the second multiplier, and the resistance value of the first resistor is the same as that of the second resistor.

[0018] In some embodiments, the division operation circuit further includes a third resistor connected between the same direction input terminal of the operational amplifier and the ground terminal.

[0019] In some embodiments, the division operation circuit includes:

[0020] a second multiplier including a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is configured to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected with the second input terminal of the first multiplier;

[0021] An operational amplifier, comprising a same-phase input end, an opposite-phase input end and a second output end, the same-phase input end being connected with the first output end of the second multiplier and a ground end, the opposite-phase input end being connected with the output end of the first digital-to-analog converter, and the second output end being connected with the second input end of the first multiplier and the fourth input end of the second multiplier;

[0022] A first resistor and a second resistor, the first resistor being connected between the same-phase input end of the operational amplifier and the ground end, and the second resistor being connected between the same-phase input end of the operational amplifier and the first output end of the second multiplier; wherein the resistance value of the first resistor is the same as that of the second resistor.

[0023] In some embodiments, the division operation circuit comprises:

[0024] A second multiplier, comprising a third input end, a fourth input end and a first output end, the third input end being used for receiving a second voltage output by the second digital-to-analog converter, and the fourth input end being connected with the second input end of the first multiplier;

[0025] An operational amplifier, comprising a same-phase input end, an opposite-phase input end and a second output end, the same-phase input end being connected with the output end of the first digital-to-analog converter, the opposite-phase input end being connected with the first output end of the second multiplier and a ground end, and the second output end being connected with the second input end of the first multiplier and the fourth input end of the second multiplier;

[0026] A first resistor and a second resistor, the first resistor being connected between the opposite-phase input end of the operational amplifier and the ground end, and the second resistor being connected between the opposite-phase input end of the operational amplifier and the first output end of the second multiplier; wherein the resistance value of the first resistor is the same as that of the second resistor.

[0027] In some embodiments, the division operation circuit further comprises a third resistor, which is connected between the same-phase input end of the operational amplifier and the output end of the first digital-to-analog converter.

[0028] In some embodiments, the data voltage adjustment unit further comprises a first capacitor, which is connected between the first input end of the first multiplier and a ground end.

[0029] In some embodiments, the data voltage adjustment unit further comprises a second capacitor, which is connected between the output end of the first multiplier and a ground end.

[0030] In some embodiments, the display panel comprises a first transistor and a second transistor, a gate of the first transistor is connected with a first scan line, a first electrode of the first transistor is connected with the sub-pixel, a second electrode of the first transistor is connected with a first electrode of the second transistor, a gate of the second transistor is connected with a second scan line, and a second electrode of the second transistor receives the second data voltage.

[0031] The first charging duration control signal comprises a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the second charging duration control signal comprises a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; and the processing unit is configured to determine the first charging duration according to the first timing signal and the second timing signal, and determine the second charging duration according to the third timing signal and the fourth timing signal.

[0032] In some embodiments, the processing unit is specifically configured to: determine, as the first charging duration, a duration in which the first timing signal and the second timing signal are simultaneously high within a scanning period of a row of sub-pixels; and determine, as the second charging duration, a duration in which the third timing signal and the fourth timing signal are simultaneously high within the scanning period of the row of sub-pixels.

[0033] The application also provides a display device comprising the display driver, the controller and the display panel as described above.

[0034] The controller is configured to send a second charging duration control signal and image data to the display driver.

[0035] The application also provides a display driving method for a display driver of a display device, the display device further comprising a controller and a display panel, the display panel comprising sub-pixels; the display driving method comprising:

[0036] obtaining a first charging duration control signal stored by the display driver, and a second charging duration control signal and image data sent by the controller;

[0037] determining a first charging duration according to the first charging duration control signal, determining a second charging duration according to the second charging duration control signal, and determining a first data voltage according to the image data;

[0038] determining a second data voltage according to the first charging duration, the second charging duration and the first data voltage, so that the display driver charges the sub-pixels according to the second data voltage and the second charging duration control signal, wherein the product of the first data voltage and the first charging duration is equal to the product of the second data voltage and the second charging duration.

[0039] In some embodiments, the display panel comprises a first transistor and a second transistor, a gate of the first transistor is connected with a first scan line, a first electrode of the first transistor is connected with the sub-pixel, a second electrode of the first transistor is connected with a first electrode of the second transistor, a gate of the second transistor is connected with a second scan line, and a second electrode of the second transistor receives the second data voltage; the first charging duration control signal comprises a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the first charging duration control signal comprises a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; and the determining the first charging duration according to the first charging duration control signal and the determining the second charging duration according to the second charging duration control signal specifically comprises:

[0040] determining the first charging duration according to the first timing signal and the second timing signal and determining the second charging duration according to the third timing signal and the fourth timing signal.

[0041] In some embodiments, the determining the first charging duration according to the first timing signal and the second timing signal and the determining the second charging duration according to the third timing signal and the fourth timing signal specifically comprises:

[0042] determining the first charging duration as a duration in which the first timing signal and the second timing signal are simultaneously high within a scanning period of a row of sub-pixels, and determining the second charging duration as a duration in which the third timing signal and the fourth timing signal are simultaneously high within the scanning period of the row of sub-pixels.

[0043] The beneficial effects of the present application include:

[0044] In the present embodiment, when the second charging duration control signal of the sub-pixel in a frame of picture driving period set by the controller and the first charging duration control signal of the sub-pixel originally burned and stored by the display driver are different, the processing unit determines the first charging duration according to the first charging duration control signal, determines the second charging duration according to the second charging duration control signal, determines the first data voltage of the sub-pixel according to the image data, the data voltage adjusting unit can determine the second data voltage according to the second charging duration, the first charging duration and the first data voltage, and then the display driver charges the sub-pixel according to the second data voltage and the second charging duration control signal, so that the brightness of the sub-pixel remains unchanged, and the problem of display abnormality can be avoided without adjusting the gamma value.

[0045] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and serve to explain the principles of the application.

[0047] Figure 1 Fig. 1 shows a structural schematic diagram of a display device provided by an exemplary embodiment of the application;

[0048] Figure 2 Fig. 2 shows a structural schematic diagram of a data voltage adjusting unit provided by an exemplary embodiment of the application;

[0049] Figure 3 Fig. 3 shows a structural schematic diagram of a division circuit provided by an exemplary embodiment of the application;

[0050] Figures 4 to 10 Fig. 4 shows structural schematic diagrams of several division circuits provided by an exemplary embodiment of the application;

[0051] Figure 11 Fig. 5 shows a structural schematic diagram of a display panel provided by an exemplary embodiment of the application;

[0052] Figure 12 Fig. 6(a) shows a GOA timing diagram of a display driver of a display panel provided by an exemplary embodiment of the application in a standard mode; Figure 12 Fig. 6(b) shows a GOA timing diagram to be set by a controller provided by an exemplary embodiment of the application;

[0053] Figure 13 Fig. 7 shows a GOA timing diagram of a display driver of a display panel provided by an exemplary embodiment of the application in a power saving mode;

[0054] Figure 14 Fig. 8 shows a corresponding relationship between timing signals provided by an exemplary embodiment of the application.

[0055] Fig. 1 shows a structural schematic diagram of a display device provided by an exemplary embodiment of the application; SRC1 Fig. 2 shows a structural schematic diagram of a data voltage adjusting unit provided by an exemplary embodiment of the application; SRC2 Fig. 3 shows a structural schematic diagram of a division circuit provided by an exemplary embodiment of the application; REF Fig. 4 shows structural schematic diagrams of several division circuits provided by an exemplary embodiment of the application; I1 Fig. 5 shows a structural schematic diagram of a display panel provided by an exemplary embodiment of the application; I2 Fig. 6(a) shows a GOA timing diagram of a display driver of a display panel provided by an exemplary embodiment of the application in a standard mode; Fig. 6(b) shows a GOA timing diagram to be set by a controller provided by an exemplary embodiment of the application; Fig. 7 shows a GOA timing diagram of a display driver of a display panel provided by an exemplary embodiment of the application in a power saving mode; Fig. 8 shows a corresponding relationship between timing signals provided by an exemplary embodiment of the application.o2 - feedback signal; 10 - first input terminal; 20 - second input terminal; 30 - third input terminal; 40 - fourth input terminal; 50 - first output terminal; 60 - co-directional input terminal; 70 - reverse input terminal; 80 - second output terminal; GND - ground terminal; TFT1 - first transistor; TFT2 - first transistor. DETAILED DESCRIPTION

[0056] When the host connected with the display panel needs to adjust the charging time of the sub-pixel of the display panel, if the charging time length of the sub-pixel set by the host in a frame driving period is different from the charging time length of the sub-pixel stored in the display driver originally, the brightness of the display panel will be abnormal or the gamma value needs to be adjusted again. For example, when the signal width of CLK (clock signal corresponding to scanning line) and MUX (multiplexer control signal) set by the host is different from the signal width of CLK (clock signal corresponding to scanning line) and MUX (multiplexer control signal) stored in the display driver originally, the charging time length of the sub-pixel set by the host will be different from the charging time length of the sub-pixel set by the display driver originally. Since the gray scale brightness of the display panel = gamma constant x gray scale data voltage x charging time length, if the charging time length of the sub-pixel set by the host is longer than the charging time length stored in the display driver originally, the brightness of the pixel will be higher, that is, the brightness of the display panel will be abnormal. However, if the display driver with the corresponding charging time length is returned to the factory for reprogramming to adapt to the requirement of adjusting the charging time length by the host, the cost will be higher.

[0057] The display driver, display driving method and display device provided in the present application are aimed at solving or improving the above technical problems of the related art.

[0058] The display driver, display driving method and display device in the embodiments of the present application will be described in detail below with reference to the drawings. The features in the following embodiments can be complementary or combined with each other without conflict.

[0059] As Figure 1As shown, the embodiment of the present application provides a display driver, which is used for a display device, the display device further comprises a controller and a display panel, the display panel comprises a sub-pixel; the display driver comprises a storage unit, a receiving unit, a processing unit and a data voltage adjusting unit. Wherein, the storage unit is configured to store a first charging duration control signal CTRL1 of the sub-pixel in a frame picture driving period, the first charging duration control signal CTRL1 is a control signal burned in the display panel and the display driver before leaving factory; the receiving unit is configured to receive a second charging duration control signal CTRL2 of the sub-pixel in the frame picture driving period and image data DSIDATA sent by the controller; the processing unit is configured to determine a first charging duration t1 according to the first charging duration control signal CTRL1, determine a second charging duration t2 according to the second charging duration control signal CTRL2, and determine a first data voltage U SRC1 according to the image data DSIDATA; the data voltage adjusting unit is configured to determine a second data voltage U SRC1 according to the first charging duration t1, the second charging duration t2 and the first data voltage U SRC2 , so that the display driver charges the sub-pixel according to the second data voltage U SRC2 and the first charging duration control signal CTRL1, wherein the product of the first data voltage U SRC1 and the first charging duration t1 is equal to the product of the second data voltage U SRC2 and the second charging duration t2.

[0060] In the embodiment, when the second charging duration control signal of the sub-pixel in the frame picture driving period set by the controller is different from the first charging duration control signal of the sub-pixel stored by the display driver originally burned, the processing unit determines the first charging duration t1 according to the first charging duration control signal, determines the second charging duration t2 according to the second charging duration control signal CTRL2, determines the first data voltage of the sub-pixel according to the image data, and the data voltage adjusting unit can determine the second data voltage U SRC1 according to the second charging duration t2, the first charging duration t1 and the first data voltage U SRC2 , and then the display driver charges the sub-pixel according to the second data voltage and the second charging duration control signal, so that the brightness of the sub-pixel remains unchanged, and the problem of display abnormality can be avoided without adjusting the gamma value.

[0061] In the embodiments of the present application, the display panel includes a plurality of sub-pixels, the image data includes first data voltages corresponding to the respective sub-pixels, the processing unit determines first charging durations corresponding to the respective sub-pixels according to a first charging duration control signal, determines second charging durations corresponding to the respective sub-pixels according to a second charging duration control signal, and the data voltage adjustment unit determines second data voltages corresponding to the respective sub-pixels. When the display panel displays, the brightness of each sub-pixel does not change, so that the overall brightness of the display panel does not change.

[0062] In some embodiments, the storage unit can be a ROM (Read-Only Memory) of the display driver.

[0063] In some embodiments, the receiving unit can be a MIPI (Mobile Industry Processor Interface) interface, or a router or Bluetooth, in which case the display driver and the controller perform signal transmission in a wireless connection manner.

[0064] In some embodiments, the display driver further includes a temporary RAM (Random Access Memory), and the first charging duration control signal CTRL1 received by the receiving unit can be stored in the temporary RAM.

[0065] In some embodiments, the processing unit can include a source driver, which can receive image data DSIDATA input by the controller and determine the first data voltage U SRC1 .

[0066] In some embodiments, as shown in Figure 2 , the data voltage adjustment unit includes a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a division operation circuit, and a first multiplier B1. The first digital-to-analog converter DAC1 is connected to the processing unit and is configured to receive the first charging duration t1 and convert the first charging duration t1 into a first voltage U I1 ; the second digital-to-analog converter DAC2 is connected to the processing unit and is configured to receive the second charging duration t2 and convert the second charging duration t2 into a second voltage U I2 ; the division operation circuit is electrically connected to the output terminals of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, respectively, and is configured to generate a feedback signal U I1 according to the first voltage U I2 and the second voltage U o2 ; the feedback signal U o2 is equal to the first voltage U I1 and the second voltage U I2a first multiplier B1 comprising a first input terminal 10 and a second input terminal 20; the first input terminal 10 is connected to the processing unit for receiving a first data voltage U SRC1 The second input terminal 20 is connected to the division circuit for receiving the feedback signal U output by the division circuit o2 The first multiplier B1 is configured to generate a first data voltage U SRC1 And feedback signal U o2 Generate the second data voltage U SRC2 , the second data voltage U SRC2 Equal to the first data voltage U SRC1 With the feedback signal U o2 The product of .

[0067] In this embodiment, the first data voltage U is converted into SRC1 Converted into the second data voltage U SRC2 , it can be realized that according to the first charging time control signal CTRL1 received by the receiving unit of the display driver, the second data voltage U corresponding to the first charging time control signal CTRL1 is determined. SRC2 , so that the brightness of the display panel remains normal.

[0068] In some embodiments, as Figure 3 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2 , the fourth input terminal 40 is connected to the second input terminal 20 of the first multiplier B1; the operational amplifier A includes a non-inverting input terminal 60, an inverting input terminal 70, and a second output terminal 80, the inverting input terminal 70 is connected to the output terminal of the first digital-to-analog converter DAC1 and the first output terminal 50 of the second multiplier B2, the non-inverting input terminal 60 is connected to the ground terminal GND, and the second output terminal 80 is connected to the second input terminal 20 of the first multiplier B1 and the fourth input terminal 40 of the second multiplier B2; the first resistor R1 is connected between the output terminal of the first digital-to-analog converter DAC1 and the inverting input terminal 70 of the operational amplifier A, and the second resistor R2 is connected between the inverting input terminal 70 of the operational amplifier A and the first output terminal 50 of the second multiplier B2, wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0069] In this embodiment, since the operational amplifier A can realize negative feedback, the first current I1 flowing through the first resistor R1 and the second current I2 flowing through the second resistor R2 are the same, that is, I1=I2, then U I1 / R1=-U o1 / R2, where the first voltage UI1 is the voltage of the circuit where the first resistor R1 is located, U o1 is the voltage of the circuit where the second resistor R2 is located (ie, the voltage output by the second multiplier B2).

[0070] Under the action of the second multiplier B2, U o1 =N2U I2 U o2 , where N2 is the product coefficient of the second multiplier B2, and the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, U o2 is the feedback signal.

[0071] Combining the above two equations, we can know that U I1 / R1=-N2U I2 U o2 / R2; the product coefficient N2 of the second multiplier B2 can be further set to -1, then U I1 / R1=U I2 U o2 / R2; and since R1=R2, then U o2 =U I1 / U I2 .

[0072] And U I1 =M1*V REF *t1,U I2 =M2*V REF *t2, where M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, V REF is the reference voltage. M1 can be further set to M2; then U o2 =t1 / t2.

[0073] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the product coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. N1 can be further set to 1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2, thus the first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 The data voltage adjustment unit provided in this embodiment has a simple structure and fewer components, and is less expensive than returning the device to the factory for re-programming.

[0074] In some embodiments, as Figure 4 As shown, the division operation circuit further includes a third resistor R3, and the third resistor R3 is connected between the non-inverting input terminal 60 of the operational amplifier A and the ground terminal GND.

[0075] In this embodiment, the third resistor R3 provides a certain degree of damping, reducing parasitic capacitance and inductive noise. In addition, if there is a risk of transient voltage or electrostatic discharge (ESD), the resistor can act as a current limiter to protect the inverting input terminal 70 of the operational amplifier A.

[0076] In some embodiments, the resistance of the third resistor R3 is less than 10 kΩ.

[0077] In some embodiments, as Figure 5 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2 , the fourth input terminal 40 is connected to the second input terminal 20 of the first multiplier B1; the operational amplifier A includes a non-inverting input terminal 60, a reverse input terminal 70 and a second output terminal 80, the non-inverting input terminal 60 is connected to the first output terminal 50 of the second multiplier B2 and the ground terminal GND, the reverse input terminal 70 is connected to the output terminal of the first digital-to-analog converter DAC1, and the second output terminal 80 is connected to the second input terminal 20 of the first multiplier B1 and the fourth input terminal 40 of the second multiplier B2; the first resistor R1 is connected between the non-inverting input terminal 60 of the operational amplifier A and the ground terminal GND, and the second resistor R2 is connected between the non-inverting input terminal 60 of the operational amplifier A and the first output terminal 50 of the second multiplier B2; wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0078] Similar to the above embodiment, in this embodiment, since the operational amplifier A can realize negative feedback, U I1 =-U o1 , where the first voltage U I1 is the voltage received by the inverting input terminal 70 of the operational amplifier A, U o1 It is the voltage input to the non-inverting input terminal 60 of the operational amplifier A.

[0079] Under the action of the second multiplying amplifier, U o1 =N2U I2 U 02 , where N2 is the product coefficient of the second multiplier B2, and the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, U o2is the feedback signal.

[0080] Combining the above two equations, we can know that U I1 =-N2U I2 U 02 , the product coefficient N2 of the second multiplier B2 can be further set to -1, then U I1 =U I2 U o2 ; then U o2 =U I1 / U I2 .

[0081] And U I1 =M1*V REF *t1,U I2 =M2*V REF *t2, where M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, V REF is the reference voltage. We can further set M1=M2; then U o2 =t1 / t2.

[0082] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the product coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. We can further set N1=1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2. The first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 value.

[0083] In some embodiments, as Figure 6 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2The fourth input end 40 is connected with the second input end 20 of the first multiplier B1; the operational amplifier A comprises a same direction input end 60, a reverse direction input end 70 and a second output end 80, the same direction input end 60 is connected with the output end of the first digital-to-analog converter DAC1, the reverse direction input end 70 is connected with the first output end 50 of the second multiplier B2 and the ground end GND, the second output end 80 is connected with the second input end 20 of the first multiplier B1 and the fourth input end 40 of the second multiplier B2; the first resistor R1 is connected between the reverse direction input end 70 of the operational amplifier A and the ground end GND, the second resistor R2 is connected between the reverse direction input end 70 of the operational amplifier A and the first output end 50 of the second multiplier B2, wherein the resistance value of the first resistor R1 is same as the resistance value of the second resistor R2.

[0084] The data voltage regulating unit provided in the embodiment has small self-excitation oscillation and high circuit stability. As the operational amplifier A can realize negative feedback effect, U I1 = -U o1 , wherein U I1 is the voltage (i.e. the first voltage U I1 ) received by the same direction input end 60 of the operational amplifier A, and U o1 is the voltage of the reverse direction input end 70 of the operational amplifier A.

[0085] Under the action of the second multiplier, U o1 = N2U I2 U 02 , wherein N2 is the product coefficient of the second multiplier B2, the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, and U o2 is the feedback signal.

[0086] According to the above two formulas, U I1 = -N2U I2 U 02 , further, the product coefficient N2 of the second multiplier B2 can be set as -1, then U I1 = U I2 U o2 ; U o2 = U I1 / U I2 .

[0087] U I1 = M1*V REF *t1, U I2 = M2*V REF *t2, wherein M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, and VREF is the reference voltage. We can further set M1=M2; then U o2 =t1 / t2.

[0088] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the product coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. We can further set N1=1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2. The first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 value.

[0089] In some embodiments, as Figure 7 As shown, the division circuit further includes a third resistor R3 connected between the non-inverting input terminal 60 of the operational amplifier A and the output terminal of the first digital-to-analog converter DAC1. The third resistor R3 can limit the current and protect the non-inverting input terminal 60.

[0090] In some embodiments, as Figure 8 As shown, the data voltage adjustment unit further includes a first capacitor C1, which is connected between the first input terminal 10 of the first multiplier B1 and the ground terminal GND. The first capacitor C1 can filter the input first data voltage U SRC1 DC noise, improve signal-to-noise ratio and enhance circuit stability.

[0091] In some embodiments, as Figure 9 As shown, the data voltage adjustment unit further includes a second capacitor C2, which is connected between the output terminal of the first multiplier B1 and the ground terminal GND. The second capacitor C2 can reduce the first multiplier B1's response to the second data voltage U SRC2 The impact of AC output.

[0092] In some embodiments, as Figure 10 As shown, the data voltage adjustment unit includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the first input terminal I0 of the first multiplier B1 and the ground terminal GND. The second capacitor C2 is connected between the output terminal of the first multiplier B1 and the ground terminal GND. The beneficial effects are the same as those of the previous embodiment and are not repeated here.

[0093] In some embodiments, as Figure 11As shown, the display panel includes a first transistor TFT1 and a second transistor TFT2, a gate of the first transistor TFT1 is connected with a first scan line, a first electrode of the first transistor TFT1 is connected with a sub-pixel, a second electrode of the first transistor TFT1 is connected with a first electrode of the second transistor TFT2, a gate of the second transistor TFT2 is connected with a second scan line, and a second electrode of the second transistor TFT2 receives a second data voltage U SRC2 ;

[0094] The first charging duration control signal CTRL1 includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line (not shown in the figure); the second charging duration control signal CTRL2 includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; and the processing unit is configured to determine the first charging duration t1 according to the first timing signal and the second timing signal, and determine the second charging duration t2 according to the third timing signal and the fourth timing signal.

[0095] The first charging duration t1 can be determined by the first timing signal and the second timing signal stored in the storage unit of the display driver, and the second charging duration t2 can be determined by the third timing signal and the fourth timing signal input by the controller. During the display driving process, the first data voltage U SRC1 input by the controller can be converted to obtain the first data voltage U SRC2 , and the second data voltage U SRC2 can be input to the second transistor TFT2 through the output end of the data voltage adjusting unit, so as to realize the charging of the sub-pixel.

[0096] In some embodiments, as shown in Figure 11 , the first scan line can be a gate line (gate line), and the second scan line can be a demux scan line (demux scan line). The first transistor TFT1 can be a switching transistor of a pixel circuit connected with the sub-pixel, and the second transistor TFT2 can be a switching transistor in a multiplexer for controlling demultiplexing. The third timing signal can be a clock signal CLK1, CLK2, CLK3, CLK4 input by the controller, and the fourth timing signal can be a multiplexer control signal MUX1, MUX2, MUX3, MUX4 input by the controller.

[0097] In some embodiments, the processing unit is specifically configured to: determine the duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods as the first charging duration t1; and determine the duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods as the second charging duration t2.

[0098] This embodiment can further determine the first charging time t1 and the second charging time t2 by setting the GOA timing signal. For example, Figure 12 (a) shows the original GOA timing diagram of the storage unit when the display driver is in the standard driving mode (MUX1-2-1-2). Figure 12 (b) shows the GOA timing diagram set by the controller. As can be seen from the figure, the MUX width of the original GOA timing stored in the storage unit of the display driver is different from the MUX width of the GOA timing set by the controller, which will further cause the sub-pixel charging time t2 to be set by the controller to be different from the sub-pixel charging time t1 originally stored by the display driver. In this example, the first timing signal is the first CLK signal stored in the storage unit of the display driver, the second timing signal is the first MUX signal stored in the storage unit of the display driver, the third timing signal is the second CLK signal input by the controller, and the fourth timing signal is the second MUX signal input by the controller. In this embodiment, the first charging time t1 can be determined by taking the time during which the first CLK signal and the first MUX signal are both high within the scanning time of a row of pixels stored in the storage unit; and the second charging time t2 can be determined by taking the time during which the second CLK signal and the second MUX signal are both high within the scanning time of a row of pixels set by the controller. In this example, the first charging time t1 is equal to the duration of the first MUX signal being at a high level, and the second charging time t2 is equal to the duration of the second MUX signal being at a high level. In one example, the first charging time t1 is 5 μs, and the second charging time t2 is 10 μs.

[0099] In other embodiments, Figure 13 As shown, Figure 13 The GOA timing diagram of the storage unit when the display driver is in the power saving driving mode (MUX1-2-2-1) is shown. In this embodiment, the first charging time t1 = (the width corresponding to the time when the first MUX signal is at a high level - Gap CLK ) / 2. Similarly, the second charging time t2 = (the width corresponding to the time when the second MUX signal is at a high level - Gap CLK ) / 2 (not shown in the figure). Then, the first data voltage U SRC1 Determine the second data voltage U SRC2 The numerical value of .

[0100] It should be noted that the first data voltage U SRC1 and the second data voltage U SRC2 may be a positive and negative flip polarity signal (SRC), as Figure 14 shown, the SRC signal can be turned on according to the opening of the SOE (display driver internal enable signal) and turned off according to the closing of the SOE.

[0101] For ease of understanding, the present application provides a specific implementation as follows:

[0102] Taking 180 gray scale as an example, assuming that the display driver of the display device performs gamma debugging, the base voltage of 180 gray scale is 4V, the compensation voltage of 180 gray scale is 0.6V, the first data voltage U SRC1 of 180 gray scale is equal to the base voltage + compensation voltage, the first data voltage U0 of 0 gray scale is 0.1V, and the first data voltage U 255 of 255 gray scale is 6V. The first charging time t1 stored in the storage unit of the display driver is 5μs, and the second charging time t2 set by the controller is 10μs. K n is the gamma constant of n gray scale, and the second data voltage U SRC2 = U SRC1 *t1 / t2, then:

[0103] The luminance corresponding to different gray scales originally set by the storage unit in the display driver is:

[0104] L180 = K 180 *U SRC1 *t1 = K 180 *(0.6V + 4V) * 5μs = 23K 180 ;

[0105] L255 = K 255 *U 255 *t1 = K 255 *6V * 5μs = 30K 255 ;

[0106] L0 = K0 * U0 * t1 = K0 * 0.1V * 5μs = 0.5K0;

[0107] The gamma value γ L180 = log(L 180 -L0) / log(L 255 -L0) = log(23K 180 -0.5K0) / log(30K 255 -0.5K0).

[0108] When the controller needs to reset the charging time of the sub-pixel, in the proportion (the display driver is not provided with the data voltage adjusting unit), the luminance corresponding to different gray scales is:

[0109] L180 = K 180 *U SRC1 *t2 = K 180 *(0.6V + 4V) * 10us = 46K 180 ;

[0110] L255 = K 255 *U 255 *t2 = K 255 *6V * 10us = 60K 255 ;

[0111] L0 = K0 * U0 * t1 / t2 * t2 = K0 * 0.1V * 5us / 10us * 10us = 0.5K0

[0112] Gamma value γ L180 = log(L 180 -L0) / log(L 255 -L0) = log(46K 180 -0.5K0) / log(60K 255 -0.5K0). In the embodiment of the application (the display driver is provided with the data voltage adjusting unit), the luminance corresponding to different gray scales is:

[0113] L180 = K 180 *U SRC2 *t2 = K 180 *U SRC1 *t1 / t2 * t2 = K 180 *(0.6V + 4V) * 5us / 10us * 10us

[0114] = 23K 180 ;

[0115] L255 = K 255 *U 255 *t1 / t2 * t2 = K 255 *6V * 5us / 10us * 10us = 30K 255 ;

[0116] L0 = K0 * U0 * t1 / t2 * t2 = K0 * 0.1V * 5us / 10us * 10us = 0.5K0

[0117] Gamma value γ L180 = log(L 180 -L0) / log(L 255 -L0) = log(23K 180 -0.5K0) / log(30K255 -0.5K0).

[0118] It can be seen that the gamma value corresponding to the display driver is obviously different from the gamma value corresponding to the controller. When the controller needs to correspondingly adjust the charging duration of the sub-pixel, using the gamma value corresponding to the display driver will cause the display brightness of the display panel to be too high, thereby causing display abnormalities. The embodiment can restore the brightness of the display panel to normal display by adjusting the data voltage, without the need to adjust the gamma value.

[0119] Based on the same inventive concept, the application further provides a display device, comprising the display driver, the controller and the display panel as described above; the display device is combined with Figure 1 As shown in the figure, the controller is configured to send a second charging duration control signal CTRL2 and image data DSIDATA to the display driver.

[0120] The display device provided by the embodiment and the display driver described above belong to the same inventive concept, and the descriptions of related details and beneficial effects can be mutually referred to, which will not be described here again.

[0121] Based on the same inventive concept, the application further provides a display driving method, combined with Figure 1 As shown in the figure, the display driving method comprises the following steps:

[0122] Step 100: acquiring a first charging duration control signal CTRL1 stored by a display driver, and a second charging duration control signal CTRL2 and image data DSIDATA sent by a controller;

[0123] Step 200: determining a first charging duration t1 according to the first charging duration control signal CTRL1, determining a second charging duration t2 according to the second charging duration control signal CTRL2, and determining a first data voltage U SRC1 according to the image data DSIDATA;

[0124] Step 300: determining a second data voltage U SRC1 according to the first charging duration t1, the second charging duration t2 and the first data voltage U SRC2 , so that the display driver charges the sub-pixel according to the second data voltage U SRC2 and the first charging duration control signal CTRL1, wherein the product of the first data voltage U SRC1 and the first charging duration t1 is equal to the product of the second data voltage U SRC2 and the second charging duration t2.

[0125] The display driving method provided by the embodiment and the display driver described above belong to the same inventive concept, and the descriptions of related details and beneficial effects can be mutually referred to, which will not be described here again, and the same applies hereinafter.

[0126] In some embodiments, the display panel comprises a first transistor TFT1 and a second transistor TFT2, a gate of the first transistor TFT1 is connected with a first scan line, a first electrode of the first transistor TFT1 is connected with the sub-pixel, a second electrode of the first transistor TFT1 is connected with a first electrode of the second transistor TFT2, a gate of the second transistor TFT2 is connected with a second scan line, and a second electrode of the second transistor TFT2 receives a second data voltage U SRC2 The first charging duration control signal CTRL1 comprises a first timing signal corresponding to the first scan line and a second timing signal corresponding to the first scan line; the first charging duration control signal CTRL1 comprises a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; and the step 200 of determining the first charging duration t1 according to the first charging duration control signal CTRL1 and determining the second charging duration t2 according to the second charging duration control signal CTRL2 specifically comprises:

[0127] The step 210 of determining the first charging duration t1 according to the first timing signal and the second timing signal and determining the second charging duration t2 according to the third timing signal and the fourth timing signal.

[0128] In some embodiments, the step 210 of determining the first charging duration t1 according to the first timing signal and the second timing signal and determining the second charging duration t2 according to the third timing signal and the fourth timing signal specifically comprises:

[0129] The duration of the first timing signal and the second timing signal being high simultaneously within a scanning period of a row of sub-pixels is determined as the first charging duration t1; and the duration of the third timing signal and the fourth timing signal being high simultaneously within a scanning period of a row of sub-pixels is determined as the second charging duration t2.

[0130] It should be noted that the terms "first", "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or a specific number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

Claims

1. A display driver, characterized in that: For a display device, the display device further includes a controller and a display panel, the display panel includes sub-pixels; the display driver includes: A storage unit configured to store a first charging duration control signal of a sub-pixel within a frame driving period; A receiving unit configured to receive a second charging duration control signal and image data of a sub-pixel within a frame driving period sent by the controller; a processing unit configured to determine a first charging duration according to the first charging duration control signal, determine a second charging duration according to the second charging duration control signal, and determine a first data voltage according to the image data; a data voltage adjustment unit configured to determine a second data voltage based on the first charging time, the second charging time, and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time; Wherein, the data voltage adjustment unit includes: a first digital-to-analog converter, connected to the processing unit, and configured to receive the first charging duration and convert the first charging duration into a first voltage; a second digital-to-analog converter, connected to the processing unit, and configured to receive the second charging duration and convert the second charging duration into a second voltage; a division circuit, electrically connected to an output terminal of the first digital-to-analog converter and an output terminal of the second digital-to-analog converter, and configured to generate a feedback signal according to the first voltage and the second voltage; the feedback signal being equal to a ratio of the first voltage to the second voltage; A first multiplier includes a first input terminal and a second input terminal; the first input terminal is connected to the processing unit and is used to receive the first data voltage; the second input terminal is connected to the division circuit and is used to receive a feedback signal output by the division circuit; the first multiplier is configured to generate the second data voltage based on the first data voltage and the feedback signal, and the second data voltage is equal to the product of the first data voltage and the feedback signal.

2. The display driver according to claim 1, wherein: The division operation circuit comprises: a second multiplier comprising a third input terminal, a fourth input terminal, and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, an inverting input terminal, and a second output terminal, wherein the inverting input terminal is connected to the output terminal of the first digital-to-analog converter and the first output terminal of the second multiplier, the non-inverting input terminal is connected to a ground terminal, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; a first resistor and a second resistor, wherein the first resistor is connected between the output terminal of the first digital-to-analog converter and the inverting input terminal of the operational amplifier, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

3. The display driver according to claim 2, wherein: The division operation circuit further includes a third resistor connected between the non-inverting input terminal of the operational amplifier and the ground terminal.

4. The display driver according to claim 1, wherein: The division operation circuit comprises: a second multiplier comprising a third input terminal, a fourth input terminal, and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, an inverting input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the first output terminal of the second multiplier and a ground terminal, the inverting input terminal is connected to the output terminal of the first digital-to-analog converter, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; a first resistor and a second resistor, wherein the first resistor is connected between the non-inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the non-inverting input terminal of the operational amplifier and the first output terminal of the second multiplier; wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

5. The display driver according to claim 1, wherein: The division operation circuit comprises: a second multiplier comprising a third input terminal, a fourth input terminal, and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, an inverting input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the output terminal of the first digital-to-analog converter, the inverting input terminal is connected to the first output terminal of the second multiplier and to ground, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; a first resistor and a second resistor, wherein the first resistor is connected between the inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

6. The display driver according to claim 5, wherein: The division operation circuit further includes a third resistor connected between the non-inverting input terminal of the operational amplifier and the output terminal of the first digital-to-analog converter.

7. The display driver according to claim 1, wherein: The data voltage adjustment unit further includes a first capacitor connected between the first input terminal of the first multiplier and a ground terminal.

8. The display driver according to claim 1, wherein: The data voltage adjustment unit further includes a second capacitor connected between the output terminal of the first multiplier and a ground terminal.

9. The display driver according to claim 1, wherein: The display panel includes a first transistor and a second transistor, wherein a gate of the first transistor is connected to a first scan line, a first electrode of the first transistor is connected to the sub-pixel, a second electrode of the first transistor is connected to a first electrode of the second transistor, a gate of the second transistor is connected to a second scan line, and a second electrode of the second transistor receives a second data voltage; The first charging duration control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the second charging duration control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; the processing unit is configured to determine the first charging duration according to the first timing signal and the second timing signal, and determine the second charging duration according to the third timing signal and the fourth timing signal.

10. The display driver according to claim 9, wherein: The processing unit is specifically configured to: determine the time duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods as the first charging time duration; and determine the time duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods as the second charging time duration.

11. A display device comprising the display driver, controller and display panel according to any one of claims 1 to 10; The controller is configured to send a second charging duration control signal and image data to the display driver.

12. A display driving method, used in the display driver of the display device according to any one of claims 1 to 11, wherein the display device further comprises a controller and a display panel, and the display panel comprises sub-pixels; the display driving method comprising: Acquire a first charging duration control signal stored in the display driver, and a second charging duration control signal and image data sent by the controller; determining a first charging duration according to the first charging duration control signal, determining a second charging duration according to the second charging duration control signal, and determining a first data voltage according to the image data; A second data voltage is determined based on the first charging time, the second charging time, and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time.

13. The display driving method according to claim 12, wherein: The display panel includes a first transistor and a second transistor, the gate of the first transistor is connected to a first scan line, the first electrode of the first transistor is connected to the sub-pixel, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to a second scan line, and the second electrode of the second transistor receives a second data voltage; the first charging time control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the first charging time control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; determining the first charging time according to the first charging time control signal and determining the second charging time according to the second charging time control signal specifically includes: The first charging duration is determined according to the first timing signal and the second timing signal, and the second charging duration is determined according to the third timing signal and the fourth timing signal.

14. The display driving method according to claim 13, wherein: Determining the first charging duration according to the first timing signal and the second timing signal, and determining the second charging duration according to the third timing signal and the fourth timing signal specifically includes: The duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods is determined as the first charging duration; and the duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods is determined as the second charging duration.

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