Detection compensation module and method thereof, display control system and electronic equipment

Abstract

The invention provides a detection compensation module and method, a display control system and electronic equipment, and relates to the technical field of display control. The detection compensation module is used for carrying out detection compensation on the signal generation module and comprises a detection unit, a comparison unit and a compensation unit; the detection unit is used for detecting an actual clock signal output by the signal generation module; the comparison unit is used for comparing the clock difference between the actual clock signal and the reference clock signal; and the compensation unit is used for compensating the signal generation module according to the clock difference and adjusting the difference between the actual clock signal and the reference clock signal to be within an allowable range. The signal generation module is compensated according to the clock difference, so that the stability and accuracy of the signal output by the signal generation module are ensured, more stable and accurate actual clock signals are provided for the display panel, the display problems of flicker and the like of the display panel are solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display control technology, and more specifically, to a detection compensation module and method thereof, a display control system and an electronic device. Background Art

[0002] A self-luminous display is a display composed of light-emitting diodes that can display text, images, and video animations. The self-luminous display has good visibility, can clearly display text and images in a dark environment, and can support the display of multiple colors. In addition, the power consumption of the self-luminous display is lower than that of traditional LCD screens, which can save more energy. ASIC (Application-Specific Integrated Circuit) is an integrated circuit designed specifically for specific application scenarios. It can complete specific tasks faster and more efficiently than ordinary microprocessors, and can implement complex algorithms such as machine learning, image processing, and data analysis, thereby improving the overall performance of the system. Among them, ASIC LocalDimming is a new local dimming solution, which has been widely used in some self-luminous displays. However, the stability of existing ASIC chips is poor, and it is easy to produce large fluctuations in the output signal, which ultimately leads to display problems such as flickering on the self-luminous display. Summary of the invention

[0003] In view of this, the present application provides a detection compensation module and method thereof, a display control system and an electronic device, which effectively solve the technical problems existing in the prior art, compensate the signal generating module according to the clock difference, and then adjust the difference between the actual clock signal and the reference clock signal within an allowable range, thereby ensuring the stability and accuracy of the output signal of the signal generating module, improving display problems such as flickering of the display panel, and improving the display effect of the display panel.

[0004] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0005] A detection compensation module, used for performing detection compensation on a signal generation module, the detection compensation module comprising a detection unit, a comparison unit and a compensation unit;

[0006] The detection unit is used to detect the actual clock signal output by the signal generation module;

[0007] The comparison unit is used to compare the clock difference between the actual clock signal and the reference clock signal;

[0008] The compensation unit is used to compensate the signal generation module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0009] Optionally, the detection unit includes a clock counter, and the clock counter is used to detect the actual clock signal.

[0010] Optionally, the clock counter includes a first D-type flip-flop, a second D-type flip-flop, a third D-type flip-flop, a first XOR gate, a second XOR gate and a NAND gate;

[0011] The data input terminal of the first D-type flip-flop is electrically connected to the inverted code output terminal of the first D-type flip-flop, the clock input terminal of the first D-type flip-flop is connected to the actual clock signal, and the original code output terminal of the first D-type flip-flop is electrically connected to the first input terminal of the first XOR gate, the second input terminal of the NAND gate, and the input terminal of the comparison unit;

[0012] The data input terminal of the second D-type flip-flop is electrically connected to the output terminal of the first XOR gate, the clock input terminal of the second D-type flip-flop is connected to the actual clock signal, the original code output terminal of the second D-type flip-flop is electrically connected to the second input terminal of the first XOR gate, the first input terminal of the NAND gate and the input terminal of the comparison unit, and the output terminal of the NAND gate is electrically connected to the first input terminal of the second XOR gate;

[0013] The data input terminal of the third D-type flip-flop is electrically connected to the output terminal of the second XOR gate, the clock input terminal of the third D-type flip-flop is connected to the actual clock signal, and the original code output terminal of the third D-type flip-flop is electrically connected to the second input terminal of the second XOR gate and the input terminal of the comparison unit.

[0014] Optionally, the comparison unit includes a micro control unit, an input end of the micro control unit is electrically connected to an output end of the detection unit and the reference clock signal, and an output end of the micro control unit is electrically connected to an input end of the compensation unit.

[0015] Optionally, the compensation unit is used to perform voltage compensation on the power supply voltage of the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0016] Optionally, the detection compensation module further includes a storage unit, wherein the storage unit stores a mapping data table of multiple clock ranges and their corresponding compensation voltages;

[0017] The compensation unit is used to compensate the power supply voltage of the signal generating module by the corresponding compensation voltage according to the clock range where the clock difference is located, so as to adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0018] Optionally, the compensation unit includes a programmable power supply circuit, and the programmable power supply circuit is used to perform voltage compensation on the power supply voltage of the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0019] Based on the same inventive concept, the present application also provides a detection compensation method for performing detection compensation on a signal generating module, the detection compensation method comprising:

[0020] Detecting an actual clock signal output by the signal generating module;

[0021] comparing a clock difference between the actual clock signal and a reference clock signal;

[0022] The signal generating module is compensated according to the clock difference, and the difference between the actual clock signal and the reference clock signal is adjusted to be within an allowable range.

[0023] Optionally, compensating the signal generating module according to the clock difference includes:

[0024] Voltage compensation is performed on the power supply voltage of the signal generating module according to the clock difference.

[0025] Optionally, performing voltage compensation on the power supply voltage of the signal generating module according to the clock difference includes:

[0026] Searching a mapping data table according to the clock difference, wherein the mapping data table is a data table of multiple clock ranges and their corresponding compensation voltages;

[0027] Determine the compensation voltage corresponding to the clock range to which the clock difference belongs;

[0028] The compensation voltage is compensated for the power supply voltage of the signal generating module, and the difference between the actual clock signal and the reference clock signal is adjusted to be within an allowable range.

[0029] Based on the same inventive concept, the present application also provides a display control system for controlling a display panel, the display control system comprising a video input module, a signal generation module and the above-mentioned detection compensation module;

[0030] The video input module is used to generate a display data signal based on the input video data;

[0031] The signal generating module is used to generate a display control signal according to the display data signal and send the display control signal to the display panel, wherein the display control signal includes an actual clock signal;

[0032] The detection and compensation module is used to detect the actual clock signal, and after comparing the clock difference between the actual clock signal and the reference clock signal, compensate the signal generation module according to the clock difference to adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0033] Optionally, the signal generating module includes an ASIC module.

[0034] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned display control system and a display panel electrically connected to the display control system.

[0035] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0036] The present application provides a detection and compensation module and method thereof, a display control system and an electronic device. The detection and compensation module is used to detect and compensate a signal generating module. The detection and compensation module includes a detection unit, a comparison unit and a compensation unit. The detection unit is used to detect an actual clock signal output by the signal generating module. The comparison unit is used to compare the clock difference between the actual clock signal and a reference clock signal. The compensation unit is used to compensate the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0037] From the above content, it can be seen that the technical solution provided by the present application compensates the signal generating module according to the clock difference, and then adjusts the difference between the actual clock signal and the reference clock signal within the allowable range, thereby ensuring the stability and accuracy of the output signal of the signal generating module, thereby providing a more stable and accurate actual clock signal for the display panel, improving display problems such as flickering of the display panel, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of the structure of a detection compensation module provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of another detection compensation module provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a clock counter provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of another detection compensation module provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of another detection compensation module provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of mapping a cycle number range and a supply voltage provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of the structure of another detection compensation module provided in an embodiment of the present application;

[0046] Figure 8 A flow chart of a detection compensation method provided in an embodiment of the present application;

[0047] Fig. 9 A flowchart of another detection compensation method provided in an embodiment of the present application;

[0048] Fig.10 A flowchart of another detection compensation method provided in an embodiment of the present application;

[0049] Fig.11 A schematic diagram of the structure of a display control system provided in an embodiment of the present application;

[0050] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 10-signal generation module; 20-detection compensation module; 21-detection unit; 210-clock counter; 22-comparison unit; 220-micro control unit; 23-compensation unit; 230-programmable power supply circuit; 231-step-down circuit; 232-boost circuit; 24-storage unit; 100-display panel; 200-display control system; 1000-electronic device; TXclk-actual clock signal, Pclk-reference clock signal; F1-first D-type trigger; F2-second D-type trigger; F3-third D-type trigger; C1-clock input terminal; 1D-data input terminal; Q1-inverted code output terminal; Q2-original code output terminal; G1-first XOR gate; G2 second XOR gate; G3-NAND gate. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] As described in the background technology, a self-luminous display screen is a display screen composed of light-emitting diodes, which can display text, images and video animations. The self-luminous display screen has good visibility, can clearly display text and images in a dark environment, and can support the display of multiple colors. In addition, the power consumption of the self-luminous display screen is lower than that of a traditional liquid crystal display screen, which can save more energy. ASIC, i.e., application-specific integrated circuit, is an integrated circuit designed specifically for a specific application scenario. It can complete specific tasks faster and more efficiently than ordinary microprocessors, and can implement complex algorithms such as machine learning, image processing and data analysis, thereby improving the overall performance of the system. Among them, ASIC Local Dimming is a brand-new local dimming solution, which has now been widely used in some self-luminous display screens, especially in display devices of some vehicles. However, the stability of existing ASIC chips is poor, and it is easy to produce the problem that the output signal has a large fluctuation, which ultimately leads to display problems such as flickering on the self-luminous display screen.

[0055] It is understandable that ASIC-related chips include algorithm modules, whose internal circuits are complex and include multiple timing generation circuits. Slight fluctuations in the input signals of ASIC-related chips will cause abnormal functions of the product. Considering that the stability of the timing generation circuit is affected by temperature, power supply voltage and sample differences, the actual clock signal output by the timing generation circuit may fluctuate due to offset. Therefore, the present application provides a solution for performing different compensations on ASIC-related chips in different working states to improve their working performance.

[0056] Based on this, the embodiments of the present application provide a detection compensation module and method thereof, a display control system and an electronic device, which effectively solve the technical problems existing in the prior art, compensate the signal generating module according to the clock difference, and then adjust the difference between the actual clock signal and the reference clock signal within an allowable range, thereby ensuring the stability and accuracy of the output signal of the signal generating module, improving display problems such as flickering of the display panel, and improving the display effect of the display panel.

[0057] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figures 1 to 12 The technical solution provided in the embodiments of the present application is described in detail.

[0058] refer to Figure 1 As shown, it is a structural schematic diagram of a detection and compensation module provided in an embodiment of the present application, wherein the detection and compensation module 20 provided in an embodiment of the present application is used to detect and compensate the signal generation module 10, and the detection and compensation module 20 includes a detection unit 21, a comparison unit 22 and a compensation unit 23. The detection unit 21 is used to detect the actual clock signal TXclk output by the signal generation module 10. The comparison unit 22 is used to compare the clock difference between the actual clock signal TXclk and the reference clock signal Pclk; the compensation unit 23 is used to compensate the signal generation module 10 according to the clock difference, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within an allowable range. Among them, the allowable range needs to be adjusted according to the actual application, such as the difference between the actual clock signal TXclk and the reference clock signal Pclk is 0; or in some embodiments, the difference between the actual clock signal TXclk and the reference clock signal Pclk can be so small that it can be ignored, and this application does not make specific restrictions on this.

[0059] It can be understood that the signal generating module 10 is a module for providing a display control signal for the display panel 100, wherein the display control signal at least includes the actual clock signal TXclk. The technical solution provided in the embodiment of the present application compensates the signal generating module 10 according to the time difference, and then adjusts the difference between the actual clock signal TXclk and the reference clock signal within the allowable range, thereby ensuring the stability and accuracy of the signal output by the signal generating module 10. Since the signal generating module 10 is used to provide the display panel 100 with the actual clock signal TXclk for display control, improving the stability and accuracy of the actual clock signal TXclk output by the signal generating module 10 is equivalent to providing the display panel 100 with a more stable and accurate actual clock signal TXclk, thereby improving the display problems such as flickering of the display panel 100, and improving the display effect of the display panel 100.

[0060] In some embodiments, the parameter of the actual clock signal TXclk detected by the detection unit 21 provided in the embodiments of the present application may be the number of cycles of the actual clock signal TXclk. Figure 2 As shown, it is a structural schematic diagram of another detection compensation module provided in an embodiment of the present application, wherein the detection unit 21 provided in the embodiment of the present application includes a clock counter 210, and the clock counter 210 is used to detect the actual clock signal TXclk, and actually detect the number of cycles of the actual clock signal TXclk, so as to compare the clock difference between the number of cycles of the actual clock signal TXclk and the number of cycles of the reference clock signal Pclk through the comparison unit 22, that is, to compare the difference between the number of cycles of the actual clock signal TXclk and the number of cycles of the reference clock signal Pclk, and achieve the purpose of compensating the signal generation module 10 according to the difference in the number of cycles.

[0061] Specific reference Figure 3As shown, it is a structural schematic diagram of a clock counter provided in an embodiment of the present application, wherein the clock counter 210 provided in the embodiment of the present application includes a first D-type trigger F1, a second D-type trigger F2, a third D-type trigger F3, a first XOR gate G1, a second XOR gate G2 and a NAND gate G3; the data input terminal 1D of the first D-type trigger F1 is electrically connected to the inverted code output terminal Q1 of the first D-type trigger F1, the clock input terminal C1 of the first D-type trigger F1 is connected to the actual clock signal TXclk, and the original code output terminal Q2 of the first D-type trigger F1 is electrically connected to the first input terminal of the first XOR gate G1, the second input terminal of the NAND gate G3 and the input terminal of the comparison unit 22. The data input terminal 1D of the second D-type flip-flop F2 is electrically connected to the output terminal of the first XOR gate G1, the clock input terminal C1 of the second D-type flip-flop F2 is connected to the actual clock signal TXclk, the original code output terminal Q2 of the second D-type flip-flop F2 is electrically connected to the second input terminal of the first XOR gate G1, the first input terminal of the NAND gate G3 and the input terminal of the comparison unit 22, and the output terminal of the NAND gate G3 is electrically connected to the first input terminal of the second XOR gate G2. The data input terminal 1D of the third D-type flip-flop F3 is electrically connected to the output terminal of the second XOR gate G2, the clock input terminal C1 of the third D-type flip-flop F3 is connected to the actual clock signal TXclk, and the original code output terminal Q2 of the third D-type flip-flop F3 is electrically connected to the second input terminal of the second XOR gate G2 and the input terminal of the comparison unit 22.

[0062] It should be noted that the embodiments of this application Figure 3 The clock counter 210 shown is only one of all counter structures applicable to this application. The clock counter 210 provided in the embodiment of the present application is not limited to being composed of three D-type flip-flops. In some other embodiments, the clock counter 210 provided in the embodiment of the present application can also be composed of more D-type flip-flops, or composed of some other types of flip-flops, such as SR flip-flops, JK flip-flops, etc. This application does not make specific restrictions on this, and needs to be specifically designed according to actual applications.

[0063] When the detection unit 21 detects the actual clock signal TXclk output by the signal generation module 10 and obtains the corresponding data parameters, the data parameters are sent to the comparison unit 22 so as to compare the data parameters with the reference clock signal Pclk through the comparison unit 22. That is, after the clock counter 210 detects the actual clock signal TXclk output by the signal generation module 10 and obtains the corresponding number of cycles, the data related to the number of cycles is sent to the comparison unit 22. The comparison unit 22 is also connected to the reference clock signal Pclk. The comparison unit 22 compares the number of cycles of the actual clock signal TXclk with the number of cycles of the reference clock signal Pclk, and then outputs the corresponding comparison result to the compensation unit 23 for corresponding processing. In some embodiments, the comparison unit 22 provided in the embodiments of the present application involves complex functions such as comparison and analysis, so the comparison unit 22 can implement related functions through a microcontroller unit (MCU). Figure 4 As shown, it is a structural schematic diagram of another detection compensation module provided in an embodiment of the present application, wherein the comparison unit 22 provided in the embodiment of the present application includes a micro control unit 220, the input end of the micro control unit 220 is electrically connected to the output end of the detection unit 21 and the reference clock signal Pclk, the output end of the micro control unit 220 is electrically connected to the input end of the compensation unit 23, the data processing capability of the micro control unit 220 is relatively high, and the processing efficiency of the detection compensation module 20 is improved.

[0064] After the comparison unit 22 compares the actual clock signal TXclk and the reference clock signal Pclk to obtain the clock difference, the comparison result will be output to the compensation unit 23. The compensation unit 23 compensates the signal generation module 10 according to the clock difference, thereby reducing the difference between the actual clock signal TXclk and the reference clock signal Pclk. Since the signal generation module 10 is affected by temperature, power supply voltage and sample differences, the actual clock signal TXclk will fluctuate, and the temperature and sample differences are equivalent to features that cannot be manually intervened. Therefore, the embodiment of the present application can adjust and compensate the power supply voltage of the signal generation module 10, thereby achieving the purpose of eliminating the influence of temperature, power supply voltage and sample differences on the abnormal function of the signal generation module 10. That is, the compensation unit 23 provided in the embodiment of the present application is used to perform voltage compensation on the power supply voltage of the signal generation module 10 according to the clock difference, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within the allowable range.

[0065] Optionally, when the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk, it can be indicated that the power supply voltage of the signal generation module 10 is large, and thus the corresponding negative voltage can be compensated for the power supply voltage to reduce the power supply voltage, thereby improving the difference between the actual clock signal TXclk and the reference clock signal Pclk. And, when the number of cycles of the actual clock signal TXclk is less than the number of cycles of the reference clock signal Pclk, it can be indicated that the power supply voltage of the signal generation module 10 is small, and thus the corresponding positive voltage can be compensated for the power supply voltage to increase the power supply voltage, thereby improving the difference between the actual clock signal TXclk and the reference clock signal Pclk. In some embodiments, the compensation unit 23 provided in the embodiments of the present application may compensate for the power supply voltage with a fixed voltage; that is, when the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk, regardless of the size of the difference in the number of cycles, a negative voltage of a fixed value for supply voltage compensation is used, and the negative voltage of the fixed value may be an optimized value set based on experience; and when the number of cycles of the actual clock signal TXclk is less than the number of cycles of the reference clock signal Pclk, regardless of the size of the difference in the number of cycles, a positive voltage of a fixed value for supply voltage compensation is used, and the positive voltage of the fixed value may also be an optimized value set based on experience.

[0066] Furthermore, in order to adjust the power supply voltage more finely, the present application can also determine the difference level of the clock difference, and compensate the current power supply voltage of the signal generating module 10 with different compensation voltages according to different difference levels. Figure 5 As shown, it is a structural schematic diagram of another detection and compensation module provided in an embodiment of the present application, wherein the detection and compensation module 20 provided in the embodiment of the present application also includes a storage unit 24, and the storage unit 24 stores a mapping data table of multiple clock ranges and their corresponding compensation voltages; wherein the compensation unit 23 is used to compensate the power supply voltage of the signal generating module 10 with the corresponding compensation voltage according to the clock range where the clock difference is located, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk within an allowable range, thereby realizing accurate compensation for the power supply voltage, improving the compensation effect of the power supply voltage, and further improving the stability and accuracy of the output signal of the signal generating module 10.

[0067] In some embodiments, the clock range and compensation voltage provided by the embodiments of the present application can be divided by setting corresponding thresholds. For example, a cycle number threshold is set to Zx, and a compensation step voltage is set to Vx. Taking the case where the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk as an example, the division of the clock range, that is, the division of the cycle number range, can be specifically [2*Zx, 4*Zx), [4*Zx, 6*Zx), [6*Zx, 8*Zx), and so on; the corresponding compensation voltage (in V) can be Vx, 1.5*Vx, 2*Vx, and so on; so that the power supply voltage of the signal generation module 10 is (1.2-Vx), (1.2-1.5*Vx), (1.2-2*Vx), and so on, where 1.2 is the power supply voltage of the signal generation module 10 under normal conditions. Therefore, when the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk, the difference in the number of cycles of the actual clock signal TXclk and the number of cycles of the reference clock signal Pclk is determined, and then the range of cycles to which the difference in the number of cycles belongs is determined, and finally the corresponding compensation voltage is determined. In addition, an allowable difference range is set in the range of cycles provided in the embodiment of the present application, such as the allowable difference range of [0, 2*Zx); when the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk, and the difference in the number of cycles is within the allowable difference range, it is determined that the difference in the number of cycles does not affect the subsequent control and display effect of the display panel, and therefore the current power supply voltage of the signal generation module 10 may not be compensated. Specifically combined with Figure 6 As shown, it is a schematic diagram of mapping the cycle number range and the power supply voltage provided in an embodiment of the present application. When the clock difference is in the cycle number range [0, 2*Zx), it is a normal state; when it is in the range of [2*Zx, 4*Zx), it is abnormal state 1; when it is in the range of [4*Zx, 6*Zx), it is abnormal state 2; when it is in the range of [6*Zx, 8*Zx), it is abnormal state 3, and so on; the corresponding compensation voltage (in V) is 0 in the normal state, Vx in the abnormal state 1, 1.5*Vx in the abnormal state 2, 2*Vx in the abnormal state 3, and so on; thereby, the power supply voltage is 1.2V in the normal state, (1.2-Vx) in the abnormal state 1, (1.2-1.5*Vx) in the abnormal state 2, (1.2-2*Vx) in the abnormal state 3, and so on.

[0068] In some embodiments, the storage unit 24 provided in the embodiment of the present application can be integrated into the comparison unit 22. After the comparison unit 22 has completed the comparison processing of the number of cycles of the actual clock signal TXclk being less than the number of cycles of the reference clock signal Pclk, the clock difference and the corresponding compensation voltage data are sent to the compensation unit 23 as the comparison result, so that the compensation unit 23 directly outputs the corresponding compensation voltage to the current power supply voltage of the signal generation module 10 according to the comparison result. Alternatively, the storage unit 24 provided in the embodiment of the present application can also be integrated into the compensation unit 23. After the comparison unit 22 has completed the comparison processing of the number of cycles of the actual clock signal TXclk being less than the number of cycles of the reference clock signal Pclk, the clock difference is sent to the compensation unit 23. The compensation unit 23 searches for the corresponding compensation voltage in the storage unit 24 according to the clock difference, and then outputs the compensation voltage to the current power supply voltage of the signal generation module 10. Alternatively, the storage unit 24 provided in the embodiment of the present application is an independent unit, which can search for the compensation voltage according to the clock difference through the comparison unit 22, and then send it to the compensation unit 23; or it can directly search for the compensation voltage according to the clock difference through the compensation unit 23, and then output the corresponding compensation voltage to the power supply voltage for compensation. This application does not make any specific restrictions on this.

[0069] refer to Figure 7 As shown, it is a structural schematic diagram of another detection compensation module provided in an embodiment of the present application, wherein the compensation unit 23 provided in an embodiment of the present application includes a programmable power supply circuit 230, and the programmable power supply circuit 230 is used to perform voltage compensation on the power supply voltage of the signal generating module 10 according to the clock difference, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk within an allowable range. In some embodiments, the programmable power supply circuit 230 provided in an embodiment of the present application may include a buck circuit 231 and / or a boost circuit 232, and the buck circuit 231 and the boost circuit 232 are connected to the reference voltage Vref, and the required compensation voltage is output by bucking or boosting the reference voltage Vref. Optionally, the programmable power supply circuit 230 provided in an embodiment of the present application may only include a buck circuit 231, and the power supply voltage of the signal generating module 10 is compensated by bucking, which can reduce power consumption.

[0070] It should be noted that, in the detection and compensation module 20 provided in the embodiment of the present application, the detection unit 21 included therein is not limited to realizing related functions through the clock counter 210, the comparison unit 22 included therein is not limited to realizing related functions through the microcontroller unit 220, and the compensation unit 23 included therein is not limited to realizing related functions through the programmable power supply circuit 230. This needs to be specifically designed according to the actual application, and it is only necessary to make the detection and compensation module 20 meet the following functional conditions, namely: detecting the actual clock signal TXclk output by the signal generating module 10; comparing the clock difference between the actual clock signal TXclk and the reference clock signal Pclk; compensating the signal generating module 10 according to the clock difference, and adjusting the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within the allowable range.

[0071] Based on the same inventive concept, the embodiment of the present application further provides a detection compensation method, based on the detection compensation module 20 provided in any of the above embodiments, the detection compensation method is used to perform detection compensation on the signal generating module 10. Figure 8 FIG. 1 is a flow chart of a detection compensation method provided in an embodiment of the present application, wherein the detection compensation method provided in an embodiment of the present application includes:

[0072] S1. Detecting the actual clock signal output by the signal generating module 10.

[0073] S2. Compare the clock difference between the actual clock signal TXclk and the reference clock signal Pclk.

[0074] S3. Compensate the signal generating module 10 according to the clock difference, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within an allowable range.

[0075] As can be seen from the above content, the signal generating module 10 is a module for providing a display control signal for the display panel 100, wherein the display control signal at least includes an actual clock signal TXclk. The detection compensation method provided in the embodiment of the present application compensates the signal generating module 10 according to the clock difference, and then adjusts the difference between the actual clock signal TXclk and the reference clock signal within the allowable range, thereby ensuring the stability and accuracy of the signal output by the signal generating module 10. Since the signal generating module 10 is used to provide the display panel 100 with an actual clock signal TXclk for display control, improving the stability and accuracy of the actual clock signal TXclk output by the signal generating module 10 is equivalent to providing the display panel 100 with a more stable and accurate actual clock signal TXclk, thereby improving the display problems such as flickering of the display panel 100, and improving the display effect of the display panel 100.

[0076] In some embodiments, the clock difference between comparing the actual clock signal TXclk and the reference clock signal Pclk provided in the embodiments of the present application may be a difference in the number of cycles between comparing the number of cycles of the actual clock signal TXclk and the number of cycles of the reference clock signal Pclk.

[0077] Since the signal generation module 10 is affected by temperature, power supply voltage and sample differences, the actual clock signal TXclk will fluctuate, and temperature and sample differences are equivalent to features that cannot be manually intervened. Therefore, the embodiment of the present application can adjust and compensate the power supply voltage of the signal generation module 10 to achieve the purpose of eliminating the influence of temperature, power supply voltage and sample differences on the abnormal function of the signal generation module 10. Fig. 9 As shown, it is a flow chart of another detection compensation method provided in an embodiment of the present application, wherein, in step S3 provided in the embodiment of the present application, the signal generating module 10 is compensated according to the clock difference, including: voltage compensation of the power supply voltage of the signal generating module 10 according to the clock difference.

[0078] In some embodiments, in the detection compensation method provided in the embodiments of the present application, the compensation for the power supply voltage can be a fixed voltage compensation. Wherein, when the number of cycles of the actual clock signal TXclk is greater than the number of cycles of the reference clock signal Pclk, regardless of the size of the difference in the number of cycles, the power supply voltage is compensated by a fixed negative voltage, and the fixed negative voltage can be an optimized value set based on experience; and when the number of cycles of the actual clock signal TXclk is less than the number of cycles of the reference clock signal Pclk, regardless of the size of the difference in the number of cycles, the power supply voltage is compensated by a fixed positive voltage, and the fixed positive voltage can also be an optimized value set based on experience.

[0079] Furthermore, in order to adjust the power supply voltage more finely, the present application can also determine the difference level of the clock difference, and compensate the current power supply voltage of the signal generating module 10 with different compensation voltages according to different difference levels. Fig.10 FIG. 1 is a flowchart of another detection compensation method provided by an embodiment of the present application, wherein in step S3, the voltage compensation of the power supply voltage of the signal generating module according to the clock difference includes:

[0080] S31 . Search a mapping data table according to the clock difference, where the mapping data table is a data table of multiple clock ranges and their corresponding compensation voltages.

[0081] S32: Determine the compensation voltage corresponding to the clock range to which the clock difference belongs.

[0082] S33 , compensating the power supply voltage of the signal generating module 10 by the compensation voltage, and adjusting the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within an allowable range.

[0083] It can be understood that the clock difference is judged according to the difference level, and the current power supply voltage of the signal generating module 10 is compensated with different compensation voltages according to the different difference levels, thereby achieving accurate compensation for the power supply voltage, improving the compensation effect of the power supply voltage, and further improving the stability and accuracy of the output signal of the signal generating module 10.

[0084] Based on the same inventive concept, the embodiment of the present application further provides a display control system 200 for controlling the display panel 100. Fig.11 As shown, it is a structural schematic diagram of a display control system provided by an embodiment of the present application, wherein the display control system 200 provided by an embodiment of the present application includes a video input module 30, a signal generation module 10 and a detection compensation module 20 provided by any one of the above embodiments. The video input module 30 is used to generate a display data signal based on the accessed video data; the signal generation module 10 is used to generate a display control signal according to the display data signal and send it to the display panel 100, wherein the display control signal includes an actual clock signal. And, the detection compensation module 20 is used to detect the actual clock signal TXclk, and after comparing the clock difference between the actual clock signal TXclk and the reference clock signal Pclk, compensate the signal generation module 10 according to the clock difference, and adjust the difference between the actual clock signal TXclk and the reference clock signal Pclk to be within the allowable range.

[0085] In some embodiments, the signal generating module 10 provided in the embodiments of the present application includes an ASIC module, and the detection and compensation module 20 is used to detect and compensate for the actual clock signal TXclk output by the ASIC module. The present application does not make any specific restrictions on the type of the signal generating module 10.

[0086] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes the display control system provided by any one of the above embodiments, and a display panel electrically connected to the display control system.

[0087] refer to Fig.12 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, wherein the electronic device 1000 provided in an embodiment of the present application can be a display device for a vehicle.

[0088] In some other embodiments of the present application, the electronic device 1000 provided in the embodiments of the present application may also be a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, etc., and the present invention does not make any specific limitation on this.

[0089] The embodiments of the present application provide a detection and compensation module and method thereof, a display control system and an electronic device. The detection and compensation module is used to detect and compensate a signal generating module. The detection and compensation module includes a detection unit, a comparison unit and a compensation unit. The detection unit is used to detect an actual clock signal output by the signal generating module. The comparison unit is used to compare the clock difference between the actual clock signal and a reference clock signal. The compensation unit is used to compensate the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

[0090] From the above content, it can be seen that the technical solution provided in the embodiment of the present application compensates the signal generating module according to the clock difference, and then adjusts the difference between the actual clock signal and the reference clock signal within the allowable range, thereby ensuring the stability and accuracy of the output signal of the signal generating module, thereby providing a more stable and accurate actual clock signal for the display panel, improving display problems such as flickering of the display panel, and improving the display effect of the display panel.

[0091] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0092] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0093] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0094] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0095] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0096] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A detection compensation module, used for performing detection compensation on a signal generation module, characterized in that: The detection and compensation module includes a detection unit, a comparison unit and a compensation unit; The detection unit is used to detect the actual clock signal output by the signal generation module; The comparison unit is used to compare the clock difference between the actual clock signal and the reference clock signal; The compensation unit is used to compensate the signal generation module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

2. The detection compensation module according to claim 1, characterized in that: The detection unit includes a clock counter, and the clock counter is used to detect the actual clock signal.

3. The detection compensation module according to claim 2, characterized in that: The clock counter comprises a first D-type flip-flop, a second D-type flip-flop, a third D-type flip-flop, a first XOR gate, a second XOR gate and a NAND gate; The data input terminal of the first D-type flip-flop is electrically connected to the inverted code output terminal of the first D-type flip-flop, the clock input terminal of the first D-type flip-flop is connected to the actual clock signal, and the original code output terminal of the first D-type flip-flop is electrically connected to the first input terminal of the first XOR gate, the second input terminal of the NAND gate, and the input terminal of the comparison unit; The data input terminal of the second D-type flip-flop is electrically connected to the output terminal of the first XOR gate, the clock input terminal of the second D-type flip-flop is connected to the actual clock signal, the original code output terminal of the second D-type flip-flop is electrically connected to the second input terminal of the first XOR gate, the first input terminal of the NAND gate and the input terminal of the comparison unit, and the output terminal of the NAND gate is electrically connected to the first input terminal of the second XOR gate; The data input terminal of the third D-type flip-flop is electrically connected to the output terminal of the second XOR gate, the clock input terminal of the third D-type flip-flop is connected to the actual clock signal, and the original code output terminal of the third D-type flip-flop is electrically connected to the second input terminal of the second XOR gate and the input terminal of the comparison unit.

4. The detection compensation module according to claim 1, characterized in that: The comparison unit comprises a micro control unit, an input end of the micro control unit is electrically connected to an output end of the detection unit and the reference clock signal, and an output end of the micro control unit is electrically connected to an input end of the compensation unit.

5. The detection compensation module according to claim 1, characterized in that: The compensation unit is used to perform voltage compensation on the power supply voltage of the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

6. The detection compensation module according to claim 5, characterized in that: The detection compensation module further includes a storage unit, wherein the storage unit stores a mapping data table of multiple clock ranges and their corresponding compensation voltages; The compensation unit is used to compensate the power supply voltage of the signal generating module by the corresponding compensation voltage according to the clock range where the clock difference is located, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

7. The detection compensation module according to claim 5, characterized in that: The compensation unit includes a programmable power supply circuit, which is used to perform voltage compensation on the power supply voltage of the signal generating module according to the clock difference, and adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

8. A detection compensation method for performing detection compensation on a signal generation module, characterized in that: The detection compensation method comprises: Detecting an actual clock signal output by the signal generating module; comparing a clock difference between the actual clock signal and a reference clock signal; The signal generating module is compensated according to the clock difference, and the difference between the actual clock signal and the reference clock signal is adjusted to be within an allowable range.

9. The detection compensation method according to claim 8, characterized in that: The compensating the signal generating module according to the clock difference comprises: Voltage compensation is performed on the power supply voltage of the signal generating module according to the clock difference.

10. The detection compensation method according to claim 9, characterized in that: The performing voltage compensation on the supply voltage of the signal generating module according to the clock difference includes: Searching a mapping data table according to the clock difference, wherein the mapping data table is a data table of multiple clock ranges and their corresponding compensation voltages; Determine the compensation voltage corresponding to the clock range to which the clock difference belongs; The compensation voltage is compensated for the power supply voltage of the signal generating module, and the difference between the actual clock signal and the reference clock signal is adjusted to be within an allowable range.

11. A display control system for controlling a display panel, characterized in that: The display control system comprises a video input module, a signal generation module and a detection compensation module according to any one of claims 1 to 7; The video input module is used to generate a display data signal based on the input video data; The signal generating module is used to generate a display control signal according to the display data signal and send the display control signal to the display panel, wherein the display control signal includes an actual clock signal; The detection and compensation module is used to detect the actual clock signal, and after comparing the clock difference between the actual clock signal and the reference clock signal, compensate the signal generation module according to the clock difference to adjust the difference between the actual clock signal and the reference clock signal to be within an allowable range.

12. The display control system according to claim 11, characterized in that: The signal generating module comprises an ASIC module.

13. An electronic device, characterized in that: The electronic device comprises the display control system according to claim 12, and a display panel electrically connected to the display control system.

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