Pixel driving circuit and display panel

Abstract

The invention discloses a pixel driving circuit and a display panel. The pixel driving circuit comprises a pulse width modulation module which comprises k1 first data input ends, each first data input end is used for inputting one-bit data of gray scale data, and the pulse width modulation module is used for outputting a pulse width modulation signal from a data output end according to the gray scale data; at least k1 data read-write modules, each first data input end of the pulse width modulation module is electrically connected with one data read-write module, and k1 is the bit number of gray scale data; the data read-write module comprises a first data write-in unit, a first storage unit, a first data write-out unit and a second storage unit; the first data writing unit is used for responding to an external gating signal and writing gray scale data into the first storage unit; the first data write-out unit responds to the frame refresh signal and writes the data stored in the first storage unit into the first data input end; the second storage unit is used for maintaining the potential of the first data input end. The area of the pixel driving circuit can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] Micro LED (Micro Light Emitting Diode) has the advantages of high brightness, low power consumption and long life, and is considered to be a strong competitor for the next generation of display technology. Micro LED needs to be driven by a pixel driving circuit, such as an active pixel driving circuit.

[0003] However, as the size of Micro LED devices decreases and the pixel density increases, the number of pixel driving circuits required also increases exponentially. In other words, a large number of pixel driving circuits need to be integrated within the limited area of ​​the display panel, which makes the design of the pixel driving circuit more complicated or requires increasing the area of ​​the pixel driving circuit.

[0004] In the related art, the pixel driving circuit occupies a large area of ​​the display panel, which limits the further improvement of the pixel density. Summary of the invention

[0005] The present invention provides a pixel driving circuit and a display panel, so as to reduce the area of ​​the pixel driving circuit and improve the pixel density of the display panel.

[0006] According to one aspect of the present invention, there is provided a pixel driving circuit, comprising:

[0007] At least one pulse width modulation module, the pulse width modulation module comprising k1 first data input terminals, each of which is used to input one bit of grayscale data, the pulse width modulation module is used to output a pulse width modulation signal from its data output terminal according to the grayscale data; the data output terminal of the pulse width modulation module is used to connect to at least one light-emitting unit;

[0008] at least k1 data reading and writing modules, each of the first data input terminals of the pulse width modulation module is electrically connected to one of the data reading and writing modules, and k1 is the number of bits of the grayscale data;

[0009] The data reading and writing module includes a first data writing unit, a first storage unit, a first data writing unit and a second storage unit;

[0010] In the data reading and writing module corresponding to the first data input terminal, the first data writing unit is used to respond to an external selection signal to write one bit of the grayscale data into the corresponding first storage unit; the first data writing unit is used to respond to a frame refresh signal to write the data stored in the first storage unit into a first data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the first data input terminal of the pulse width modulation module.

[0011] Optionally, the pixel driving circuit includes:

[0012] n pulse width modulation modules, the pulse width modulation modules further comprising k2 second data input terminals, each of the second data input terminals being used to input one bit of the address data within the block, the pulse width modulation module being further used to output an internal strobe signal from its m internal strobe output terminals according to the address data within the block; n is greater than 1;

[0013] n*m pixel switches, each pulse width modulation module corresponds to m pixel switches; among the m pixel switches corresponding to each pulse width modulation module, the first end of each pixel switch is electrically connected to the data output end of the corresponding pulse width modulation module, the control ends of the m pixel switches are electrically connected to the m internal strobe output ends of the pulse width modulation module in a one-to-one correspondence, and the second end of the pixel switch is used to connect to one of the light-emitting units; m>n;

[0014] n*(k1+k2) data read / write modules, each of the second data input terminals is connected to a corresponding data read / write module, and k2 is the number of bits of address data in the block;

[0015] In the data reading and writing module corresponding to the second data input terminal, the first data writing unit is used to respond to an external selection signal to write one bit of the address data in the block into the corresponding first storage unit; the first data writing unit is used to respond to a frame refresh signal to write the data of the first storage unit into a second data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the second data input terminal of the pulse width modulation module.

[0016] Optionally, a first end of the first data writing unit is connected to one bit of the grayscale data or the address data in the block, a second end of the first data writing unit is electrically connected to a first end of the first data writing unit, and a control end of the first data writing unit is connected to the external selection signal;

[0017] The first end of the first storage unit is electrically connected to the second end of the first data writing unit, and the second end of the first storage unit is grounded;

[0018] The second end of the first data write unit is electrically connected to the first data input end or the second data input end of the corresponding pulse width modulation module, and the control end of the first data write unit is connected to the frame refresh signal; the first end of the second storage unit is electrically connected to the second end of the first data write unit, and the second end of the second storage unit is grounded.

[0019] Optionally, the first data writing unit includes a first transistor, a first electrode of the first transistor serves as a first end of the first data writing unit, a second electrode of the first transistor serves as a second end of the first data writing unit, and a control electrode of the first transistor serves as a control end of the first data writing unit;

[0020] The first storage unit includes a first capacitor, a first end of the first capacitor serves as a first end of the first storage unit, and a second end of the first capacitor serves as a second end of the first storage unit;

[0021] The first data writing unit includes a second transistor, a first electrode of the second transistor serves as a first end of the first data writing unit, a second electrode of the second transistor serves as a second end of the first data writing unit, and a control electrode of the second transistor serves as a control end of the first data writing unit;

[0022] The second storage unit includes a second capacitor, a first end of the second capacitor serves as a first end of the second storage unit, and a second end of the second capacitor serves as a second end of the second storage unit.

[0023] Optionally, the pixel driving circuit further includes:

[0024] A block address parsing module, wherein the input end of the block address parsing module is connected to a block address signal, and the block address parsing module is used to parse the block address signal; and to generate the external selection signal when the block address signal matches the address of the pixel driving circuit.

[0025] Optionally, the pixel driving circuit further includes:

[0026] An energy-saving control module, the energy-saving control module is connected to the external selection signal and the frame refresh signal; the energy-saving control module is configured to enter a first state in response to the external selection signal, and output a start signal when receiving the frame refresh signal in the first state; the energy-saving control module is also configured to enter a second state when the current frame does not receive the external selection signal corresponding to the next frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state;

[0027] The start control terminal of the pulse width modulation module is connected to the start signal or the shutdown signal, and the pulse width modulation module is configured to start in response to the start signal and shut down in response to the shutdown signal.

[0028] Optionally, the energy-saving control module includes an enabling unit and a startup control unit;

[0029] The enabling unit is connected to the external strobe signal and the frame refresh signal, and the enabling unit is configured to set the enabling signal to a first level in response to a pulse ending edge of the external strobe signal, and to set the enabling signal to a second level in response to a pulse ending edge of the frame refresh signal;

[0030] The startup control unit is connected to the enable signal and the frame refresh signal, and the startup control unit is configured to set the output signal to the first level to form the startup signal when the enable signal is at the first level and at a preset time within the pulse time of the frame refresh signal; and to set the output signal to the second level to form the shutdown signal when the enable signal is at the second level and at a preset time within the pulse time of the frame refresh signal.

[0031] Optionally, the pulse width modulation module includes: a counter, a comparator, an intra-block address decoding unit, a current generating unit and a light emitting control switch;

[0032] The counter is connected to the frame refresh signal and counts according to the frame refresh signal; the clock end of the counter is connected to a preset clock signal;

[0033] The comparator comprises k1 first input terminals, the first input terminal of the comparator serves as the first data input terminal of the pulse width modulation module; the second input terminal of the comparator is electrically connected to the output terminal of the counter; the output terminal of the comparator is electrically connected to the control terminal of the light emitting control switch;

[0034] The first end of the light emitting control switch is electrically connected to the current generating unit, and the second end of the light emitting control switch is electrically connected to the data output end of the pulse width modulation module;

[0035] The in-block address decoding unit includes k2 input terminals, the input terminal of the in-block address decoding unit serves as the second data input terminal of the pulse width modulation module, and the m output terminals of the in-block address decoding unit are electrically connected to the m internal selection output terminals of the pulse width modulation module in a one-to-one correspondence; the in-block address decoding unit is used to generate the internal selection signal according to the in-block address data.

[0036] Optionally, the current generating unit includes a first current source, a second current source and a current switching switch;

[0037] The output end of the first current source is electrically connected to the first end of the current switching switch, the second end of the current switching switch is electrically connected to the first end of the light emitting control switch, and the control end of the current switching switch is electrically connected to the third data input end of the pulse width modulation module;

[0038] The second current source is electrically connected to the first end of the light emitting control switch; the output current of the first current source is different from the output current of the second current source;

[0039] The pixel driving circuit includes n*(k1+k2+1) data reading and writing modules, and each of the third data input terminals is connected to a corresponding data reading and writing module; in the data reading and writing modules connected to the third data input terminal, the first data writing unit is used to respond to an external selection signal to write current selection data into the corresponding first storage unit; the first data writing unit is used to respond to a frame refresh signal to write the data of the first storage unit into the third data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the third data input terminal of the pulse width modulation module.

[0040] Optionally, the pixel driving circuit further includes a clock regeneration module;

[0041] The input end of the clock regeneration module is connected to q clock signals with a preset phase difference;

[0042] The clock regeneration module is used to encode according to the states of the q clock signals, and generate a quantitative decoding representing the number of types of the encoding according to the number of types of the encoding;

[0043] The least significant bit of the decoded quantity is used as the preset clock signal.

[0044] According to another aspect of the present invention, there is provided a display panel, the display panel comprising a plurality of pixel driving circuits as described above arranged in an array;

[0045] The display panel also includes a plurality of light-emitting units arranged in an array;

[0046] Each of the pixel driving circuits is correspondingly connected to m of the light-emitting units.

[0047] The technical solution of the embodiment of the present invention adopts a pixel driving circuit comprising: at least one pulse width modulation module, the pulse width modulation module comprises k1 first data input terminals, each first data input terminal is used to input one bit of grayscale data, the pulse width modulation module is used to output a pulse width modulation signal from its data output terminal according to the grayscale data; the data output terminal of the pulse width modulation module is used to connect at least one light-emitting unit; at least k1 data read-write modules, each first data input terminal of the pulse width modulation module is electrically connected to a data read-write module, k1 is the number of bits of grayscale data; the data read-write module comprises a first data write unit, a first storage unit, a first data write unit and a second storage unit; in the data read-write module corresponding to the first data input terminal, the first data write unit is used to respond to an external selection signal to write one bit of grayscale data into the corresponding first storage unit; the first data write unit is used to respond to a frame refresh signal to write the data stored in the first storage unit into a first data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the first data input terminal of the pulse width modulation module. The data read and write modules can be completed by two units. The pixel driving circuit only needs a small number of components to complete the reading and writing operations of one bit of data. The small number of components required can greatly reduce the number of components required for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and improving the pixel density of the display panel.

[0048] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of a circuit structure of another pixel driving circuit provided by an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a circuit structure of another pixel driving circuit provided by an embodiment of the present invention;

[0053] Figure 4A schematic diagram of a circuit structure of another pixel driving circuit provided by an embodiment of the present invention;

[0054] Figure 5 A timing diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0055] Figure 6 A schematic diagram of a circuit structure of another pixel driving circuit provided by an embodiment of the present invention;

[0056] Figure 7 A phase relationship diagram of a clock signal provided by an embodiment of the present invention;

[0057] Figure 8 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] Figure 1 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention, referring to Figure 1 , the pixel driving circuit includes:

[0061] At least one pulse width modulation module 11, the pulse width modulation module 11 includes k1 first data input terminals, each of which is used to input one bit of grayscale data; the pulse width modulation module 11 is used to output a pulse width modulation signal from its data output terminal a1 according to the grayscale data; the data output terminal a1 of the pulse width modulation module 11 is used to connect to at least one light emitting unit 13;

[0062] At least k1 data read / write modules 14, each first data input terminal of the pulse width modulation module 11 is electrically connected to a data read / write module 14, k1 is the number of bits of grayscale data;

[0063] The data reading and writing module 14 includes a first data writing unit 141, a first storage unit 142, a first data writing unit 143 and a second storage unit 144;

[0064] In the data reading and writing module 14 corresponding to the first data input terminal, the first data writing unit 141 is used to respond to the external selection signal Bsel to write one bit of grayscale data into the corresponding first storage unit 142; the first data writing unit 143 is used to respond to the frame refresh signal FSYN to write the data stored in the first storage unit 142 into a first data input terminal of the pulse width modulation module 11; the second storage unit 144 is used to maintain the potential of the first data input terminal of the pulse width modulation module 11.

[0065] Specifically, the light-emitting unit 13 may be a Micro LED. Of course, the light-emitting unit 13 may also be a light-emitting unit of other structures. The light-emitting unit 13 is a current-type device and needs to be driven by a pixel driving circuit to emit light. In the display panel, all the light-emitting units 13 may be arranged in an array. The display panel may include a plurality of pixel driving circuits arranged in an array, and each pixel driving circuit drives at least one light-emitting unit 13.

[0066] Each pixel driving circuit includes at least one pulse width modulation module 11, and each pulse width modulation module 11 can drive a light-emitting unit 13. Each pulse width modulation module 11 includes k1 first data input terminals. Each first data input terminal is connected to a data reading and writing module. Among them, k1 is the number of bits of grayscale data, and the grayscale data is also the data corresponding to the light emission of the light-emitting unit 13. When the grayscale data is different, the light-emitting grayscale of the light-emitting unit 13 is different. In this embodiment, the pixel driving circuit is a digital pixel driving circuit. When the grayscale data is different, the light-emitting time of the light-emitting unit 13 is different within a frame time. It can be understood that in some embodiments, in the same frame, the driving current corresponding to different light-emitting units driven can be the same. The number of bits of grayscale data can be determined by the number of grayscale levels corresponding to the light-emitting unit. The more the number of grayscale levels, the more bits of the corresponding grayscale data, that is, the larger k1. Exemplarily, k1 can be 12. The pulse width modulation module 11 can generate a corresponding pulse width modulation signal according to the grayscale data. The pulse width modulation signal is a signal with a certain current value and a certain pulse width. Different pulse width modulation signals have the same current value, and the pulse widths of the pulse width modulation signals corresponding to different grayscale data are different, thereby making the light-emitting unit 13 display different grayscales.

[0067] In one frame time, the k1 first data input terminals of the pulse width modulation module 11 receive k1 bits of grayscale data in parallel. Among them, the k1 bits of grayscale data are written in parallel to the k1 first data input terminals of the pulse width modulation module 11 by k1 data read and write modules. Since the grayscale data is input in parallel, each data read and write module 14 can only read and write one bit of data at a time. Therefore, each pulse width modulation module 11 requires at least k1 data read and write modules 14 to write data. Each data read and write module 14 needs to be connected to a data line, so each pixel driving circuit needs at least k1 data lines in total. Among them, if Figure 1 As shown, k1 data read / write modules 14 are connected to the block data input terminal BData, and the block data input terminal BData includes at least k1 sub-terminals, each of which is connected to a data line.

[0068] In the related art, the pixel driving circuit needs two latches to read and write one bit of data, and 2*k1 latches are needed to read and write k1 bits of data in parallel. However, the number of transistors required in each latch is relatively large, such as at least six transistors per latch, which means that the number of components required for the pixel driving circuit as a whole is relatively large, and the area occupied by the pixel driving circuit is relatively large.

[0069] In this embodiment, the data reading and writing of the data reading and writing module 14 can be completed by two units. Specifically, when the external selection signal Bsel is enabled, the data reading and writing module 14 is in the data reading state. When the data reading and writing module 14 reads data, the first data writing unit 141 is turned on, and the corresponding data (i.e., grayscale data) is stored in the first storage unit 142. When the frame refresh signal FSYN arrives, the data reading and writing module 14 writes data to the pulse width modulation module 11. At this time, the first data writing unit 143 is turned on, and the data on the first storage unit 142 is written to the corresponding data input terminal (first data input terminal) of the pulse width modulation module 11. And by setting the second storage unit 144, the potential of the first data input terminal of the corresponding pulse width modulation module 11 is maintained, so that the pulse width modulation module 11 can stably output the pulse width modulation signal. In summary, the pixel driving circuit of this embodiment only requires a small number of components to complete the reading and writing operations of one bit of data. The small number of components required can greatly reduce the number of components required for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and improving the pixel density of the display panel.

[0070] The technical solution of this embodiment adopts a pixel driving circuit including: at least one pulse width modulation module, the pulse width modulation module includes k1 first data input terminals, each first data input terminal is used to input one bit of grayscale data, and the pulse width modulation module is used to output a pulse width modulation signal from its data output terminal according to the grayscale data; the data output terminal of the pulse width modulation module is used to connect at least one light-emitting unit; at least k1 data read-write modules, each first data input terminal of the pulse width modulation module is electrically connected to a data read-write module, and k1 is the number of bits of grayscale data; the data read-write module includes a first data write unit, a first storage unit, a first data write unit, and a second storage unit; in the data read-write module corresponding to the first data input terminal, the first data write unit is used to respond to an external selection signal to write one bit of grayscale data into the corresponding first storage unit; the first data write unit is used to respond to a frame refresh signal to write the data stored in the first storage unit into a first data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the first data input terminal of the pulse width modulation module. The data read and write modules can be completed by two units. The pixel driving circuit only needs a small number of components to complete the reading and writing operations of one bit of data. The small number of components required can greatly reduce the number of components required for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and improving the pixel density of the display panel.

[0071] Optionally, Figure 2 A circuit structure diagram of another pixel driving circuit provided by an embodiment of the present invention, referring to Figure 2 The pixel driving circuit includes:

[0072] n pulse width modulation modules 11, the pulse width modulation module 11 further comprising k2 second data input terminals, each second data input terminal being used to input one bit of the address data within the block, and the pulse width modulation module 11 being further used to output an internal strobe signal from its m internal strobe output terminals a2 according to the address data within the block; n is greater than 1;

[0073] n*m pixel switches 12, each pulse width modulation module 11 corresponds to m pixel switches 12; in the m pixel switches 12 corresponding to each pulse width modulation module 11, the first end of each pixel switch 12 is electrically connected to the data output end a1 of the corresponding pulse width modulation module 11, the control ends of the m pixel switches 12 are electrically connected to the m internal selection output ends a2 of the pulse width modulation module 11 in a one-to-one correspondence, and the second end of the pixel switch 12 is used to connect a light-emitting unit 13; m>n;

[0074] n*(k1+k2) data read / write modules 14, each second data input terminal is connected to a corresponding data read / write module 14, different second data input terminals are connected to different data read / write modules 14, and the first data input terminal and the second data input terminal are also connected to different data read / write modules 14, that is, in this embodiment, each pulse width modulation module 11 corresponds to (k1+k2) data read / write modules 14, k1 is the number of bits of grayscale data, and k2 is the number of bits of address data in the block;

[0075] In the data reading and writing module 14 corresponding to the second data input terminal, the first data writing unit 141 is used to respond to the external selection signal Bsel to write one bit of the address data in the block into the corresponding first storage unit 142; the first data writing unit 143 is used to respond to the frame refresh signal FSYN to write the data of the first storage unit 142 into a second data input terminal of the pulse width modulation module 11; the second storage unit 144 is used to maintain the potential of the second data input terminal of the pulse width modulation module 11.

[0076] Specifically, in this embodiment, the pixel driving circuit is used to drive m light-emitting units 13. In the display panel, the m light-emitting units 13 can be arranged in an array. The display panel may include a plurality of pixel driving circuits arranged in an array, and from the overall perspective of the display panel, all the light-emitting units 13 can also be arranged in an array. Exemplarily, m can be 64, and the 64 light-emitting units corresponding to each pixel driving circuit can be arranged in an array of 8 rows and 8 columns. In this embodiment, the second ends of the m pixel switches 12 corresponding to each pulse width modulation module 11 are electrically connected to the m light-emitting units. That is, each light-emitting unit will be connected to n pixel switches, and the n pixel switches 12 belong to different pulse width modulation modules 11 respectively.

[0077] For each pixel driving circuit, the pixel driving circuit includes n pulse width modulation modules 11, and each pulse width modulation module 11 can drive a light-emitting unit 13 to emit light according to the address data in the block. That is to say, in one frame time, only a few of the m light-emitting units 13 corresponding to a pixel driving circuit can emit light, wherein the number of light-emitting units that emit light simultaneously in one frame is at most n. Thus, a pixel driving circuit can sparsely drive the m light-emitting units 13, and then the m light-emitting units 13 can realize sparse display. Exemplarily, the value of n is 8.

[0078] Each pulse width modulation module 11 includes k1 first data input terminals and k2 second data input terminals. Each first data input terminal is connected to a data read-write module, and each second data input terminal is connected to a data read-write module. Among them, k1 is the number of bits of grayscale data, and the grayscale data is also the data corresponding to the light emission of the light-emitting unit 13. When the grayscale data is different, the light-emitting grayscale of the light-emitting unit 13 is different. In this embodiment, the pixel driving circuit is a digital pixel driving circuit. If the grayscale data is different, the light-emitting time of the light-emitting unit 13 is different within a frame time. It can be understood that in some embodiments, in the same frame, the driving current corresponding to different light-emitting units driven can be the same. The number of bits of grayscale data can be determined by the number of grayscale levels corresponding to the light-emitting unit. The more the number of grayscale levels, the more bits of the corresponding grayscale data, that is, the larger k1. Exemplarily, k1 can be 12.

[0079] k2 is the number of bits of the address data within the block, and the address data within the block characterizes the positions of the m light-emitting units 13 corresponding to the pixel driving circuit. In one frame time, each pulse width modulation module 11 drives a light-emitting unit 13 to emit light. The specific address of the light-emitting unit 13 driven by it is determined by the address data within the block. Each address data within the block corresponds to a light-emitting unit 13, and different address data within the block correspond to different light-emitting units 13. The number of bits of the address data within the block is determined by the specific value of m. The larger the value of m, the larger the number of bits of the address data within the block, that is, the larger the value of k2. Exemplarily, when m is 64, the value of k2 can be 6.

[0080] In one frame time, the k1 first data input terminals of the pulse width modulation module 11 receive k1 bits of grayscale data in parallel. Among them, the k1 bits of grayscale data are written in parallel to the k1 first data input terminals of the pulse width modulation module 11 by k1 data read and write modules. The k2 second data input terminals of the pulse width modulation module 11 receive k2 bits of block address data in parallel. Among them, the k2 bits of block address data are written in parallel to the k2 second data input terminals of the pulse width modulation module 11 by k2 data read and write modules. Since both the grayscale data and the block address data are input in parallel, each data read and write module 14 can only read and write one bit of data at a time, and therefore, each pulse width modulation module 11 requires k1+k2 data read and write modules 14 to write data. Furthermore, n pulse width modulation modules 11 require n*(k1+k2) data read and write modules 14 to write data. When n=8, k1=12, and k2=6, n pulse width modulation modules 11 require a total of 144 data read / write modules 14. Each data read / write module 14 needs to be connected to a data line, so each pixel driving circuit requires a total of n*(k1+k2) data lines, that is, 144 data lines. Figure 1As shown, n*(k1+k2) data read / write modules 14 are connected to the block data input terminal BData, and the block data input terminal BData includes n*(k1+k2) sub-terminals, each of which is connected to a data line.

[0081] In the related art, the pixel driving circuit needs two latches to read and write one bit of data, and 2*n*(k1+k2) latches are needed to read and write n*(k1+k2) bits of data in parallel. The number of transistors required in each latch is relatively large, such as at least six transistors per latch, which means that the number of components required for the pixel driving circuit as a whole is relatively large, and the area occupied by the pixel driving circuit is relatively large.

[0082] In this embodiment, the data reading and writing of the data reading and writing module 14 can be completed by two units. Specifically, when the external selection signal Bsel is enabled, the data reading and writing module 14 is in the data reading state. When the data reading and writing module 14 reads data, the first data writing unit 141 is turned on, and the corresponding data (i.e., one bit of grayscale data or one bit of address data in the block) is stored in the first storage unit 142. When the frame refresh signal FSYN arrives, the data reading and writing module 14 writes data to the pulse width modulation module 11. At this time, the first data writing unit 143 is turned on, and the data on the first storage unit 142 is written to the corresponding data input terminal (first data input terminal or second data input terminal) of the pulse width modulation module 11. And by setting the second storage unit 144, the potential of the corresponding data input terminal of the pulse width modulation module 11 is maintained, so that the pulse width modulation module 11 can stably output the internal selection signal and the pulse width modulation signal. In summary, the pixel driving circuit of this embodiment only requires a small number of components to complete the reading and writing operations of one bit of data. The small number of components required can greatly reduce the number of components required for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and improving the pixel density of the display panel.

[0083] The technical solution of this embodiment adopts a pixel driving circuit comprising: n pulse width modulation modules, the pulse width modulation module further comprising k2 second data input terminals, each second data input terminal being used to input one bit of address data within the block, and the pulse width modulation module being further used to output an internal selection signal from its m internal selection output terminals according to the address data within the block; n being greater than 1; n*m pixel switches, each pulse width modulation module 11 corresponding to m pixel switches 12; in the m pixel switches corresponding to each pulse width modulation module 11, the first terminal of each pixel switch is electrically connected to the data output terminal of the corresponding pulse width modulation module, and the control terminals of the m pixel switches are electrically connected to the m internal selection output terminals of the pulse width modulation module. The strobe output terminals are electrically connected one by one, and the second terminal of the pixel switch is used to connect a light-emitting unit; m>n; n*(k1+k2) data read-write modules, each second data input terminal is connected to a data read-write module, k2 is the number of bits of the address data in the block; in the data read-write module corresponding to the second data input terminal, the first data write unit is used to respond to the external strobe signal to write one bit of the address data in the block into the corresponding first storage unit; the first data write unit is used to respond to the frame refresh signal to write the data of the first storage unit into a second data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the second data input terminal of the pulse width modulation module. The reading and writing of the data read-write module can be completed by two units. The pixel drive circuit only needs a small number of components to complete the read and write operation of one bit of data, and the number of components required is small, which can greatly reduce the number of components required for the pixel drive circuit, thereby reducing the area of ​​the pixel drive circuit and improving the pixel density of the display panel.

[0084] Optionally, continue to refer to Figure 1 and Figure 2 , the first end of the first data write unit 141 is connected to the grayscale data or one bit of the address data in the block, the second end of the first data write unit 141 is electrically connected to the first end of the first data write unit 143, and the control end of the first data write unit 141 is connected to the external selection signal Bsel; the first end of the first storage unit 142 is electrically connected to the second end of the first data write unit 141, and the second end of the first storage unit 142 is grounded; the second end of the first data write unit 143 is electrically connected to the first data input end or the second data input end of the corresponding pulse width modulation module 11, and the control end of the first data write unit 143 is connected to the frame refresh signal FSYN; the first end of the second storage unit 144 is electrically connected to the second end of the first data write unit 143, and the second end of the second storage unit 144 is grounded.

[0085] Specifically, in the data reading and writing module 14 corresponding to the input grayscale data, the first end of the first data writing unit 141 is connected to one bit of grayscale data, and different first data writing units 141 are connected to different bits of grayscale data. The second end of the corresponding first data writing unit 143 is electrically connected to a first data input terminal of the pulse width modulation module 11, and different first data writing units 143 are electrically connected to different first data input terminals.

[0086] In the data read-write module 14 corresponding to the input block address data, the first end of the first data write unit 141 is connected to one bit of the block address data, and different first data write units 141 are connected to different bits of the block address data. The second end of the corresponding first data write unit 143 is electrically connected to a second data input terminal of the pulse width modulation module 11, and different first data write units 143 are electrically connected to different first data input terminals.

[0087] For example, continue to refer to Figure 1 The first data writing unit 141 includes a first transistor T1, a first electrode of the first transistor T1 serves as a first end of the first data writing unit 141, a second electrode of the first transistor T1 serves as a second end of the first data writing unit 141, and a control electrode of the first transistor T1 serves as a control end of the first data writing unit 141.

[0088] The first storage unit 142 includes a first capacitor C1 , a first end of the first capacitor C1 serves as a first end of the first storage unit 142 , and a second end of the first capacitor C1 serves as a second end of the first storage unit 142 .

[0089] The first data write unit 143 includes a second transistor T2, a first electrode of the second transistor T2 serves as a first end of the first data write unit 143, a second electrode of the second transistor T2 serves as a second end of the first data write unit 143, and a control electrode of the second transistor T2 serves as a control end of the first data write unit 143.

[0090] The second storage unit 144 includes a second capacitor C2 , a first end of the second capacitor C2 serves as a first end of the second storage unit 144 , and a second end of the second capacitor C2 serves as a second end of the second storage unit 144 .

[0091] In this embodiment, the data reading and writing module 14 can complete the reading and writing operations of one bit of data through two transistors and two capacitors, and the number of components required is small, so the area occupied by the pixel driving circuit is also small. Of course, it can be understood that in some other embodiments, the first data writing unit 141 and the first data writing unit 143 can also adopt other types of switch structures. The first storage unit 142 and the second storage unit 144 can also adopt other types of charge storage elements.

[0092] Optionally, the capacitance value of the first capacitor C1 is greater than or equal to twice the capacitance value of the second capacitor C2, so as to ensure that the data of the first capacitor C1 is accurately written into the second capacitor C2.

[0093] Specifically, due to the capacitance characteristics, the second capacitor C2 will gradually discharge over time, causing the voltage value on the second capacitor C2 to gradually decrease. Therefore, the capacitance value of the second capacitor C2 needs to be designed so that it can maintain a certain amount of power within the time range of a frame image, thereby ensuring the accuracy of the grayscale data.

[0094] The basic formula for discharging a capacitor is:

[0095] V t =V 0 *e (-t / τ)

[0096] Among them, the discharge time constant τ is the key factor that determines the discharge speed of the capacitor, and its calculation formula is τ=R*C. t is the voltage across the capacitor at time t, V 0 is the initial voltage across the capacitor, R is the resistance of the capacitor, C is the capacitance, t is the time, and e is the base of the natural logarithm (approximately equal to 2.718).

[0097] When the discharge time t is approximately equal to 1 / 2 of the discharge time constant, V t The value reaches 60% of the original V0. Assuming that the voltage detected in the circuit drops to 60% or more of the original voltage, it can be considered that the data stored in the capacitor can still be detected, then the discharge time must satisfy t<=τ / 2, that is, the time constant of the C2 capacitor must satisfy the following relationship:

[0098] τ=Ri*C2>=2*t

[0099] In the sparse high refresh display application proposed by the present invention, it is assumed that the frame refresh rate of the system is 200KHz, that is, the time period of each frame is T = 5us. The capacitance of the second capacitor C2 needs to ensure that the voltage data stored can still be accurately identified within 5us, that is, the discharge time t is at least equal to one T. It can be deduced that the discharge time constant of C2 satisfies:

[0100] τ=Ri*12>=2*T=10us

[0101] Where Ri is the input impedance of the comparator.

[0102] Then the capacitance of the second capacitor C2 needs to satisfy:

[0103] C2>=10us / Ri

[0104] Under the Cmos process, the comparator impedance can generally reach the order of 100 G ohms. Assuming that the comparator impedance is 10 GΩ, the value of the second capacitor C2 can be obtained by substituting it into the above formula:

[0105] C2>=10us / 10GΩ=0.1*10 -14 F=1fF

[0106] According to the capacitance calculation formula of parallel plates:

[0107]

[0108] Among them, ε is the dielectric constant of the dielectric material, A is the area of ​​the parallel plate, and d is the thickness of the dielectric material. Generally speaking, in the Cmos process, SiO2 is used as the dielectric material, and its dielectric constant ε = 3.9*8.854*10-12, and assuming its thickness is 0.1um, it can be deduced that the area of ​​the C2 capacitor is:

[0109]

[0110] Substituting the constant values ​​of d and ε, we can get that the area of ​​C2 is 2.89um2.

[0111] In the sparse driving method proposed in this patent, a pixel driving circuit can drive 8 pixels simultaneously in an 8*8 pixel block unit. Assuming that the driving data of each pixel includes 12bit+6bit+1bit, a block pixel driving circuit needs to support (12+6+1)*8 bits of data storage and refresh. Then the total area of ​​the first capacitor C1 for data storage and the second capacitor C2 for grayscale refresh under each block is at least (considering C1>=2C2):

[0112] ^

[0113] A=2.89*152*3=1318um 2

[0114] In CMOS technology, stacked capacitor design is often used. This can be achieved by making metal and dielectric material layers on different process layers. These layers are stacked up through specific design and process steps to form a capacitor structure. The stacked capacitor design can increase the capacitance value per unit area. In other words, capacitors of the same capacitance value can occupy a smaller plane area.

[0115] Assuming that the block pixel driving circuit proposed in this patent adopts a double-layer capacitor design, that is, the total capacitor area required for an 8*8 pixel block occupies a plane area of ​​A / 2 of the total area, that is, 6590um^2. The size of this area will determine the maximum area of ​​a block pixel unit. Assuming that the utilization rate of the capacitor layer wiring can be achieved at 80%, that is, to realize an 8*8 block pixel circuit, the minimum required plane area is:

[0116] S=659 / 80%=823.75um^2

[0117] The minimum pixel pitch supported by this area is:

[0118]

[0119] According to the above estimates, the block pixel circuit proposed in this patent can support the pitch of Micro-LED display devices to be reduced to about 3.5um.

[0120] In addition, this solution of using a capacitor structure for data storage and refresh enables the data storage unit to be realized through the upper metal layer during chip wiring design without occupying the area of ​​the underlying MOS tube, providing the possibility of integrating more MOS tubes at the bottom layer and laying the foundation for higher PPI display applications.

[0121] Optionally, Figure 3 A circuit structure diagram of another pixel driving circuit provided by an embodiment of the present invention, referring to Figure 3 The pixel driving circuit further includes a block address parsing module 15, the input end of which is connected to the block address signal ADData, and the block address parsing module 15 is used to parse the block address signal ADData, and generate an external selection signal Bsel when the block address signal ADData matches the address of the pixel driving circuit.

[0122] Specifically, the display panel includes a plurality of pixel drive circuits arranged in an array, each pixel drive circuit corresponds to a block address, and different pixel drive circuits correspond to different block addresses. The pixel drive circuits in the same column share the same data line, and the display panel can select the corresponding pixel drive circuit to drive through the block address signal ADData. For example, if the pixel drive circuit in the first row needs to be selected for driving at a certain moment, the block address signal ADData matching the address of the pixel drive circuit in the first row can be written on the data line, and the pixel drive circuit in the first row receives the block address signal ADData and generates an external selection signal Bsel. The block address signal ADData received by the pixel drive circuits in other rows does not match their own addresses, so the pixel drive circuits in other rows are not selected. In other words, the grayscale data transmitted on the data line can only be received by the pixel drive circuit in the first row at this time, and the pixel drive circuit that does not need to be driven is not selected, and the pixel drive circuit does not work, which can reduce power consumption. In addition, a column of pixel drive circuits share a data line, and the mode of matching the block address can be understood as a mode of matching the bus mode with the block address, which can save data routing. Exemplarily, the block address parsing module 15 may include a decoder and a comparator. The decoder decodes the received block address signal ADData, and the comparator compares the decoding result with the address of the pixel driving circuit, and outputs an external selection signal if they match.

[0123] Optionally, continue to refer to Figure 3 The pixel driving circuit also includes an energy-saving control module 16, which is connected to an external selection signal Bsel and a frame refresh signal FSYN; the energy-saving control module 16 is configured to enter a first state in response to the external selection signal Bsel, and output a start signal when receiving the frame refresh signal FSYN in the first state; the energy-saving control module 16 is also used to enter a second state when the current frame does not receive an external selection signal of the next frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state; the start control end of the pulse width modulation module 11 is connected to a start signal or a shutdown signal, and the pulse width modulation module is configured to start in response to the start signal. The start control end of the pulse width modulation module shuts down in response to the shutdown signal.

[0124] Specifically, in this embodiment, the pixel driving circuit in the display panel may not be driven in every frame, that is, there may be a frame that does not require the corresponding light-emitting unit 13 to display. When the pixel driving circuit does not need to be driven in a certain frame, the energy-saving control module 16 can control the pulse width modulation module 11 not to start in the frame, and more specifically, it can control the comparator and / or counter in the pulse width modulation module 11 not to start, thereby reducing power consumption.

[0125] One frame of the pixel driving circuit starts with the frame refresh signal FSYN of the current frame and ends with the frame refresh signal FSYN of the next frame. When the frame refresh signal FSYN arrives, the data in the data read-write module 14 will be read into the pulse width modulation module 11. Before the frame refresh signal FSYN of the current frame arrives, the first storage unit 142 in the data read-write module 14 stores the data required to complete the current frame. In other words, the external selection signal of the current frame is received in the previous frame of the current frame, and the external selection signal received in the current frame indicates that data needs to be written to the next frame of the current frame, that is, the pulse width modulation module 11 needs to be started. Therefore, when the energy-saving control module 16 receives the external selection signal Bsel in the current frame, it means that the pulse width modulation module 11 needs to be started in the next frame of the current frame. When the energy-saving control module 16 receives the external selection signal Bsel, the energy-saving control module 16 can first enter the first state, and when the frame refresh signal FSYN is received, it indicates that the next frame is coming, and the pulse width modulation module 11 is started at this time, so as to avoid directly starting the pulse width modulation module when the external selection signal is received in the current frame, thereby increasing power consumption. In addition, when the current frame does not receive the external selection signal Bsel, it indicates that there is no data in the next frame, and the pulse width modulation module 11 does not need to be started. At this time, the energy-saving control module 16 is first entered into the second state, and when the frame refresh signal FSYN is received, it indicates that the next frame is coming, and the pulse width modulation module 11 is turned off at this time, thereby saving power consumption.

[0126] Optionally, Figure 4 A circuit structure diagram of another pixel driving circuit provided by an embodiment of the present invention is shown. Figure 5 A timing diagram of a pixel driving circuit provided by an embodiment of the present invention, referring to Figure 4 and Figure 5 The energy-saving control module 16 includes an enabling unit 161 and a starting control unit 162; the enabling unit 161 is connected to an external selection signal Bsel and a frame refresh signal FSYN, and the enabling unit 161 is configured to set the enabling signal ML to a first level in response to a pulse end edge of the external selection signal Bsel, and to set the enabling signal ML to a second level in response to a pulse end edge of the frame refresh signal; the starting control unit 162 is connected to the enabling signal ML and the frame refresh signal FSYN, and the starting control unit 162 is configured to set the output signal ACT to a first level to form a starting signal when the enabling signal ML is at a first level and at a preset time within the pulse time of the frame refresh signal FSYN; and to set the output signal ACT to a second level to form a shutdown signal when the enabling signal ML is at a second level and at a preset time within the pulse time of the frame refresh signal FSYN.

[0127] Specifically, in this embodiment, the output signal ACT of the start control unit 162 controls the pulse width modulation module 11 to start or shut down. The first level can be a high level, and the second level can be a low level, or vice versa. Figure 5 As shown, Figure 5 Three consecutive frames are schematically illustrated in the example. In the first frame, there is an external selection signal Bsel. Therefore, at the end edge (i.e., the falling edge) of the pulse of the external selection signal Bsel, the enable signal output by the enable unit 161 is set to the first level, and the energy-saving control module 16 enters the first state. After the frame refresh signal FSYN of the second frame arrives, the enable signal ML of the falling edge enable unit 161 is set to the second level, and the output signal ACT of the start control unit 162 is set to the first level at a certain moment in the middle of the frame refresh signal FSYN pulse (i.e., whether it is currently the first level or the second level, it is set to the first level). In this embodiment, the output signal ACT of the start control unit 162 jumps at a certain moment of the starting edge and the ending edge of the pulse of the frame refresh signal FSYN, so that the pulse width modulation module 11 can be started in advance, and when the ending edge of the frame refresh signal arrives, that is, after starting to write data, the pulse width modulation module 11 can enter a stable working state. As shown Figure 5 As shown, in the second frame, there is no external selection signal Bsel, so the enable signal ML always maintains the second level; when the frame refresh signal FSYN of the third frame arrives, the output signal ACT is set to the second level.

[0128] It should be noted that, in the above embodiment, the pulse width modulation module 11 needs to work under the control of the input clock Dclk, and the duration of the external selection signal Bsel includes at least one cycle of the input clock Dclk. The output signal ACT can jump at the middle moment of the frame refresh signal FSYN. In addition, the enabling unit 161 and the start control unit 162 can be implemented based on FPGA (Field Programmable Gate Array, field programmable gate array) and the like.

[0129] Optionally, Figure 6 A circuit structure diagram of another pixel driving circuit provided by an embodiment of the present invention, referring to Figure 6The pulse width modulation module 11 includes a counter 111, a comparator 112, an intra-block address decoding unit 113, a current generating unit 114 and a light-emitting control switch 115; the counter 111 is connected to the frame refresh signal FSYN; the clock end of the counter 111 is connected to the preset clock signal, that is, the input clock Dclk. The comparator 112 includes k1 first input ends, the first input end of the comparator 112 serves as the first data input end of the pulse width modulation module 11, and the second input end of the comparator 112 is electrically connected to the output end of the counter 111; the output end of the comparator 112 is electrically connected to the control end of the light-emitting control switch 115;

[0130] The first end of the light-emitting control switch 115 is electrically connected to the current generating unit 114, and the second end of the light-emitting control switch 115 is electrically connected to the data output terminal a1 of the pulse width modulation module 11; the intra-block address decoding unit 113 includes k2 input terminals, the input terminal of the intra-block address decoding unit 113 serves as the second data input terminal of the pulse width modulation module 11, and the m output terminals of the intra-block address decoding unit 113 are electrically connected one-to-one with the m internal selection output terminals of the pulse width modulation module 11; the intra-block address decoding unit 113 is used to generate an internal selection signal according to the intra-block address data.

[0131] Specifically, refer to Figure 5 and Figure 6 , when the pulse end edge of the frame refresh signal FSYN arrives, the counter 111 starts counting, and the count output Conter of the counter 111 gradually increases. The count output Conter is compared with the data (i.e., grayscale data) at the first input terminal of the comparator 112. At this time, the grayscale data is greater than the count output Conter, and the comparator 112 controls the light control switch 115 to turn on, that is, the output control signal PWM of the comparator 112 controls the light control switch 115 to turn on. The constant current generated by the current generating unit 114 is transmitted to the corresponding light-emitting unit 13, and the light-emitting unit 13 emits light. When the count output Conter is greater than the grayscale data, the output control signal PWM of the comparator 112 controls the light control switch 115 to turn off, and the light-emitting unit 13 is extinguished. It can be understood that the block address decoding unit 113 controls the corresponding pixel switch 12 to turn on according to the block address data, so that the light-emitting unit 13 corresponding to the pixel switch 12 is turned on with the light control switch 115, thereby achieving sparse display. It should be noted that when the energy-saving control module 16 outputs a shutdown signal, the comparator 112 does not perform comparison, and the counter 111 does not count.

[0132] Optionally, continue to refer to Figure 6, the current generating unit 114 includes a first current source I1, a second current source I2 and a current switching switch 1141; the output end of the first current source I1 is electrically connected to the first end of the current switching switch 1141, the second end of the current switching switch 1141 is electrically connected to the first end of the light emitting control switch 115, and the control end of the current switching switch 1141 is electrically connected to the third data input end of the pulse width modulation module 11;

[0133] The second current source I2 is electrically connected to the first end of the light emitting control switch 115, and the output current of the first current source I1 is different from the output current of the second current source I2;

[0134] The pixel driving circuit includes n*(k1+k2+1) data read and write modules 14, and each third data input terminal is connected to a corresponding data read and write module 14; in the data read and write module 14 connected to the third data input terminal, the first data write unit 141 is used to respond to the external selection signal Bsel to write the current selection data into the corresponding first storage unit 142; the first data write unit 143 is used to respond to the frame refresh signal FSYN to write the data of the first storage unit 142 into the third data input terminal of the pulse width modulation module 11; the second storage unit 144 is used to maintain the potential of the third data input terminal of the pulse width modulation module 11.

[0135] Specifically, in this embodiment, the current generating module 114 can generate two different driving currents, and can control whether the current switching switch 1141 is turned on or not according to the current selection data. That is to say, in this embodiment, different light-emitting units are driven by different pulse width modulation modules 11, and the current selection data corresponding to different pulse width modulation modules can be different. Therefore, the driving currents corresponding to different pulse width modulation modules can be different, and then the driving currents corresponding to different light-emitting units can be different. The current selection data also requires a data reading and writing module 14 to read and write. In this embodiment, each pixel driving circuit includes a total of n*(k1+k2+1) data reading and writing modules 14. When n is 8, k1 is 12, and k2 is 6, each pixel driving circuit includes a total of 152 data reading and writing modules 14, and a total of 152 data lines are required. The first current source I1 and the second current source I2 can both be current mirrors. The current generated by the first current source I1 can be 400μA, and the current generated by the second current source I2 can be 1μA. Thus, a larger dynamic brightness range can be achieved.

[0136] For example, in a display panel, a wiring method of sending data to multiple pixel driving circuits in a 100Mbps bus mode can save the wiring density outside the block (outside the pixel driving circuit). Assuming that a set of buses supports a unit column block (i.e., a column of pixel driving circuits), taking the parallel input of unit block data proposed in the embodiment as an example, the number of buses required for a unit column block is about 4+9+(12+6+1)*8=165 buses. According to the minimum wiring line width of 0.42um in the relevant 0.13um process, the width of the 165 buses is 165*0.42um=69.3um in total. Since each unit block includes 8 columns of pixels, considering that the bus is laid out using 3 layers of metal, the minimum column width of the pixel block supported by the bus width is: 69.3 / 8 / 3=2.8um, that is, when a set of buses is laid out with 1 unit column, it can support a pixel size of 2.8um, and its row resolution is 500*8=4000. If multiple sets of bus wiring methods arranged in columns are used, a display device with a small pitch and high resolution can be easily achieved. Among them, 4 in the formula 4+9+(12+6+1)*8 is a clock line, and the clock signal on the clock line is finally converted into an input clock Dclk; 9 is a column addressing line required by a column of pixel driving circuits. In this embodiment, each row of pixel driving circuits can correspond to 5 row addressing lines.

[0137] Optionally, continue to refer to Figure 6 The pixel driving circuit also includes a clock regeneration module 17; the input end of the clock regeneration module 17 is connected to q clock signals with a preset phase difference; the clock regeneration module 17 is used to encode according to the states of the q clock signals, and generate a quantity decoding representing the number of encoding types according to the number of encoding types; the clock regeneration module 17 is also used to use the lowest bit of the quantity decoding as a preset clock signal.

[0138] Specifically, the periods of q clock signals are the same, and their phase difference can be 1 / (2*q) phases, and the phases of any two clock signals are different. The clock regeneration module 17 obtains the state of q clock signals at a certain moment, and encodes the state, and then decodes the total number of different codes to obtain the quantity decoding. The rate of change of the lowest bit of the quantity decoding is 2*q times the period of the clock signal. This signal is used as the preset clock signal, which means that the conversion from a low-speed clock signal to a high-speed clock signal is realized. For example, Figure 7 As shown, Figure 7A phase relationship diagram of a clock signal provided by an embodiment of the present invention. Taking q as 4 as an example, a total of 4 clock signals are included, namely, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4, and the four clock signals differ by 1 / 8 phase. In the t1 stage, the encoding of the q clock signals received by the clock regeneration module 17 is 1111, the t2 stage is 1110, the t3 stage is 1100, the t4 stage is 1000, the t5 stage is 0000, the t6 stage is 0001, the t7 stage is 0011, and the t8 stage is 0111. The number of corresponding encoding types is 8, that is, the number decoding requires a total of three bits, assuming that the number decoding in the t1 stage is 000, the t2 stage is 001, the t3 stage is 010, the t4 stage is 011, the t5 stage is 100, the t6 stage is 101, the t7 stage is 110, and the t8 stage is 111. It can be seen that the least significant bit of the quantity decoding changes with a period of 1 / 8 of the clock signal.

[0139] Optionally, in the counter 111, the quantity decoding may be used as the last three digits of the counter, and the counter 111 may include a 9-bit register, so that the counter 111 constitutes a 12-bit counter.

[0140] Optionally, continue to refer to Figure 6 The pixel switch 12 includes a third transistor T3, a first electrode of the third transistor T3 serves as a first end of the pixel switch 12, a second electrode of the third transistor T3 serves as a second end of the pixel switch 12, and a control electrode of the third transistor T3 serves as a control end of the pixel switch 12.

[0141] The light emitting control switch 115 includes a fourth transistor T4 , a first electrode of the fourth transistor T4 serves as a first end of the light emitting control switch 115 , a second electrode of the fourth transistor T4 serves as a second end of the light emitting control switch 115 , and a control electrode of the fourth transistor T4 serves as a control end of the light emitting control switch 115 .

[0142] The current switching switch 1141 includes a fifth transistor T5, a first electrode of the fifth transistor T5 serves as a first end of the current switching switch 1141, a second electrode of the fifth transistor T5 serves as a second end of the current switching switch 1141, and a control electrode of the fifth transistor T5 serves as a control end of the current switching switch 1141.

[0143] The first transistor T1 to the fifth transistor T5 may be N-type transistors or P-type transistors.

[0144] The present invention also provides a display panel, such as Figure 8 As shown, Figure 8A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. The display panel includes a plurality of pixel driving circuits PX arranged in an array as provided by any embodiment of the present invention. Each pixel driving circuit PX is connected to m light-emitting units. Since the display panel provided by an embodiment of the present invention includes the pixel driving circuit provided by an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0145] The present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. The display device may be a mobile phone, a tablet computer, an MP3, an MP4, a smart watch, a smart helmet, a videophone, a personal digital assistant or other wearable device, etc. Since the display device provided by the embodiment of the present invention includes the display panel provided by the embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0146] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0147] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: At least one pulse width modulation module, the pulse width modulation module comprising k1 first data input terminals, each of which is used to input one bit of grayscale data, the pulse width modulation module is used to output a pulse width modulation signal from its data output terminal according to the grayscale data; the data output terminal of the pulse width modulation module is used to connect to at least one light-emitting unit; at least k1 data reading and writing modules, each of the first data input terminals of the pulse width modulation module is electrically connected to one of the data reading and writing modules, and k1 is the number of bits of the grayscale data; The data reading and writing module includes a first data writing unit, a first storage unit, a first data writing unit and a second storage unit; In the data reading and writing module corresponding to the first data input terminal, the first data writing unit is used to respond to an external selection signal to write one bit of the grayscale data into the corresponding first storage unit; the first data writing unit is used to respond to a frame refresh signal to write the data stored in the first storage unit into a first data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the first data input terminal of the pulse width modulation module.

2. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit comprises: n pulse width modulation modules, the pulse width modulation modules further comprising k2 second data input terminals, each of the second data input terminals being used to input one bit of the address data within the block, the pulse width modulation module being further used to output an internal strobe signal from its m internal strobe output terminals according to the address data within the block; n is greater than 1; n*m pixel switches, each pulse width modulation module corresponds to m pixel switches; among the m pixel switches corresponding to each pulse width modulation module, the first end of each pixel switch is electrically connected to the data output end of the corresponding pulse width modulation module, the control ends of the m pixel switches are electrically connected to the m internal selection output ends of the pulse width modulation module in a one-to-one correspondence, and the second end of the pixel switch is used to connect to one of the light-emitting units; m>n; n*(k1+k2) data read / write modules, each of the second data input terminals is connected to a corresponding data read / write module, and k2 is the number of bits of address data in the block; In the data reading and writing module corresponding to the second data input terminal, the first data writing unit is used to respond to an external selection signal to write one bit of the address data in the block into the corresponding first storage unit; the first data writing unit is used to respond to a frame refresh signal to write the data of the first storage unit into a second data input terminal of the pulse width modulation module; the second storage unit is used to maintain the potential of the second data input terminal of the pulse width modulation module.

3. The pixel driving circuit according to claim 2, characterized in that: A first end of the first data writing unit is connected to one bit of the grayscale data or the address data in the block, a second end of the first data writing unit is electrically connected to a first end of the first data writing unit, and a control end of the first data writing unit is connected to the external selection signal; The first end of the first storage unit is electrically connected to the second end of the first data writing unit, and the second end of the first storage unit is grounded; The second end of the first data write unit is electrically connected to the first data input end or the second data input end of the corresponding pulse width modulation module, and the control end of the first data write unit is connected to the frame refresh signal; the first end of the second storage unit is electrically connected to the second end of the first data write unit, and the second end of the second storage unit is grounded.

4. The pixel driving circuit according to claim 3, characterized in that: The first data writing unit comprises a first transistor, a first electrode of the first transistor serves as a first end of the first data writing unit, a second electrode of the first transistor serves as a second end of the first data writing unit, and a control electrode of the first transistor serves as a control end of the first data writing unit; The first storage unit includes a first capacitor, a first end of the first capacitor serves as a first end of the first storage unit, and a second end of the first capacitor serves as a second end of the first storage unit; The first data writing unit includes a second transistor, a first electrode of the second transistor serves as a first end of the first data writing unit, a second electrode of the second transistor serves as a second end of the first data writing unit, and a control electrode of the second transistor serves as a control end of the first data writing unit; The second storage unit includes a second capacitor, a first end of the second capacitor serves as a first end of the second storage unit, and a second end of the second capacitor serves as a second end of the second storage unit.

5. The pixel driving circuit according to claim 1 or 2, characterized in that: The pixel driving circuit further includes: A block address parsing module, wherein the input end of the block address parsing module is connected to a block address signal, and the block address parsing module is used to parse the block address signal; and to generate the external selection signal when the block address signal matches the address of the pixel driving circuit.

6. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit further includes: An energy-saving control module, the energy-saving control module is connected to the external selection signal and the frame refresh signal; the energy-saving control module is configured to enter a first state in response to the external selection signal, and output a start signal when receiving the frame refresh signal in the first state; the energy-saving control module is also configured to enter a second state when the current frame does not receive the external selection signal corresponding to the next frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state; The start control terminal of the pulse width modulation module is connected to the start signal or the shutdown signal, and the pulse width modulation module is configured to start in response to the start signal and shut down in response to the shutdown signal.

7. The pixel driving circuit according to claim 6, characterized in that: The energy-saving control module includes an enabling unit and a startup control unit; The enabling unit is connected to the external strobe signal and the frame refresh signal, and the enabling unit is configured to set the enabling signal to a first level in response to a pulse ending edge of the external strobe signal, and to set the enabling signal to a second level in response to a pulse ending edge of the frame refresh signal; The startup control unit is connected to the enable signal and the frame refresh signal, and the startup control unit is configured to set the output signal to the first level to form the startup signal when the enable signal is at the first level and at a preset time within the pulse time of the frame refresh signal; and to set the output signal to the second level to form the shutdown signal when the enable signal is at the second level and at a preset time within the pulse time of the frame refresh signal.

8. The pixel driving circuit according to claim 2, characterized in that: The pulse width modulation module includes: a counter, a comparator, an intra-block address decoding unit, a current generating unit and a light emitting control switch; The counter is connected to the frame refresh signal and counts according to the frame refresh signal; the clock end of the counter is connected to a preset clock signal; The comparator comprises k1 first input terminals, the first input terminal of the comparator serves as the first data input terminal of the pulse width modulation module; the second input terminal of the comparator is electrically connected to the output terminal of the counter; the output terminal of the comparator is electrically connected to the control terminal of the light emitting control switch; The first end of the light emitting control switch is electrically connected to the current generating unit, and the second end of the light emitting control switch is electrically connected to the data output end of the pulse width modulation module; The in-block address decoding unit includes k2 input terminals, the input terminal of the in-block address decoding unit serves as the second data input terminal of the pulse width modulation module, and the m output terminals of the in-block address decoding unit are electrically connected to the m internal selection output terminals of the pulse width modulation module in a one-to-one correspondence; the in-block address decoding unit is used to generate the internal selection signal according to the in-block address data.

9. The pixel driving circuit according to claim 8, characterized in that: The current generating unit includes a first current source, a second current source and a current switching switch; The output end of the first current source is electrically connected to the first end of the current switching switch, the second end of the current switching switch is electrically connected to the first end of the light emitting control switch, and the control end of the current switching switch is electrically connected to the third data input end of the pulse width modulation module; The second current source is electrically connected to the first end of the light emitting control switch; the output current of the first current source is different from the output current of the second current source; The pixel driving circuit comprises n*(k1+k2+1) data read / write modules, each of the third data input terminals is connected to a corresponding data read / write module; in the data read / write modules connected to the third data input terminals, the first data writing unit is used to respond to an external selection signal to write current selection data into the corresponding first storage unit; The first data writing unit is used to write the data of the first storage unit into the third data input terminal of the pulse width modulation module in response to a frame refresh signal; the second storage unit is used to maintain the potential of the third data input terminal of the pulse width modulation module.

10. The pixel driving circuit according to claim 8, characterized in that: The pixel driving circuit also includes a clock regeneration module; The input end of the clock regeneration module is connected to q clock signals with a preset phase difference; The clock regeneration module is used to encode according to the states of the q clock signals, and generate a quantitative decoding representing the number of types of the encoding according to the number of types of the encoding; The least significant bit of the decoded quantity is used as the preset clock signal.

11. A display panel, characterized in that: The display panel comprises a plurality of pixel driving circuits arranged in an array as claimed in any one of claims 1 to 10; The display panel also includes a plurality of light-emitting units arranged in an array; Each of the pixel driving circuits is correspondingly connected to m of the light-emitting units.

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