Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of sub display areas; the sub-display area comprises a plurality of sub-pixel units, and each sub-pixel unit comprises a pixel electrode and a driving transistor. The display panel further comprises a gate drive circuit for transmitting scanning signals to the sub-pixel units. And the driving transistor transmits the signal of the first node to the pixel electrode under the control of the scanning signal. In at least one frame of working time of the display panel, a plurality of scanning sub-segments which are executed in sequence are included, in at least one scanning sub-segment, a first node in a pixel row in one sub-display area receives a data voltage signal, and first nodes in pixel rows in other sub-display areas receive a common voltage signal. Through the arrangement, the previous frame image and the current frame image can be prevented from appearing in the same frame image, so that the crosstalk problem of the front frame image and the rear frame image of the display panel is solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, all walks of life have higher and higher requirements for the display effect of display products. In some display products, directional backlight technology (light diffraction / reflection / diffraction) is used to separate the left and right eye backlight paths, combined with the high refresh rate of the display screen to form a 3D display. However, the display image needs to be scanned separately for the left and right eyes, and is limited by the response time of the liquid crystal, so there is a crosstalk problem between the left and right eyes.

[0003] Therefore, how to solve the above problems has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to improve the display effect of the display panel.

[0005] In one aspect, the present disclosure provides a display panel, comprising:

[0006] A display area, the display area includes m sub-display areas, m≥2, and m is an integer; the sub-display area includes a plurality of pixel rows, the pixel rows include a plurality of sub-pixel units, and the sub-pixel units include pixel electrodes and driving transistors;

[0007] a first scanning line, wherein the control end of the driving transistor is electrically connected to the gate driving circuit through the first scanning line, the first end of the driving transistor is connected to the first node, and the second end of the driving transistor is connected to the pixel electrode; the gate driving circuit is configured to transmit a scanning signal to the sub-pixel unit, and the scanning signal turns the driving transistor on or off; and the driving transistor transmits the signal of the first node to the pixel electrode under the control of the scanning signal;

[0008] The first node receives at least a data voltage signal or a common voltage signal;

[0009] During at least one working frame of the display panel, m scanning sub-segments are sequentially executed, and within the scanning sub-segments, the pixel rows in each sub-display area sequentially receive scanning signals in time-sharing;

[0010] In at least one scanning sub-segment, a first node in a pixel row in one sub-display area receives a data voltage signal, and a first node in a pixel row in another sub-display area receives a common voltage signal.

[0011] On the other hand, based on the same inventive concept, the present disclosure also provides a display device, including a display panel.

[0012] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0013] The present disclosure provides a display panel and a display device, wherein the display panel includes a display area, the display area includes a plurality of sub-display areas; the sub-display area includes a plurality of pixel rows, the pixel rows include a plurality of sub-pixel units, and the sub-pixel units include pixel electrodes and driving transistors. The display panel also includes a first scan line, the control end of the driving transistor is electrically connected to the gate driving circuit through the first scan line, the first end of the driving transistor is connected to the first node, and the second end of the driving transistor is connected to the pixel electrode; the gate driving circuit is configured to transmit a scan signal to the sub-pixel unit, the scan signal turns the driving transistor on or off; the driving transistor transmits the signal of the first node to the pixel electrode under the control of the scan signal. During at least one frame of working time of the display panel, it includes a plurality of scan sub-segments executed in sequence, and in at least one scan sub-segment, the first node in the pixel row in one sub-display area receives a data voltage signal, and the first node in the pixel row in other sub-display areas receives a common voltage signal. With such a configuration, when the display panel scans and refreshes the image frame by frame, the first node in the sub-display area corresponding to the refresh area receives the data voltage signal to achieve image refresh; the first node in the sub-display area corresponding to the unrefreshed area receives the common voltage signal, and the corresponding area is set to black, preventing the previous frame image and the current frame image from appearing in the same frame, thereby improving the crosstalk problem between the previous and next frame images of the display panel, which is beneficial to improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] Figure 1 The figure is a schematic diagram of the cause of crosstalk formation of a display panel in the prior art;

[0017] Figure 2 Shown is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 3 Shown is an equivalent circuit diagram of a sub-pixel unit provided by an embodiment of the present disclosure;

[0019] Figure 4 Shown is a timing diagram of a display panel in the prior art;

[0020] Figure 5 Shown is a timing diagram of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 6 Shown is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0022] Figure 7 Shown is a schematic diagram of another sub-pixel unit provided by an embodiment of the present disclosure;

[0023] Figure 8 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0024] Fig. 9 FIG. 1 is a schematic diagram of another sub-pixel unit provided by an embodiment of the present disclosure;

[0025] Fig.10 Shown is a schematic diagram of a display area provided by an embodiment of the present disclosure;

[0026] Fig.11 Shown Fig.10 The corresponding timing diagram;

[0027] Fig.12 Shown Fig.10 The corresponding display effect diagram;

[0028] Fig.13 FIG. 1 is a timing diagram of another display panel provided by an embodiment of the present disclosure;

[0029] Fig.14 Shown Fig.13 A schematic diagram of the display effect of the display panel driven by the timing sequence shown;

[0030] Fig.15 FIG. 1 is a timing diagram of another display panel provided by an embodiment of the present disclosure;

[0031] Fig.16 Shown Fig.15 A schematic diagram of the display effect of the display panel driven by the timing sequence shown;

[0032] Fig.17 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0035] The inventors found in their research that in some display products (such as three-dimensional head-up displays, also known as 3D HUDs), directional backlight technology (light diffraction / reflection / diffraction) is used to separate the left and right eye backlight paths, and combined with the high refresh rate of the display screen to form a 3D display. However, the display image needs to be scanned separately for the left and right eyes, and is limited by the response time of the liquid crystal, so there is a crosstalk problem between the left and right eyes. Figure 1 The figure shows a schematic diagram of the cause of crosstalk in a display panel in the prior art. Please refer to Figure 1 The display panel is divided into left and right eye frames for scanning, and the left eye image data signal and the right eye image data signal are transmitted frame by frame, that is, the current frame transmits the left eye image data signal, and the next frame transmits the right eye image data signal, or the current frame transmits the right eye image data signal, and the next frame transmits the left eye image data signal. For example, Figure 1 In the example, the left eye frame needs to display image "A", and the right eye frame needs to display image "B". During one frame of working time of the display panel, the display panel scans line by line, and the image data signal drives the liquid crystal deflection to realize pixel light emission. In the figure, TBL-L is the directional backlight on period for the left eye, and TBL-R is the directional backlight on period for the right eye. The human eye can observe the corresponding image during the backlight start period. Since the liquid crystal response requires a certain amount of time, the time period shown as t0 in the figure is the liquid crystal response time, resulting in the image data signal of the previous frame being strung into the current image when the current frame transmits the image data signal, causing the image crosstalk problem between the left and right eyes. In the figure, 01' represents the tail part of the previous frame image, which is strung into the current frame image to form crosstalk. In the figure, 02' represents independent imaging of the current frame. Due to the existence of the crosstalk problem, the display effect of the display panel is affected.

[0036] Therefore, how to solve the above problems has become one of the technical problems that need to be solved urgently at this stage.

[0037] In view of this, the present disclosure provides a display panel and a display device to improve the display effect of the display panel.

[0038] Figure 2 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 FIG. 1 is an equivalent circuit diagram of a sub-pixel unit provided in an embodiment of the present disclosure. Please refer to FIG. Figure 2 and Figure 3The present disclosure provides a display panel 100, including: a display area 10, the display area 10 includes m sub-display areas 11, m≥2, and m is an integer; the sub-display area 11 includes a plurality of pixel rows 110, the pixel row 110 includes a plurality of sub-pixel units 111, the sub-pixel unit 111 includes a pixel electrode and a driving transistor T0; a first scan line 20, the control end of the driving transistor T0 is electrically connected to a gate driving circuit 30 through the first scan line 20, the first end of the driving transistor T0 is connected to a first node N1, and the second end of the driving transistor T0 is connected to a pixel electrode (not shown in the figure); the gate driving circuit 30 is configured to transmit a scan signal Gn to the sub-pixel unit 111, the scan signal Gn turns on or off the driving transistor T0; the driving transistor T0 transmits a signal of a first node N1 to the pixel electrode under the control of the scan signal Gn; the first node N1 at least receives a data voltage signal Dn or a common voltage signal VCOM.

[0039] During at least one frame of working time of the display panel 100, it includes m scanning sub-segments executed sequentially. In the scanning sub-segment, the pixel rows 110 in each sub-display area 11 receive the scanning signal Gn in time-sharing order; in at least one scanning sub-segment, the first node N1 in the pixel row 110 in one sub-display area 11 receives the data voltage signal Dn, and the first node N1 in the pixel row 110 in other sub-display areas 11 receives the common voltage signal VCOM.

[0040] It should be noted that the display panel 100 further includes a common electrode. The specific structures of the pixel electrode and the common electrode are not shown in the drawings of the present disclosure. Figure 3 The pixel electrode is connected to the second end of the driving transistor T0. When the driving transistor T0 is turned on, the voltage received by the first node N1 is transmitted to the pixel electrode. The common electrode can receive the common voltage signal VCOM. The voltage difference generated between the pixel electrode and the common electrode can drive the liquid crystal to deflect, thereby realizing the pixel light emission; the magnitude of the voltage difference between the pixel electrode and the common electrode affects the deflection angle of the liquid crystal, thereby affecting the pixel light emission. Figure 3 In the figure, the first plate where the capacitor Clc is connected to the second end of the driving transistor T0 represents the pixel electrode, and the second plate where the capacitor Clc is connected to the common voltage signal VCOM represents the common electrode.

[0041] Specifically, the display panel 100 includes a display area 10, and the display area 10 is used to display an image. The display area 10 includes m sub-display areas 11, and the sub-display area 11 includes a plurality of pixel rows 110 arranged along a first direction F1, and the pixel row 110 includes a plurality of sub-pixel units 111. Each sub-pixel unit 111 includes a pixel electrode and a driving transistor T0, and the control end of the driving transistor T0 is electrically connected to the first scanning line 20 corresponding to the row where it is located, and the first scanning line 20 is electrically connected to the gate driving circuit 30, and the gate driving circuit 30 generates a corresponding scanning signal Gn for each row of sub-pixel units 111, so as to scan the sub-pixel units 111 in the sub-display area 11 row by row. Under the control of the scanning signal Gn generated by the gate driving circuit 30, the driving transistor T0 transmits the signal of the first node N1 to the pixel electrode. The scanning signal Gn includes a first level and a second level, wherein the first level corresponds to the on-voltage of the driving transistor T0, and is used to turn on the driving transistor T0 of the sub-pixel unit 111 in the pixel row 110 when scanning a pixel row 110; and the second level corresponds to the off-voltage of the driving transistor T0, and is used to turn off the driving transistor T0 of the sub-pixel unit 111 in the row when the scanning ends. It should be noted that the embodiment of the present disclosure is described by taking the driving transistor T0 as an N-type transistor as an example, the first level corresponds to a high level, and the second level corresponds to a low level, and the present disclosure is described only by taking this as an example, and is not limited thereto.

[0042] It should also be noted that during different working hours of the display panel 100, the pixel electrode receives different signals, so that different voltage differences are formed between the pixel electrode and the common electrode, thereby affecting the deflection angle of the liquid crystal and realizing the display of different pictures. The pixel electrode is connected to the driving transistor T0, which is used to receive the signal transmitted by the first node N1 in a timely manner. The first node N1 receives the data voltage signal Dn or the common voltage signal VCOM. Under the condition that the driving transistor T0 is turned on, when the first node N1 receives the data voltage signal Dn, the pixel electrode can receive the data voltage signal Dn, and a voltage difference is formed between the pixel electrode and the common electrode, thereby driving the liquid crystal to deflect and realizing the pixel to emit light. When the first node N1 receives the common voltage signal VCOM, the pixel electrode can receive the common voltage signal VCOM, and the voltage difference between the pixel electrode and the common electrode is zero or close to zero, which is not enough to drive the liquid crystal to deflect, and the corresponding pixel cannot emit light, and the corresponding area is set to black.

[0043] In the prior art, the pixel rows 110 in the display area 10 receive the scanning signal Gn in time-sharing order. Since the liquid crystal response requires a certain amount of time, the pixel row 110 at the tail of the display area 10 maintains the scanning signal received in the previous frame, resulting in the tail of the previous frame image being strung into the current frame image, affecting the display effect. In the present disclosure, the display panel 100 includes m sub-display areas 11, and includes m scanning sub-segments executed in sequence during at least one frame of working time of the display panel 100. In each scanning sub-segment, the pixel rows 110 in each sub-display area 11 receive the scanning signal Gn in time-sharing order to achieve line-by-line scanning. During one frame of working time of the display panel 100, each pixel row 110 receives the scanning signal Gn m times. In at least one scanning sub-segment, only the first node N1 corresponding to the sub-pixel unit 111 in the pixel row 110 in one sub-display area 11 receives the data voltage signal Dn, and the first node N1 corresponding to the sub-pixel unit 111 in the pixel rows 110 in other sub-display areas 11 receives the common voltage signal VCOM. In other words, in at least one scanning sub-segment, only the first node N1 in one sub-display area 11 receives the data voltage signal Dn, the pixel electrode receives the data voltage signal Dn, and a voltage difference is formed between the pixel electrode and the common electrode, thereby driving the liquid crystal to deflect and realizing the pixel to emit light; the first node N1 in other sub-display areas 11 receives the common voltage signal VCOM, the pixel electrode receives the common voltage signal VCOM, and the voltage difference between the pixel electrode and the common electrode is zero or close to zero, which is insufficient to drive the liquid crystal to deflect, and the corresponding pixel cannot emit light, and the corresponding area is set to black. In this way, when the display panel 100 scans and refreshes the image frame by frame, the first node N1 in the sub-display area 11 corresponding to the refresh area receives the data voltage signal Dn to realize image refresh; the first node N1 in the sub-display area 11 corresponding to the unrefreshed area receives the common voltage signal VCOM, and the corresponding area is set to black, so as to avoid the previous frame image and the current frame image appearing in the same frame, thereby improving the crosstalk problem of the previous and next frame images of the display panel 100, which is conducive to improving the display effect of the display panel 100.

[0044] Please continue to refer to Figure 2 and Figure 3 In an optional embodiment of the present disclosure, the gate driving circuit 30 includes a multi-stage shift register unit 301 and an enable signal line 80, the shift register unit 301 is electrically connected to the first scan line 20, the first-stage shift register unit 301 corresponding to the sub-display area 11 is connected to the enable signal line 80, and the enable signal line 80 receives an enable signal; the enable signal is used to enable the first-stage shift register unit 301 corresponding to the sub-display area 11 to start transmitting the scan signal Gn; within at least one frame of working time of the display panel 100, the enable signal includes m valid pulse signals; different sub-display areas 11 start scanning at the same time.

[0045] It should be noted that the embodiment of the present disclosure is described by taking the example that the first-level shift register units 301 corresponding to different sub-display areas 11 are connected to the same start signal line 80, but it is not limited to this. The first-level shift register units 301 corresponding to different sub-display areas 11 can also be connected to different start signal lines 80 to meet the requirement of starting scanning of different sub-display areas 11 at the same time.

[0046] Specifically, the gate drive circuit 30 includes a plurality of shift register units 301, the shift register units 301 corresponding to the same sub-display area 11 are cascaded, and the shift register units 301 corresponding to different sub-display areas 11 are not connected. The gate drive circuit 30 also includes an opening signal line 80, the opening signal line 80 receives an opening signal, and is used to drive the first-stage shift register unit 301 to start transmitting the scanning signal Gn, so that the shift register unit 301 cascaded with the first-stage shift register unit 301 starts to transmit the scanning signal Gn to the corresponding first scanning line 20 step by step, thereby realizing the row-by-row scanning of the sub-pixel unit 111. In this embodiment, the shift register units 301 corresponding to the same sub-display area 11 are cascaded, and the first-stage shift register unit 301 corresponding to each sub-display area 11 is connected to the start signal line 80, and the start signal line 80 is connected to the start signal, and the m sub-display areas 11 correspond to the m first-stage shift register units 301. During at least one frame of working time of the display panel 100, the start signal STV includes m valid pulse signals, so that the first-stage shift register unit 301 corresponding to each sub-display area 11 starts to transmit the scanning signal Gn, and the sub-display area 11 starts to scan line by line. In this embodiment, different sub-display areas 11 are also configured to be driven by the same start signal STV, and different sub-display areas 11 start scanning at the same time. In this way, during at least one frame of working time of the display panel 100, each of the m sub-display areas 11 is scanned m times under the control of the start signal STV, and the driving transistor T0 is turned on during each scan, and the corresponding signal can be transmitted to the first node N1 according to demand.

[0047] Figure 4 FIG. 1 is a timing diagram of a display panel in the prior art. Figure 5 FIG. 1 is a timing diagram of a display panel provided by an embodiment of the present disclosure, please refer to Figure 2 to Figure 5 , the present disclosure takes the display area 10 including four sub-display areas 11 as an example to illustrate the scanning timing of the display panel 100, please refer to Figure 4In the prior art, during one frame of operation of the display panel, the start signal STV includes only one valid pulse signal, which is provided to the first-stage shift register unit 301, and other shift register units 301 are cascaded with the first-stage shift register unit 301, so as to realize the progressive scanning of the display panel 100. It should be noted that the effective pulse signal described in the present disclosure represents a signal that can drive the first-stage shift register unit to start transmitting the scanning signal. For example, the effective pulse signal of the start signal STV in the accompanying drawings is a high-level signal, and the present disclosure is only described by taking this as an example, and is not limited thereto.

[0048] Please refer to Figure 2 , Figure 3 and Figure 5 In the display panel 100 provided in the present embodiment, the display area 10 includes 4 sub-display areas 11 (the number of the sub-display areas 11 is for illustration only and is not limited thereto), and the multiple shift register units 301 corresponding to each sub-display area 11 are cascaded, and the shift register units 301 corresponding to different sub-display areas 11 are not connected. Then, the display panel 100 includes 4 first-stage shift register units 301, and the 4 first-stage shift register units 301 are all connected to the start signal line 80, and the start signal line 80 receives the start signal STV, and the start signal STV includes 4 valid pulse signals. Each shift register unit 301 receives 4 scan signals Gn, and when the scan signal Gn turns on the driving transistor T0, a signal is transmitted to the first node N1 according to demand.

[0049] It should be noted that the attached Figure 4 and Figure 5 In the illustrated embodiment, the display panel includes four sub-display areas, and the timing of the prior art and the timing of the embodiment of the present disclosure are compared, wherein n represents the number of pixel rows in the display panel, m represents the number of partitions, G represents the scanning signal, and G1, G(n / m+1), G(n / 2m) and G(n / m(m-1)+1) are the timings corresponding to the first-level shift register units in the four sub-display areas respectively.

[0050] In the embodiment provided by the present disclosure, the display area 10 is divided into m sub-display areas 11. In each scanning sub-segment, each sub-display area 11 performs row-by-row scanning. For the sub-display area 11 that needs to refresh the image, the data voltage signal Dn is transmitted to the first node N1 to update the image of the corresponding sub-display area 11. For the sub-display area 11 that does not need to refresh the image, the common voltage signal VCOM is transmitted to the first node N1 to blacken the image of the corresponding sub-display area 11. In this way, the previous frame image and the current frame image are prevented from appearing in the same frame, thereby improving the crosstalk problem of the previous and next frame images of the display panel 100, which is beneficial to improving the display effect of the display panel 100.

[0051] Please refer to Figure 2 and Figure 3 In an optional embodiment of the present disclosure, the sub-pixel unit 111 also includes a first control transistor T1 and a second control transistor T2; the control end of the first control transistor T1 is electrically connected to the first scan control signal end spic, the first end receives the data voltage signal Dn, and the second end is electrically connected to the first node N1; the control end of the second control transistor T2 is electrically connected to the second scan control signal end sv, the first end receives the common voltage signal VCOM, and the second end is electrically connected to the first node N1.

[0052] Specifically, in order to facilitate the transmission of the required signal to the first node N1, the sub-pixel unit 111 also includes a first control transistor T1 and a second control transistor T2. The control end of the first control transistor T1 is electrically connected to the first scan control signal end spic, and the first control transistor T1 is turned on or off under the control of the first scan control signal end spic. The first control transistor T1 is used to control whether the data voltage signal Dn is transmitted to the first node N1. The control end of the second control transistor T2 is electrically connected to the second scan control signal end sv, and the second control transistor T2 is turned on or off under the control of the second scan control signal end sv. The second control transistor T2 is used to control whether the common voltage signal VCOM is transmitted to the first node N1. When the first control transistor T1 is turned on, the data voltage signal Dn is transmitted to the first node N1, and when the driving transistor T0 is turned on, the data voltage signal Dn is transmitted to the pixel electrode, forming a voltage difference between the pixel electrode and the common electrode, thereby deflecting the liquid crystal and realizing pixel light emission. When the second control transistor T2 is turned on, the common voltage signal VCOM is transmitted to the first node N1, and when the driving transistor T0 is turned on, the data voltage signal Dn is transmitted to the pixel electrode. The voltage difference between the pixel electrode and the common electrode is zero or close to zero, which is insufficient to drive the liquid crystal to deflect. The corresponding pixel cannot emit light, and the corresponding area is black. In this embodiment, the first control transistor T1 and the second control transistor T2 are set to control the transmission of the data voltage signal Dn or the common voltage signal VCOM to the first node N1, so as to control the corresponding sub-pixel unit 111 to refresh the image or blacken the image.

[0053] It should be noted that the first control transistor T1 and the second control transistor T2 are both connected to the first node N1, and transmit the data voltage signal Dn or the common voltage signal VCOM to the first node N1. At the same time, only one of the first control transistor T1 and the second control transistor T2 connected to the same first node N1 is turned on. When the first control transistor T1 and the second control transistor T2 are turned off at the same time, the pixel light emitting state can be maintained unchanged. For example, after the sub-display area 11 scans and refreshes the image, the first control transistor T1 and the second control transistor T2 are turned off at the same time, and the sub-display area 11 can keep displaying the refreshed image.

[0054] Figure 6 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Figure 7 FIG. 1 is a schematic diagram of another sub-pixel unit provided in an embodiment of the present disclosure. Please refer to FIG. Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the display panel 100 also includes: a first driving chip 40 and a first data line 50; the first end of the first control transistor T1 is electrically connected to the first driving chip 40 through the first data line 50, and the first driving chip 40 is configured to provide a data voltage signal Dn to the sub-pixel unit 111; the first end of the first control transistor T1 in the same pixel column is connected to the same first data line 50.

[0055] Specifically, the display panel 100 further includes a first driving chip 40 and a plurality of first data lines 50, the plurality of first data lines 50 are connected to the first driving chip 40, the first driving chip 40 is used to provide a data voltage signal Dn to the sub-pixel unit 111, and the same first data line 50 is connected to the first end of the first control transistor T1 in the same pixel column. When the first control transistor T1 is turned on, the data voltage signal Dn provided by the first driving chip 40 is transmitted to the first node N1 of the corresponding sub-pixel unit 111 through the first data line 50, and when the driving transistor T0 corresponding to the sub-pixel unit 111 is turned on, the data voltage signal Dn is transmitted to the pixel electrode, thereby driving the liquid crystal deflection to realize the pixel light emission. The present disclosure sets the first end of the first control transistor T1 in the same pixel column to be connected to the same first data line 50, and the first driving chip 40 provides the corresponding data voltage signal Dn to the first data line 50, which is conducive to reducing the number of wirings in the display panel 100, simplifying the wiring structure of the display panel 100, simplifying the manufacturing process, and saving production costs.

[0056] Figure 8 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Fig. 9 FIG. 1 is a schematic diagram of another sub-pixel unit provided in an embodiment of the present disclosure, please refer to FIG. Figure 8 and Fig. 9 In an optional embodiment of the present disclosure, the display panel 100 also includes: a second driving chip 60 and a common electrode line 70; the first end of the second control transistor T2 is electrically connected to the second driving chip 60 through the common electrode line 70, and the second driving chip 60 is configured to provide a common voltage signal VCOM to the sub-pixel unit 111; the first end of the second control transistor T2 in the same pixel column is connected to the same common electrode line 70.

[0057] Please refer to the attached Figure 8In the perspective shown, the present disclosure shows that the first driving chip 40 is shown below the display area 10, and the second driving chip 60 is shown above the display area 10, but the present disclosure is not limited to this and can be designed according to actual conditions. The drawings of the present disclosure are for clear illustration of the first data line 50 and the common electrode line 70, and the first data line 50 and the common electrode line 70 are shown on both sides of the sub-pixel unit 111, but the present disclosure is not limited to this and can be designed according to actual conditions.

[0058] Specifically, the display panel 100 includes a first driving chip 40 and a first data line 50, the first data line 50 is connected to the first driving chip 40, the first driving chip 40 is used to provide a data voltage signal Dn to the sub-pixel unit 111, and the same first data line 50 is connected to the first end of the first control transistor T1 in the same pixel column. The first end of the first control transistor T1 is connected to the first data line 50, and the first driving chip 40 provides the data voltage signal Dn to the first data line 50. The display panel 100 also includes a second driving chip 60 and a plurality of common electrode lines 70, the plurality of common electrode lines 70 are connected to the second driving chip 60, the second driving chip 60 is used to provide a common voltage signal VCOM to the sub-pixel unit 111, and the same common electrode line 70 is connected to the first end of the second control transistor T2 in the same pixel column. When the second control transistor T2 is turned on, the common voltage signal VCOM provided by the second driving chip 60 is transmitted to the first node N1 of the corresponding sub-pixel unit 111 through the common electrode line 70. When the driving transistor T0 corresponding to the sub-pixel unit 111 is turned on, the common voltage signal VCOM is transmitted to the pixel electrode. The voltage difference between the pixel electrode and the common electrode is zero or close to zero, which is insufficient to drive the liquid crystal to deflect and make the image in the corresponding area black. The present disclosure sets the first end of the second control transistor T2 in the same column to be connected to the same common electrode line 70, and the second driving chip 60 provides the corresponding common voltage signal VCOM to the common electrode line 70, which is conducive to reducing the number of wirings in the display panel 100, simplifying the wiring structure of the display panel 100, simplifying the manufacturing process, and saving production costs.

[0059] It should be noted that the first end of the first control transistor T1 receives the data voltage signal Dn, and the first end of the second control transistor T2 receives the common voltage signal VCOM. The data voltage signal Dn and the common voltage signal VCOM can be provided by the same driver chip or by different driver chips, which is not specifically limited in the present disclosure. When the data voltage signal Dn and the common voltage signal VCOM are provided by different driver chips, it is beneficial to achieve the effect of providing a frame rate without affecting the charging rate of the sub-pixel unit 111, thereby improving the smoothness of the display panel 100 and improving the display effect of the display panel 100.

[0060] Please refer to Figure 2and Figure 3 In an optional embodiment of the present disclosure, the control end of the first control transistor T1 in the same sub-display area 11 is connected to the same first scan control signal end spic; the control end of the second control transistor T2 in the same sub-display area 11 is connected to the same second scan control signal end Sv.

[0061] Specifically, the display panel 100 provided by the present disclosure includes m sub-display areas 11 in the display area 10. In at least one frame of working time of the display panel 100, m scanning sub-segments are included. In at least one scanning sub-segment, the first node N1 in the same sub-display area 11 receives the data voltage signal Dn or the common voltage signal VCOM, that is, the first control transistor T1 in the same sub-display area 11 is turned on or the second control transistor T2 is turned on. In this embodiment, the control end of the first control transistor T1 in the same sub-display area 11 is connected to the same first scanning control signal end spic, and the control end of the second control transistor T2 in the same sub-display area 11 is connected to the same second scanning control signal end sv. In this way, the first control transistor T1 in the same sub-display area 11 is controlled by the control signal transmitted by the same first scanning control signal end spic, and the second control transistor T2 in the same sub-display area 11 is controlled by the control signal transmitted by the same second scanning control signal end sv. On the one hand, m sub-display areas 11 only need to set m first scanning control signal terminals spic and m second scanning control signal terminals sv, which is beneficial to reducing the number of first scanning control signal terminals spic and second scanning control signal terminals sv in the display panel 100 and simplifying the structure of the display panel 100; on the other hand, the same sub-display area 11 is controlled by the same first scanning control signal terminal spic, and the same sub-display area 11 is controlled by the same second scanning control signal terminal sv, which is beneficial to controlling the first control transistor T1 and the second control transistor T2 in the sub-display area 11, thereby realizing unified control of the display effect of the sub-pixel unit 111 of the same sub-display area 11.

[0062] Further, Fig.10 FIG. 1 is a schematic diagram of a display area provided by an embodiment of the present disclosure. Fig.11 Shown Fig.10 The corresponding timing diagram is: Fig.12 Shown Fig.10 For the corresponding display effect diagram, please refer to Figure 3 , Figure 10 to Figure 12The present disclosure provides an optional implementation scheme, m=2, the display area 10 includes two sub-display areas 11, namely a first sub-display area 11-1 and a second sub-display area 11-2; the first scanning control signal terminal spic corresponding to the first sub-display area 11-1 and the second scanning control signal terminal sv corresponding to the second sub-display area 11-2 receive the same control signal S1; the second scanning control signal terminal sv corresponding to the first sub-display area 11-1 and the first scanning control signal terminal spic corresponding to the second sub-display area 11-2 receive the same control signal S2.

[0063] Specifically, in this embodiment, the display panel 100 includes two sub-display areas 11, a first sub-display area 11-1 and a second sub-display area 11-2, and the first sub-display area 11-1 and the second sub-display area 11-2 are scanned simultaneously. When the first sub-display area 11-1 is scanned to achieve image refresh, the second sub-display area 11-2 is scanned to achieve image blacking; when the second sub-display area 11-2 is scanned to achieve image refresh, the first sub-display area 11-1 is scanned to achieve image blacking. When scanning in the sub-display area 11 to achieve image refresh, the control signal transmitted by the first scanning control signal terminal spic controls the first control transistor T1 to turn on; when scanning in the sub-display area 11 to achieve image blacking, the control signal transmitted by the second scanning control signal terminal sv controls the second control transistor T2 to turn on. When the first sub-display area 11-1 is scanned to achieve image refresh, and the second sub-display area 11-2 is scanned to achieve image blacking, the first scanning control signal terminal spic in the first sub-display area 11-1 controls the first control transistor T1 to turn on, and the second scanning control signal terminal sv in the second sub-display area 11-2 controls the second control transistor T2 to turn on; when the first sub-display area 11-1 is scanned to achieve image blacking, and the second sub-display area 11-2 is scanned to achieve image refresh, the second scanning control signal terminal sv in the first sub-display area 11-1 controls the second control transistor T2 to turn on, and the first scanning control signal terminal spic in the second sub-display area 11-2 controls the first control transistor T1 to turn on. It can be seen that the first control transistor T1 in the first sub-display area 11-1 and the second control transistor T2 in the second sub-display area 11-2 are turned on and off at the same time, and the second control transistor T2 in the first sub-display area 11-1 and the first control transistor T1 in the second sub-display area 11-2 are turned on and off at the same time. Therefore, in the embodiment of the present disclosure, the first scanning control signal terminal spic corresponding to the first sub-display area 11-1 and the second scanning control signal terminal sv corresponding to the second sub-display area 11-2 receive the same control signal S1; the second scanning control signal terminal sv corresponding to the first sub-display area 11-1 and the first scanning control signal terminal spic corresponding to the second sub-display area 11-2 receive the same control signal S2. Such a configuration is conducive to reducing the number of control signals received by the display panel 100, thereby reducing the wiring within the display panel 100 and simplifying the structure of the display panel 100.

[0064] Please refer to Figure 2 , Figure 3 , Fig.10 and Fig.11 In an optional embodiment of the present disclosure, the first scanning control signal terminal spic receives the first scanning control signal; the duration of one frame working time of the display panel 100 is t1, and within one frame working time of the display panel 100, the duration of the effective signal of the first scanning control signal corresponding to the single sub-display area 11 is t2, t2=t1 / m.

[0065] It should be noted that the present disclosure is described by taking the first control transistor T1 as an N-type transistor as an example, and the effective signal of the first scanning control signal is a high-level signal. The present disclosure is described only by taking this as an example and is not limited thereto.

[0066] Specifically, the display panel 100 includes m sub-display areas 11. During at least one frame of working time of the display panel 100, it includes m scanning sub-segments executed in sequence. In each scanning sub-segment, there is only one sub-display area 11 that performs scanning to refresh the image. When the sub-display area 11 performs image refresh, the first scanning control signal received by the first scanning control signal terminal spic is a valid signal. At this time, the first control transistor T1 is turned on and transmits the corresponding data voltage signal Dn to the first node N1. Therefore, the duration of the first scanning control signal corresponding to a single sub-display area 11 accounts for 1 / m of the duration of a frame of working time, and the duration of the valid signal of the first scanning control signal corresponding to a single sub-display area 11 is t1 / m. In this embodiment, during a frame of working time, each sub-display area 11 refreshes the image data line by line only in one scanning sub-segment. In this way, the sub-pixel unit 111 in each sub-display area 11 receives the image data for the same duration, which is conducive to improving display uniformity.

[0067] When the first scan control signal is a valid signal, the first control transistor T1 is turned on, the data voltage signal Dn is transmitted to the first node N1, and a voltage difference is generated between the data voltage signal Dn received by the pixel electrode and the common voltage signal VCOM received by the common electrode, driving the liquid crystal to deflect and realize pixel light emission. In an optional embodiment of the present disclosure, at the same time, only the first scan control signal corresponding to one sub-display area 11 is a valid signal. That is, at the same time, only one sub-display area 11 receives the data voltage signal Dn, realizes pixel light emission, and refreshes image data. This is conducive to preventing image crosstalk problems between different display areas 10, thereby improving the display effect of the display panel 100.

[0068] Fig.13 FIG. 1 is a timing diagram of another display panel provided by an embodiment of the present disclosure. Please refer to FIG. Figure 2 , Figure 3 and Fig.13 In an optional embodiment of the present disclosure, the second scan control signal terminal sv receives the second scan control signal SV; when the first scan control signal SPIC corresponding to the same sub-display area 11 is a valid signal, the second scan control signal SV is an invalid signal; when the first scan control signal SPIC corresponding to the same sub-display area 11 is an invalid signal, the second scan control signal SV is a valid signal.

[0069] It should be noted that the present disclosure is described by taking the second control transistor T2 as an N-type transistor as an example, and the effective signal of the second scanning control signal SV is a high-level signal. The present disclosure is described only by taking this as an example and is not limited thereto.

[0070] Specifically, in the display panel 100 provided in the present embodiment, in the same sub-display area 11, when the first scan control signal SPIC is a valid signal, the first control transistor T1 is turned on, the second scan control signal SV is an invalid signal, the second control transistor T2 is turned off, and the first node N1 receives the data voltage signal Dn. In the same sub-display area 11, when the first scan control signal SPIC is an invalid signal, the first control transistor T1 is turned off, the second scan control signal SV is a valid signal, the second control transistor T2 is turned on, and the first node N1 receives the common voltage signal VCOM. The first scan control signal SPIC and the second scan control signal SV corresponding to the same sub-display area 11 are opposite control signals. The first control transistor T1 and the second control transistor T2 only include two states, one of which is that the first control transistor T1 is turned on and the second control transistor T2 is turned off; the other is that the first control transistor T1 is turned off and the second control transistor T2 is turned on. In this way, the sub-pixel unit 111 receives the data voltage signal Dn and refreshes the image data when the first scanning control signal SPIC is a valid signal; it receives the common voltage signal VCOM and performs image blackout shielding when the first scanning control signal SPIC is an invalid signal, thereby avoiding the previous frame image and the current frame image from appearing in the same picture at the same time, which is beneficial to improving the crosstalk phenomenon of the display panel 100.

[0071] Fig.14 Shown Fig.13 For a schematic diagram of the display effect of the display panel driven by the timing shown, please refer to Figure 2 , Figure 3 , Fig.13 and Fig.14The present disclosure provides an optional implementation mode, in which the display panel 100 includes three sub-display areas 11, and within a scanning sub-segment, one sub-display area 11 performs image refresh, and the other sub-display areas 11 perform image blackening. Specifically, within a frame working time t1 of the display panel 100, three scanning sub-segments are included. In the first scanning sub-segment s1, the first sub-display area 11 starts to refresh the image data line by line, and the corresponding first scanning control signal SPIC-1 is a valid signal, and the second sub-display area 11 and the third sub-display area 11 respectively start scanning line by line to perform image blackening, and the corresponding second scanning control signals SV-2 and SV-3 are valid signals. In the second scanning sub-segment s2, the second sub-display area 11 starts to refresh the image data line by line, and the corresponding first scanning control signal SPIC-2 is a valid signal, and the first sub-display area 11 and the third sub-display area 11 respectively start scanning line by line to perform image blackening, and the corresponding second scanning control signals SV-1 and SV-3 are valid signals. In the third scanning sub-segment s3, the third sub-display area 11 starts to refresh the image data line by line, and the corresponding first scanning control signal SPIC-3 is a valid signal. The first sub-display area 11 and the second sub-display area 11 start scanning line by line to black out the image, and the corresponding second scanning control signals SV-1 and SV-2 are valid signals. In this way, it is helpful to avoid the image of the previous frame and the image of the current frame appearing in one frame at the same time, so as to improve the screen crosstalk problem of the display panel 100. In this embodiment, within a frame working time t1, each sub-display area 11 refreshes the image data line by line only in one scanning sub-segment, and the duration of the valid signal of the first scanning control signal SPIC corresponding to a single sub-display area 11 is t1 / m, and the image is blacked out at other times. In this way, the duration of each sub-display area 11 displaying the image is the same, which is helpful to improve the display uniformity.

[0072] Fig.15 FIG. 1 is a timing diagram of another display panel provided by an embodiment of the present disclosure. Please refer to FIG. Figure 2 , Figure 3 and Fig.15 In an optional embodiment of the present disclosure, the second scan control signal terminal sv receives the second scan control signal SV; within a frame working time t1 of the display panel 100, before the start time of the valid signal of the first scan control signal SPIC corresponding to the same sub-display area 11, the second scan control signal SV is a valid signal; after the start time of the valid signal of the first scan control signal SPIC corresponding to the same sub-display area 11, the second scan control signal SV is an invalid signal.

[0073] Specifically, during one frame of working time of the display panel 100, when the valid signal of the first scan control signal SPIC corresponding to the sub-display area 11 starts, the sub-display area 11 starts to refresh the image line by line. Before this, the sub-display area 11 performs image blacking to prevent the image of the previous frame from interfering with the image of the current frame. Therefore, before the start time of the valid signal of the first scan control signal SPIC corresponding to the same sub-display area 11, the second scan control signal SV is a valid signal, the second control transistor T2 is turned on, and the sub-display area 11 performs image blacking. After the first scan control signal SPIC corresponding to the sub-display area 11 jumps to a valid signal, the sub-display area 11 starts to refresh the image line by line, and before the next frame of working time starts, the image blacking is no longer performed. Therefore, after the first scan control signal SPIC corresponding to the same sub-display area 11 jumps to a valid signal, the second scan control signal SV is an invalid signal, the first control transistor T1 is turned on, the second control transistor T2 is turned off, and the sub-display area 11 no longer performs image blacking. After the valid signal of the first scanning control signal SPIC of the sub-display area 11 ends, the image data of the sub-display area 11 has been refreshed, the first scanning control signal SPIC and the second scanning control signal SV are both invalid signals, and the sub-pixel unit 111 can maintain the refreshed image, thereby extending the display time of part of the sub-display area 11, which is beneficial to improving the display brightness of the display panel 100.

[0074] Furthermore, the present disclosure provides an optional implementation mode: Fig.16 Shown Fig.15 For a schematic diagram of the display effect of the display panel driven by the timing shown, please refer to Figure 2 , Figure 3 , Fig.15 and Fig.16, the display panel 100 includes three sub-display areas 11. One frame working time t1 of the display panel 100 includes three scanning sub-segments. The first sub-display area 11 starts to refresh the image data line by line in the first scanning sub-segment s1. The first scanning control signal SPIC-1 is a valid signal, and the second scanning control signal SV-1 is an invalid signal. At the end of the first scanning sub-segment s1, the first scanning control signal SPIC-1 jumps to an invalid signal, and the second scanning control signal SV-1 remains an invalid signal. At this time, the first sub-display area 11 has completed the image refresh of the current frame, and the current display state can be maintained in the subsequent scanning sub-segments, and the image is not set to black. Therefore, in the second scanning sub-segment s2 and the third scanning sub-segment s3, the first scanning control signal SPIC-1 and the second scanning control signal SV-1 corresponding to the first sub-display area 11 are both invalid signals. The second sub-display area 11 starts to refresh the image data line by line in the second scanning sub-segment s2, the first scanning control signal SPIC-2 is a valid signal, and the second scanning control signal SV-2 is an invalid signal; before the second sub-display area 11 starts to refresh the image data, the second scanning control signal SV-2 is a valid signal, and the second sub-display area 11 performs image blackening to avoid crosstalk between the image of the previous frame and the image of the current frame. When the second sub-display area 11 starts to refresh the image data line by line, the second scanning control signal SV-2 jumps to an invalid signal. At the end of the second scanning sub-segment s2, the first scanning control signal SPIC-2 jumps to an invalid signal, and the second scanning control signal SV-2 remains an invalid signal. At this time, the second sub-display area 11 has completed the image refresh of the current frame, and the current display state can be maintained in the subsequent scanning sub-segments, and the image blackening is not performed. Therefore, in the third scanning sub-segment s3, the first scanning control signal SPIC-2 and the second scanning control signal SV-2 corresponding to the second sub-display area 11 are both invalid signals. The third sub-display area 11 starts to refresh the image data line by line in the third scanning sub-segment s3. In the third scanning sub-segment s3, the first scanning control signal SPIC-3 is a valid signal, and the second scanning control signal SV-3 is an invalid signal. Before the third sub-display area 11 starts to refresh the image data, the second scanning control signal SV-3 is a valid signal, and the third sub-display area 11 performs image blacking to avoid crosstalk between the image of the previous frame and the image of the current frame. When the third sub-display area 11 starts to refresh the image data line by line, the second scanning control signal SV-3 jumps to an invalid signal. At the end of the third scanning sub-segment s3, the first scanning control signal SPIC-3 jumps to an invalid signal. At this time, the third sub-display area 11 has completed the image refresh of the current frame, and one frame of working time ends.

[0075] Based on the same inventive concept, the present disclosure provides a display device, Fig.17 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present disclosure, please refer to FIG. Fig.17The display device 200 includes a display panel 100 , and the display panel 100 is any display panel 100 provided in the present disclosure.

[0076] It should be noted that the embodiment of the display device 200 provided in the embodiment of the present disclosure can refer to the embodiment of the display panel 100 described above, and will not be repeated. The display device 200 provided in the present application can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a navigator, or any other product or component with a display function.

[0077] It can be seen from the above embodiments that the display panel and display device provided by the present disclosure achieve at least the following beneficial effects:

[0078] The present disclosure provides a display panel and a display device, wherein the display panel includes a display area, the display area includes a plurality of sub-display areas; the sub-display area includes a plurality of pixel rows, the pixel rows include a plurality of sub-pixel units, and the sub-pixel units include pixel electrodes and driving transistors. The display panel also includes a first scan line, the control end of the driving transistor is electrically connected to the gate driving circuit through the first scan line, the first end of the driving transistor is connected to the first node, and the second end of the driving transistor is connected to the pixel electrode; the gate driving circuit is configured to transmit a scan signal to the sub-pixel unit, the scan signal turns the driving transistor on or off; the driving transistor transmits the signal of the first node to the pixel electrode under the control of the scan signal. During at least one frame of working time of the display panel, it includes a plurality of scan sub-segments executed in sequence, and in at least one scan sub-segment, the first node in the pixel row in one sub-display area receives a data voltage signal, and the first node in the pixel row in other sub-display areas receives a common voltage signal. With such a configuration, when the display panel scans and refreshes the image frame by frame, the first node in the sub-display area corresponding to the refresh area receives the data voltage signal to achieve image refresh; the first node in the sub-display area corresponding to the unrefreshed area receives the common voltage signal, and the corresponding area is set to black, preventing the previous frame image and the current frame image from appearing in the same frame, thereby improving the crosstalk problem between the previous and next frame images of the display panel, which is beneficial to improving the display effect of the display panel.

[0079] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0080] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A display area, wherein the display area includes m sub-display areas, m≥2, and m is an integer; the sub-display area includes a plurality of pixel rows, the pixel rows include a plurality of sub-pixel units, and the sub-pixel units include pixel electrodes and driving transistors; a first scanning line, wherein the control end of the driving transistor is electrically connected to the gate driving circuit through the first scanning line, the first end of the driving transistor is connected to the first node, and the second end of the driving transistor is connected to the pixel electrode; The gate driving circuit is configured to transmit a scanning signal to the sub-pixel unit, wherein the scanning signal turns the driving transistor on or off; and the driving transistor transmits the signal of the first node to the pixel electrode under the control of the scanning signal; The first node receives at least a data voltage signal or a common voltage signal; During at least one working frame of the display panel, m scanning sub-segments are included and executed sequentially, and within the scanning sub-segments, the pixel rows in each of the sub-display areas receive the scanning signals in time-sharing order; In at least one of the scanning sub-segments, the first nodes in the pixel rows in one of the sub-display areas receive the data voltage signal, and the first nodes in the pixel rows in other sub-display areas receive the common voltage signal.

2. The display panel according to claim 1, characterized in that: The gate driving circuit includes a multi-stage shift register unit and an enable signal line, wherein the shift register unit is electrically connected to the first scan line, the first stage of the shift register unit corresponding to the sub-display area is connected to the enable signal line, and the enable signal line receives an enable signal; The start signal is used to start the first-stage shift register unit corresponding to the sub-display area to start transmitting the scan signal; during at least one frame of working time of the display panel, the start signal includes m valid pulse signals; The scanning of different sub-display areas is started simultaneously.

3. The display panel according to claim 1, characterized in that: The sub-pixel unit further includes a first control transistor and a second control transistor; The control end of the first control transistor is electrically connected to the first scan control signal end, the first end receives the data voltage signal, and the second end is electrically connected to the first node; the control end of the second control transistor is electrically connected to the second scan control signal end, the first end receives the common voltage signal, and the second end is electrically connected to the first node.

4. The display panel according to claim 3, characterized in that: Also includes: A first driving chip and a first data line; The first end of the first control transistor is electrically connected to the first driving chip through the first data line, and the first driving chip is configured to provide the data voltage signal to the sub-pixel unit; The first ends of the first control transistors in the same pixel column are connected to the same first data line.

5. The display panel according to claim 3, characterized in that: Also includes: A second driving chip and a common electrode line; The first end of the second control transistor is electrically connected to the second driving chip through the common electrode line, and the second driving chip is configured to provide the common voltage signal to the sub-pixel unit; The first ends of the second control transistors in the same pixel column are connected to the same common electrode line.

6. The display panel according to claim 3, characterized in that: The control end of the first control transistor in the same sub-display area is connected to the same first scanning control signal end; The control end of the second control transistor in the same sub-display area is connected to the same second scan control signal end.

7. The display panel according to claim 3, characterized in that: m=2, the display area includes two sub-display areas, namely the first sub-display area and the second sub-display area; the first scanning control signal end corresponding to the first sub-display area and the second scanning control signal end corresponding to the second sub-display area receive the same control signal; the second scanning control signal end corresponding to the first sub-display area and the first scanning control signal end corresponding to the second sub-display area receive the same control signal.

8. The display panel according to claim 3, characterized in that: The first scanning control signal terminal receives a first scanning control signal; The duration of one frame of working time of the display panel is t1. During the one frame of working time of the display panel, the duration of the effective signal of the first scanning control signal corresponding to a single sub-display area is t2, and t2=t1 / m.

9. The display panel according to claim 8, characterized in that: At the same time, only the first scanning control signal corresponding to one of the sub-display areas is a valid signal.

10. The display panel according to claim 8, characterized in that: The second scanning control signal terminal receives a second scanning control signal; When the first scanning control signal corresponding to the same sub-display area is a valid signal, the second scanning control signal is an invalid signal; when the first scanning control signal corresponding to the same sub-display area is an invalid signal, the second scanning control signal is a valid signal.

11. The display panel according to claim 8, characterized in that: The second scanning control signal terminal receives a second scanning control signal; During one frame of working time of the display panel, before the start time of the valid signal of the first scan control signal corresponding to the same sub-display area, the second scan control signal is a valid signal; after the start time of the valid signal of the first scan control signal corresponding to the same sub-display area, the second scan control signal is an invalid signal.

12. A display device, characterized in that: A display panel comprising the display panel according to any one of claims 1 to 11.

Images