A goa circuit for bidirectional scanning

Abstract

The application discloses a GOA circuit for bidirectional scanning, comprising a plurality of cascaded GOA units, an nth GOA unit for outputting an nth scanning signal, the nth GOA unit comprising: a forward and reverse scanning module for accepting a forward control signal UD and a reverse control signal DU; a node control module for controlling the high and low of the potentials of a first node Q and a second node QB; an output module for outputting a scanning signal; and a reset module for resetting the scanning signal. The application has the beneficial effect that the output of forward and reverse scanning signals can be met without increasing the switching of forward and reverse scanning switch signals.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to a GOA circuit for bidirectional scanning. Background Art

[0002] In display driver technology, gate-on-array (GOA) technology has been widely adopted in product design. Using a shift register, GOA signals enable gate lines row by row, writing data to pixels. This replaces gate IC design and significantly reduces costs. In displays, GOA circuit designs often only support unidirectional scanning: from the first row upwards or from the last row downwards, failing to support bidirectional scanning. By changing the timing, a GOA circuit design can support both top-down and bottom-up scanning, significantly improving display uniformity and detecting in-plane defects.

[0003] Existing improved reversible GOA circuits have the following disadvantages: 1. The internal node control circuit is complex, making this circuit unsuitable for manufacturing liquid crystal display panels into narrow-frame products; 2. Current GOA circuits often suffer from threshold voltage drift due to circuit problems, requiring additional compensation circuits, which is even more detrimental to the design of borderless display products.

[0004] Therefore, the present invention proposes a GOA circuit with a simple structure, strong stability and conducive to achieving a narrow frame. Summary of the Invention

[0005] The purpose of the present invention is to provide a GOA circuit for bidirectional scanning, which realizes a GOA circuit that can complete forward and reverse scanning with a simple circuit structure.

[0006] The present invention aims to realize a GOA circuit for bidirectional scanning through the following technical solution, comprising a plurality of cascaded GOA units, wherein the n-th GOA unit is used to output an n-th level scanning signal, and the n-th level GOA unit comprises: a forward and reverse scanning module, used to receive a forward control signal and a reverse control signal;

[0007] A node control module, controlling the potential of the first node and the second node according to a forward control signal or a reverse control signal;

[0008] An output module, outputting a scanning signal according to the potential of the first node and the second node;

[0009] The reset module is used to reset the scan signal according to the level of the second node potential after outputting the scan signal.

[0010] Furthermore, the forward and reverse scan module includes a first transistor, a sixth transistor and a seventh transistor; the second source and drain of the sixth transistor are coupled to the first source and drain of the seventh transistor and the first source and drain of the first transistor; the gate of the sixth transistor is coupled to the forward control signal, and the first source and drain are coupled to the n-1th level scan signal; the gate of the seventh transistor is coupled to the reverse control signal, and the second source and drain are coupled to the n+1th level scan signal; the gate of the first transistor is coupled to the first clock signal line, and the second source and drain of the first transistor are coupled to the first node, the node control module and the output module.

[0011] Furthermore, the forward and reverse scanning module includes a sixth transistor and a seventh transistor; the second source and drain of the sixth transistor are coupled to the first source and drain and the first node of the seventh transistor; the gate of the sixth transistor is coupled to the n-1th level scanning signal, and the first source and drain are coupled to the forward control signal; the gate of the seventh transistor is coupled to the n+1th level scanning signal, and the first source and drain are coupled to the reverse control signal.

[0012] Furthermore, the output module includes a fourth transistor, a first capacitor and a scan output signal line;

[0013] The gate of the fourth transistor is coupled to the second source and drain of the first transistor and one end of the first capacitor, the first source and drain of the fourth transistor are coupled to the second clock signal line, and the second source and drain of the fourth transistor are coupled to the other end of the first capacitor and the scan output signal line.

[0014] Furthermore, the reset module includes a fifth transistor and a second capacitor; the gate of the fifth transistor is coupled to the second source and drain of the second transistor and one end of the second capacitor, the first source and drain of the fifth transistor is coupled to the scan output signal line, and the second source and drain of the fifth transistor is coupled to the ground line.

[0015] Furthermore, the node control module includes a second transistor and a third transistor; a first source and drain of the second transistor is coupled to the operating voltage line, a gate of the second transistor is coupled to the first clock signal line, and a second source and drain of the second transistor is coupled to the second source and drain of the third transistor and the second node;

[0016] The gate of the third transistor is coupled to the second source and drain of the first transistor, and the first source and drain of the third transistor is coupled to the first clock signal line.

[0017] Further, the node control module includes a second transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0018] The gate and the first source-drain electrode of the ninth transistor are coupled to a working voltage line, the second source-drain electrode of the ninth transistor is coupled to the second source-drain electrode of the eighth transistor, the gate of the eighth transistor is coupled to a second clock signal line, and the first source-drain electrode of the eighth transistor is coupled to a ground line;

[0019] The gate of the tenth transistor is coupled to the first source-drain electrode of the ninth transistor, the first source-drain electrode of the tenth transistor is coupled to a working voltage line, the second source-drain electrode of the tenth transistor is coupled to the gate of the second transistor, the first source-drain electrode of the second transistor is coupled to a working voltage line, the second source-drain electrode of the second transistor is coupled to the gate of the twelfth transistor and a second node, the second source-drain electrode of the twelfth transistor is coupled to the gate of the thirteenth transistor, the first source-drain electrode of the thirteenth transistor is coupled to a first node, and the second source-drain electrode of the thirteenth transistor is coupled to a ground line.

[0020] The gate of the eleventh transistor is coupled to the first node, the first source-drain electrode of the eleventh transistor is coupled to a ground line, and the second source-drain electrode of the eleventh transistor is coupled to the gate of the thirteenth transistor; the gate of the third transistor is coupled to the first node, the first source-drain electrode of the third transistor is coupled to a ground line, and the second source-drain electrode of the third transistor is coupled to a second node.

[0021] Further, the gate of the sixth transistor is coupled to a forward control signal, and the first source-drain electrode of the sixth transistor is coupled to an (n-1)th scanning signal line.

[0022] The gate of the seventh transistor is coupled to a reverse control signal, and the second source-drain electrode of the seventh transistor is coupled to an (n+1)th scanning signal line.

[0023] Further, the gate of the sixth transistor is coupled to an (n-1)th scanning signal line, and the first source-drain electrode of the sixth transistor is coupled to a forward control signal.

[0024] The gate of the seventh transistor is coupled to an (n+1)th scanning signal line, and the second source-drain electrode of the seventh transistor is coupled to a reverse control signal.

[0025] Further, when the GOA circuit is forward scanned, the forward control signal is at a high potential, and the reverse scanning control signal is at a low potential.

[0026] When the GOA circuit is reverse scanned, the forward control signal is at a low potential, and the reverse scanning signal is at a high potential.

[0027] Further, the pulse periods of the first clock signal line and the second clock signal line are the same, but the potential changes are opposite.

[0028] The present application has the following advantages:

[0029] The forward and reverse scanning module of the present invention includes a sixth transistor and a seventh transistor. The gate of the sixth transistor can be coupled to the n-1th level scanning signal or the forward control signal, and the gate of the seventh transistor can be coupled to the n+1th level scanning signal or the reverse control signal. The two transistors can switch between forward and reverse scanning.

[0030] The present invention further provides a node control module, which includes a second transistor and a third transistor. The potential of the second node can be controlled by turning the third transistor and the second transistor on and off. The first source and drain of the second transistor are connected to a constant high-potential working voltage line, and the second source and drain are connected to the second node and the fifth transistor. This ensures that the potential of the second node does not drop outside the second stage (scan signal input stage), thereby improving the stability of the GOA circuit.

[0031] Through a simple circuit design, the present invention can achieve forward and reverse scanning switching without the need for a switch switching signal compared to the existing technology; furthermore, compared with the existing forward and reverse scanning circuit, the internal circuit structure is simplified, and the number of transistors and capacitors used in the internal circuit is reduced, which is greatly beneficial for the liquid crystal panel to achieve a narrow-edge or borderless design.

[0032] The present invention also prevents some transistors from repeatedly turning on and causing threshold voltage drift by setting multiple transistors to work alternately, thereby improving the stability of the circuit; and when designing the circuit structure of multiple transistors, the present invention also sets the on and off of the thirteenth transistor to achieve the first node reaching the first high potential; it also ensures that the charge of the first node will not be lost when the second high potential is reached, and the potential remains stable when the scanning signal is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A circuit diagram of embodiment 1 of the present invention;

[0034] Figure 2 This is a timing diagram of the first embodiment of the present invention;

[0035] Figure 3 This is a circuit diagram of embodiment 2 of the present invention;

[0036] Figure 4 This is a timing diagram of the second embodiment of the present invention;

[0037] Figure 5 This is a circuit diagram of embodiment 3 of the present invention;

[0038] Figure 6 This is a timing diagram of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0040] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the drawings, or the directions or positional relationships in which the product of the application is usually placed, or the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0041] It should be noted that the embodiments in the application and the features and technical solutions in the embodiments can be combined with each other without conflict. Embodiment

[0042] The application provides a GOA circuit for bidirectional scanning, comprising a plurality of cascaded GOA units, an nth GOA unit being used for outputting an nth scanning signal,

[0043] Reference Figure 1 For Embodiment One, the nth GOA unit comprises: a forward and reverse scanning module, used for receiving a forward control signal UD and a reverse control signal DU; a node control module, used for controlling the high and low of the potentials of a first node Q and a second node QB according to the forward control signal UD or the reverse control signal DU; an output module, used for outputting a scanning signal according to the high and low of the potentials of the first node Q and the second node QB; and a reset module, used for resetting the scanning signal according to the high and low of the potential of the second node QB after the scanning signal is outputted.

[0044] In some specific embodiments, the forward and reverse scanning module comprises a first transistor T1, a sixth transistor T6 and a seventh transistor T7; a second source-drain electrode of the sixth transistor T6 is coupled to a first source-drain electrode of the seventh transistor T7 and a first source-drain electrode of the first transistor T1; a gate of the first transistor T1 is coupled to a first clock signal line ClkA, and a second source-drain electrode of the first transistor T1 is coupled to the first node Q.

[0045] In some specific embodiments, the node control module comprises a second transistor T2 and a third transistor T3; a first source-drain electrode of the second transistor T2 is coupled to a working voltage line Vdd, a gate of the second transistor T2 is coupled to the first clock signal line ClkA, and a second source-drain electrode of the second transistor T2 is coupled to a second source-drain electrode of the third transistor T3 and a second node QB; a gate of the third transistor T3 is coupled to a second source-drain electrode of the first transistor T1, and a first source-drain electrode of the third transistor T3 is coupled to the first clock signal line ClkA.

[0046] In some specific embodiments, the output module includes a fourth transistor T4, a first capacitor C1 and a scan output signal line Gn; the gate of the fourth transistor T4 is coupled to the second source and drain of the first transistor T1 and one end of the first capacitor C1, the first source and drain of the fourth transistor T4 are coupled to the second clock signal line ClkB, and the second source and drain of the fourth transistor T4 are coupled to the other end of the first capacitor C1 and the scan output signal line Gn.

[0047] In some specific embodiments, the reset module includes a fifth transistor T5 and a second capacitor C2; the gate of the fifth transistor T5 is coupled to the second source and drain of the second transistor T2 and one end of the second capacitor C2, the first source and drain of the fifth transistor T5 is coupled to the scan output signal line Gn, and the second source and drain of the fifth transistor T5 is coupled to the ground line Vss.

[0048] While working, refer to Figure 2 , the GOA circuit outputs a scanning signal in three stages. When the GOA circuit is scanning forward, the forward control signal UD is at a high potential, and the sixth transistor T6 is turned on; the reverse scanning control signal DU is at a low potential, and the seventh transistor T7 is turned off;

[0049] Phase 1: The first clock signal line ClkA jumps to a high level, and the first transistor T1 is turned on; the n-1th level scanning signal line Gn-1 writes a first high potential to the first node Q through the first transistor T1, so that the fourth transistor T4 is turned on;

[0050] Phase 2: The first clock signal line ClkA jumps to a low level, and the first transistor T1 is turned off. The second clock signal line ClkB jumps to a high level, and is charged through the first capacitor C1 via the fourth transistor T4. The first capacitor C1 raises the potential of the first node Q to a second high potential through capacitive coupling. At this time, the third transistor T3 is fully turned on, causing the charge at the potential of the second node QB to transfer to the first clock signal line ClkA. The potential of the second node QB drops to the first low potential, and the fifth transistor T5 is turned off. At this time, the scan output signal line Gn outputs a high level.

[0051] Phase 3: The second clock signal line ClkB jumps to a low level, the first clock signal line ClkA jumps to a high level, the fourth transistor T4 is turned off, and the first transistor T1 and the second transistor T2 are turned on;

[0052] At this time, the first node Q transfers charges to the n-1th level scanning signal line Gn-1 through the first transistor T1, the potential of the first node Q drops to zero potential, and the third transistor T3 is turned off;

[0053] The second transistor T2 is turned on, and the working voltage line Vdd increases the potential of the second node QB through the second transistor T2, turning on the fifth transistor T5. At this time, the scan output signal line Gn is pulled down to a low potential and outputs a low-level signal.

[0054] When the GOA circuit needs to scan in the reverse direction, the forward control signal UD is at a low potential, the reverse scanning signal DU is at a high potential, and the rest of the process is similar to the forward scanning process.

[0055] The forward and reverse scanning module of the present invention includes a sixth transistor T6 and a seventh transistor T7. The gate of the sixth transistor T6 can be coupled to the n-1th level scanning signal Gn-1 or the forward control signal UD, and the gate of the seventh transistor T7 can be coupled to the n+1th level scanning signal Gn+1 or the reverse control signal DU. The two transistors can switch between forward and reverse scanning.

[0056] The present invention provides a node control module, which includes a second transistor T2 and a third transistor T3. The potential of the second node can be controlled by turning the third transistor T3 and the second transistor T2 on and off. The first source and drain of the second transistor T2 are connected to the constant high-potential working voltage line Vdd, and the second source and drain are connected to the second node QB and the fifth transistor T5. This ensures that the potential of the second node QB does not drop outside the second stage (when the scan signal is output), thereby improving the stability of the GOA circuit.

[0057] Through a simple circuit design, the present invention can achieve forward and reverse scanning switching without the need for a switch switching signal compared to the existing technology; furthermore, compared with the existing forward and reverse scanning circuit, the internal circuit structure is simplified, and the number of transistors and capacitors used in the internal circuit is reduced, which is greatly beneficial for the liquid crystal panel to achieve a narrow-edge or borderless design. Example

[0058] In some specific embodiments, the second embodiment of the present invention refers to Figure 3 , the node control module includes a second transistor T2, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13;

[0059] The gate and first source and drain of the ninth transistor T9 are coupled to the operating voltage line Vdd, the second source and drain of the ninth transistor T9 are coupled to the second source and drain of the eighth transistor T8, the gate of the eighth transistor T8 is coupled to the second clock signal line ClkB, and the first source and drain of the eighth transistor T8 is coupled to the ground line Vss;

[0060] The gate of the tenth transistor T10 is coupled to the first source-drain electrode of the ninth transistor T9, the first source-drain electrode of the tenth transistor T10 is coupled to the working voltage line Vdd, and the second source-drain electrode of the tenth transistor T10 is coupled to the gate of the second transistor T2; the first source-drain electrode of the second transistor T2 is coupled to the working voltage line Vdd, and the second source-drain electrode of the second transistor T2 is coupled to the gate of the twelfth transistor T12 and the second node QB; the second source-drain electrode of the twelfth transistor T12 is coupled to the gate of the thirteenth transistor T13, the first source-drain electrode of the thirteenth transistor T13 is coupled to the first node Q, and the second source-drain electrode of the thirteenth transistor T13 is coupled to the ground line Vss.

[0061] The gate of the eleventh transistor T11 is coupled to the first node Q, the first source-drain electrode of the eleventh transistor T11 is coupled to the ground line Vss, and the second source-drain electrode of the eleventh transistor T11 is coupled to the gate of the thirteenth transistor T13; the gate of the third transistor T3 is coupled to the first node Q, the first source-drain electrode of the third transistor T3 is coupled to the ground line Vss, and the second source-drain electrode of the third transistor T3 is coupled to the second node QB.

[0062] In operation, referring to Figure 4 , the GOA circuit outputs the scanning signal in three stages, when the GOA circuit is forward scanned, the forward control signal UD is high, and the sixth transistor T6 is turned on; the reverse scanning control signal DU is low, and the seventh transistor T7 is turned off.

[0063] First, the first clock signal line ClkA jumps to high level, and the first transistor T1 is turned on; the (n-1)th scanning signal line Gn-1 writes the first high level to the first node Q through the first transistor T1; at the same time, the first high level makes the eleventh transistor T11 partially conductive and the third transistor T3 partially conductive; the eleventh transistor T11 is partially conductive, so that the signal of the ground line Vss reaches the thirteenth transistor T13, thereby the thirteenth transistor T13 changes from full conduction to partial conduction, so that the charge of the (n-1)th scanning signal line Gn-1 writing the first high level to the first node Q through the first transistor T1 is reduced by the charge taken away by the thirteenth transistor T13; the third transistor T3 partially makes the second node QB transfer the charge to the ground line Vss through the third transistor, so as to drop to the first low level;

[0064] Then, the first clock signal line ClkA jumps to a low level, and the second clock signal line ClkB jumps to a high level. At this time, the fourth transistor T4 is turned on, and the second clock signal ClkB inputs a high-level signal through the fourth transistor T4, so that the first capacitor C1 is coupled upward to the first node Q, raising the potential of the first node Q to the second high potential. At this time, the eleventh transistor T11 and the third transistor T3 are fully turned on. The eleventh transistor T11 conducts the low signal of the ground line Vss, turning off the thirteenth transistor T13. As a result, the potential of the first node Q does not drop due to charge loss. The third transistor T3 is completely turned on, causing the potential of the second node QB to drop to the second low potential, and the fifth transistor T5 is turned off.

[0065] At the same time as the second clock signal line ClkB jumps to a high level, the eighth transistor T8 is turned on, and the ground line Vss inputs a low potential signal to the gate of the tenth transistor T10 through the eighth transistor T8. The tenth transistor T10 is turned off, causing the second transistor T2 to stop receiving Vdd, thereby turning off the second transistor T2. As a result, the twelfth transistor T12 is turned off, thereby ensuring that the thirteenth transistor T13 is also turned off. The thirteenth transistor T13 is turned off to ensure that the potential of the first node Q is at the second high potential during the scan signal output period, maintaining the potential stable.

[0066] At this time, the output scanning signal line Gn outputs a high potential;

[0067] Finally, the second clock signal line ClkB jumps to a low level, the first clock signal line ClkA jumps to a high level, the fourth transistor T4 is turned off, and the first transistor T1 is turned on;

[0068] The second clock signal line ClkB jumps to a low level, the eighth transistor T8 is turned off, so that the gate of the tenth transistor T10 receives the high level signal input by the ninth transistor T9, the tenth transistor T10 is turned on, the second transistor T2 is turned on, and thus the twelfth transistor T12 is turned on;

[0069] The twelfth transistor T12 is turned on, so that the thirteenth transistor T13 is turned on; the potential of the first node Q drops to a low potential through the first transistor T1 and the thirteenth transistor T13, so that the eleventh transistor T11 and the third transistor T3 are turned off;

[0070] At the same time, the second transistor T2 is turned on, so that the potential of the second node QB is increased by the working voltage Vdd, and the fifth transistor T5 is turned on. At this time, the output scanning signal line Gn outputs a low level.

[0071] During the second phase, the eleventh transistor T11, the third transistor T3, and the eighth transistor T8 operate. The eleventh transistor T11 and the third transistor T3 lower the potential of the second node QB by being turned on. The eighth transistor T8, after being turned on, receives a low-level signal from the ground line Vss, thereby turning off the subsequent transistors. This prevents the charge at the first node Q from being lost through the thirteenth transistor T13, thereby ensuring stability during the output of the scan signal.

[0072] The alternating operation of the eleventh transistor T11, the third transistor T3, the eighth transistor T8 and other transistors completes the conversion of the potential of the first node Q and the second node QB. The alternating operation can reduce the number of times the transistor itself is repeatedly turned on to complete the high and low potential conversion, thereby preventing the threshold voltage of the transistor from shifting. Example

[0073] like Figure 5 and Figure 6 In the third embodiment shown, in some specific embodiments, the forward and reverse scanning module includes a sixth transistor T6 and a seventh transistor T7; the second source and drain of the sixth transistor T6 are coupled to the first source and drain of the seventh transistor T7 and the first node Q; the gate of the sixth transistor T6 is coupled to the n-1th level scanning signal line Gn-1, and the first source and drain of the sixth transistor T6 are connected to the forward control signal UD; the gate of the seventh transistor T7 is coupled to the n+1th level scanning signal line Gn+1, and the second source and drain of the seventh transistor T7 are connected to the reverse control signal DU.

[0074] When the GOA circuit is scanning forward, the forward control signal UD is at a high potential and the reverse scanning control signal DU is at a low potential; when the GOA circuit is scanning reverse, the forward control signal UD is at a low potential and the reverse scanning signal DU is at a high potential.

[0075] The n-1th level scanning signal line Gn-1, the nth level scanning signal line (output scanning signal line Gn), and the n+1th level scanning signal line Gn+1 all jump once in one working cycle, and the jumping time is when the falling edge of the previous scanning signal and the rising edge of the next scanning signal are generated simultaneously.

[0076] In this embodiment, only one clock signal is needed to realize the normal output of the scanning signal, thereby saving one clock signal and one transistor and simplifying the circuit structure.

[0077] The above embodiments merely represent preferred implementations, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art will be able to make various modifications and improvements without departing from the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A GOA circuit for bidirectional scanning, characterized in that: The device comprises a plurality of cascaded GOA units, wherein the n-th level GOA unit is used to output the n-th level scanning signal, and the n-th level GOA unit comprises: A forward and reverse scanning module is used to receive a forward control signal (UD) and a reverse control signal (DU); A node control module controls the potential of the first node (Q) and the second node (QB) according to a forward control signal (UD) or a reverse control signal (DU); An output module outputs a scan signal according to the potentials of the first node (Q) and the second node (QB); a reset module, configured to reset the scan signal according to the potential of the second node (QB) after outputting the scan signal; The node control module includes a second transistor (T2), an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), a third transistor (T3), an eleventh transistor (T11), a twelfth transistor (T12) and a thirteenth transistor (T13); The gate and the first source and drain of the ninth transistor (T9) are both coupled to the operating voltage line (Vdd), the second source and drain of the ninth transistor (T9) are coupled to the second source and drain of the eighth transistor (T8), the gate of the eighth transistor (T8) is coupled to the second clock signal line (ClkB), and the first source and drain of the eighth transistor (T8) is coupled to the ground line (Vss); The gate of the tenth transistor (T10) is coupled to the first source and drain of the ninth transistor (T9), the first source and drain of the tenth transistor (T10) is coupled to the operating voltage line (Vdd), and the second source and drain of the tenth transistor (T10) is coupled to the gate of the second transistor (T2); the first source and drain of the second transistor (T2) is coupled to the operating voltage line (Vdd), and the second source and drain of the second transistor (T2) is coupled to the gate of the twelfth transistor (T12) and the second node (QB); the second source and drain of the twelfth transistor (T12) is coupled to the gate of the thirteenth transistor (T13), the first source and drain of the thirteenth transistor (T13) is coupled to the first node (Q), and the second source and drain of the thirteenth transistor (T13) is coupled to the ground line (Vss); The gate of the eleventh transistor (T11) is coupled to the first node (Q), the first source and drain of the eleventh transistor (T11) are coupled to the ground line (Vss), and the second source and drain of the eleventh transistor (T11) are coupled to the gate of the thirteenth transistor (T13); the gate of the third transistor (T3) is coupled to the first node (Q), the first source and drain of the third transistor (T3) are coupled to the ground line (Vss), and the second source and drain of the third transistor (T3) are coupled to the second node (QB).

2. A GOA circuit for bidirectional scanning according to claim 1, characterized in that, The forward and reverse scanning module includes a first transistor (T1), a sixth transistor (T6) and a seventh transistor (T7); the second source and drain of the sixth transistor (T6) are coupled to the first source and drain of the seventh transistor (T7) and the first source and drain of the first transistor (T1); the gate of the first transistor (T1) is coupled to a first clock signal line (ClkA), and the second source and drain of the first transistor (T1) are coupled to a first node (Q), a node control module and an output module.

3. A GOA circuit for bidirectional scanning according to claim 1, characterized in that: The forward and reverse scanning module comprises a sixth transistor (T6) and a seventh transistor (T7); the second source and drain of the sixth transistor (T6) are coupled to the first source and drain and the first node (Q) of the seventh transistor (T7).

4. A GOA circuit for bidirectional scanning according to any one of claim 2 or 3, characterized in that: The output module includes a fourth transistor (T4), a first capacitor (C1) and a scan output signal line (Gn); The gate of the fourth transistor (T4) is coupled to the second source and drain of the first transistor (T1) and one end of the first capacitor (C1), the first source and drain of the fourth transistor (T4) are coupled to the second clock signal line (ClkB), and the second source and drain of the fourth transistor (T4) are coupled to the other end of the first capacitor (C1) and the scan output signal line (Gn).

5. A GOA circuit for bidirectional scanning according to claim 4, characterized in that: The reset module includes a fifth transistor (T5) and a second capacitor (C2); the gate of the fifth transistor (T5) is coupled to the second source and drain of the second transistor (T2) and one end of the second capacitor (C2), the first source and drain of the fifth transistor (T5) is coupled to the scan output signal line (Gn), and the second source and drain of the fifth transistor (T5) is coupled to the ground line (Vss).

6. A GOA circuit for bidirectional scanning according to claim 2, characterized in that: The gate of the sixth transistor (T6) is coupled to the forward control signal (UD), and the first source and drain of the sixth transistor (T6) are coupled to the n-1th level scanning signal line (Gn-1); The gate of the seventh transistor (T7) is coupled to the reverse control signal (DU), and the second source and drain of the seventh transistor (T7) are coupled to the n+1th stage scanning signal line (Gn+1).

7. A GOA circuit for bidirectional scanning according to claim 3, characterized in that: The gate of the sixth transistor (T6) is coupled to the n-1th stage scanning signal line (Gn-1), and the first source and drain of the sixth transistor (T6) are coupled to the forward control signal (UD); The gate of the seventh transistor (T7) is coupled to the n+1th stage scanning signal line (Gn+1), and the second source and drain of the seventh transistor (T7) are coupled to the reverse control signal (DU).

8. A GOA circuit for bidirectional scanning according to any one of claims 6 or 7, characterized in that: When the GOA circuit is scanning in the forward direction, the forward control signal (UD) is at a high potential, and the reverse scanning control signal (DU) is at a low potential; When the GOA circuit is scanning in the reverse direction, the forward control signal (UD) is at a low potential, and the reverse scanning signal (DU) is at a high potential.

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