DRAM read-write time sequence adjusting circuit and DRAM

Abstract

The embodiment of the invention provides a DRAM (Dynamic Random Access Memory) read-write time sequence adjusting circuit and a DRAM. The DRAM read-write time sequence adjusting circuit comprises a test mode control signal generating module, a time delay module and an adjusting module, the test mode control signal generation module is used for acquiring a test coding signal corresponding to the control signal and generating a test mode control signal corresponding to the control signal according to the test coding signal when a coding value of a target coding bit of the test coding signal is a preset coding value, and the control signal is the control signal which makes a read-write time sequence error in the DRAM; the time delay module receives the control signal, delays the control signal for a preset time length and then generates a time delay control signal; the adjusting module is used for generating a target control signal according to the test mode control signal, the control signal and the delay control signal, and the pulse width of the target control signal is larger than or smaller than that of the control signal. Therefore, the time sequence of the DRAM read-write process meets the specified time sequence, and errors of read-write data of the storage unit are avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technology and related technical fields, and in particular, to a DRAM read / write timing adjustment circuit and a DRAM. Background Art

[0002] DRAM (Dynamic Random Access Memory) is an internal memory that includes one or more memory arrays. Each memory array consists of M×N memory cells. Each memory cell is located at the intersection of WL (Word Line) and BL (Bit Line) and is used to store data. As the size of DRAM chips continues to shrink, the failure rate caused by reading and writing memory cells is gradually increasing, which in turn affects the yield of DRAM memory chips.

[0003] When the timing of the DRAM reading and writing process does not meet the requirements, the read and write data of the storage unit may be erroneous. These failed storage units may cause the chip to fail, thereby reducing the chip yield. Summary of the invention

[0004] The embodiments described herein provide a DRAM read / write timing adjustment circuit and a DRAM, so that the timing of the DRAM read / write process meets the specified timing, thereby avoiding errors in the read / write data of the storage unit.

[0005] In a first aspect, according to the content of the present disclosure, a DRAM read / write timing adjustment circuit is provided, comprising: a test mode control signal generation module, a delay module and an adjustment module; The test mode control signal generating module is configured to obtain a test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal according to the test coding signal, wherein the control signal is a control signal that causes a read and write timing error in the DRAM; The delay module is configured to receive a control signal and generate a delayed control signal after delaying the control signal for a preset time length; The adjustment module is configured to generate a target control signal according to the test mode control signal, the control signal and the delay control signal, wherein a pulse width of the target control signal is greater than or less than a pulse width of the control signal.

[0006] In some embodiments of the present disclosure, the test mode control signal generating module includes a test mode determining unit, a target test code signal generating unit and a test mode control signal generating unit; The test mode determination unit is configured to obtain a coding value of a target coding bit of the test coding signal, and generate a first test signal to the target test coding signal generation unit when the coding value of the target coding bit of the test coding signal is the same as a preset coding value; The target test code signal generating unit is configured to invert the test code signal according to the first test signal to obtain a target test code signal; The test mode control signal generating unit is configured to generate a test mode control signal according to the target test code signal.

[0007] In some embodiments of the present disclosure, the test mode determination unit includes a first latch, a data input terminal of the first latch receives a coding value of a target coding bit of the test coding signal, an enable terminal of the first latch receives an enable signal, and a data output terminal of the first latch outputs a test signal.

[0008] In some embodiments of the present disclosure, the target test coding signal generating unit includes a first inverter and a first NOR gate, the input end of the first inverter receives a test signal, the output end of the first inverter is electrically connected to the first input end of the first NOR gate, the second input end of the first NOR gate receives the test coding signal, and the output end of the first NOR gate outputs the target test coding signal.

[0009] In some embodiments of the present disclosure, the test mode control signal generating unit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and a second latch, wherein the first input end of the first AND gate receives the encoding value of the eleventh encoding bit of the target test encoding signal, the second input end of the first AND gate receives the encoding value of the tenth encoding bit of the target test encoding signal, the first input end of the second AND gate receives the encoding value of the ninth encoding bit of the target test encoding signal, the second input end of the second AND gate receives the encoding value of the eighth encoding bit of the target test encoding signal, the first input end of the third AND gate receives the encoding value of the sixth encoding bit of the target test encoding signal, the second input end of the third AND gate receives the encoding value of the fifth encoding bit of the target test encoding signal, and the output end of the first AND gate is connected to the first input end of the fourth AND gate. The output end of the second AND gate is electrically connected to the second input end of the fourth AND gate, the output end of the fourth AND gate is electrically connected to the first input end of the fifth AND gate, the output end of the third AND gate is electrically connected to the second input end of the fifth AND gate, the output end of the fifth AND gate is electrically connected to the first input end of the sixth AND gate, the second input end of the sixth AND gate receives the code value of the twelfth code bit of the target test code signal, the output end of the sixth AND gate is electrically connected to the first input end of the seventh AND gate, the second input end of the seventh AND gate receives the code value of the fourth code bit of the target test code signal, the output end of the seventh AND gate is electrically connected to the enable end of the second latch, the data input end of the second latch receives the code values ​​of the zeroth code bit to the third code bit of the target test code signal, and the data output end of the second latch outputs a test mode control signal.

[0010] In some embodiments of the present disclosure, the adjustment module includes an eighth AND gate and a second NOR gate, the first input end of the eighth AND gate receives the test mode control signal, the second input end of the eighth AND gate receives the delay control signal, the output end of the eighth AND gate is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the control signal, and the output end of the second NOR gate outputs the target control signal.

[0011] In some embodiments of the present disclosure, the adjustment module includes a second inverter, an OR gate and a NAND gate, the input end of the second inverter receives the test mode control signal, the output end of the second inverter is electrically connected to the first input end of the OR gate, the second input end of the OR gate receives the delay control signal, the output end of the OR gate is electrically connected to the first input end of the NAND gate, the second input end of the NAND gate receives the control signal, and the output end of the NAND gate outputs the target control signal.

[0012] In some embodiments of the present disclosure, the test mode control signal generating module further includes a test mode control signal inverting unit and an XOR unit; The test mode control signal inversion unit is configured to generate an inverse test mode control signal opposite to the test mode control signal according to the test mode control signal; The XOR unit is configured to generate a target test mode control signal according to the test mode control signal and the reverse test mode control signal.

[0013] In some embodiments of the present disclosure, the test mode control signal inverting unit includes at least a switch tube, a capacitor and a third inverter, the XOR unit includes an XOR gate, the first end of the switch tube is electrically connected to the power supply voltage node, the second end of the switch tube and the first end of the capacitor are electrically connected to the input end of the third inverter, the second end of the capacitor is electrically connected to the voltage node, the output end of the third inverter is electrically connected to the first input end of the XOR gate, the second input end of the XOR gate receives the test mode control signal, and the output end of the XOR gate outputs the target test mode control signal.

[0014] In a second aspect, according to the content of the present disclosure, a DRAM is provided, comprising the circuit described in any one of the first aspect.

[0015] The DRAM read / write timing adjustment circuit and DRAM provided by the embodiment of the present disclosure, after the DRAM determines that a control signal of the control module causes the read / write data of the storage unit in the memory to be erroneous, the test mode control signal generation module first obtains the test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generates a test mode control signal to the adjustment module, and the delay module delays the control signal that causes the read / write timing of the DRAM to be erroneous for a preset time and then generates a delay control signal, through the delay control signal, the adjustment module can adjust the pulse width of the control signal after generating the test mode control signal, the adjustment module generates a target control signal according to the received test mode control signal, the control signal and the delay control signal, the generated target control signal has a narrower or wider pulse than the control signal, so that the timing of the control signal output by the control module to SA, WL, CSL, etc. is changed, so that the timing of the DRAM read / write process meets the specified timing, and the read / write data of the storage unit is avoided from being erroneous. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein: Figure 1It is a structural schematic diagram of a DRAM read-write timing adjustment circuit provided by an embodiment of the present disclosure; Figure 2 It is a structural schematic diagram of another DRAM read-write timing adjustment circuit provided by an embodiment of the present disclosure; Figure 3 is a circuit structure diagram of a test mode determination unit provided in an embodiment of the present disclosure; Figure 4 is a circuit structure diagram of a target test coding signal generating unit provided by an embodiment of the present disclosure; Figure 5 is a circuit structure diagram of a test mode control signal generating unit provided by an embodiment of the present disclosure; Fig. 6A is a schematic diagram of a circuit structure of an adjustment module provided in an embodiment of the present disclosure; Figure 6B is a timing diagram of a target control signal generated by an adjustment module provided in an embodiment of the present disclosure; Fig. 7A is a circuit structure diagram of another adjustment module provided in an embodiment of the present disclosure; Figure 7B is a timing diagram of a target control signal generated by another adjustment module provided in an embodiment of the present disclosure; Figure 8 It is a structural schematic diagram of another DRAM read-write timing adjustment circuit provided by an embodiment of the present disclosure; Fig. 9 It is a partial structural diagram of a test mode control signal generating module in a DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0019] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0020] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0021] Based on the problems existing in the prior art, the present disclosure provides a DRAM read / write timing adjustment circuit. Figure 1 is a structural diagram of a DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure, such as Figure 1 As shown, the DRAM read and write timing adjustment circuit includes: a test mode control signal generating module 10, a delay module 20 and an adjustment module 30; the test mode control signal generating module 10 is configured to obtain a test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal according to the test coding signal, and the control signal is a control signal that causes a read and write timing error in the DRAM; the delay module 20 is configured to receive the control signal, and generate a delay control signal after delaying the control signal for a preset time length; the adjustment module 30 is configured to generate a target control signal according to the test mode control signal, the control signal and the delay control signal.

[0022] Specifically, in DRAM, the control module outputs control signals to the sense amplifier (Sense Amp, SA), word line (WordLine, WL), switch signal line (Column Switch Line, CSL), etc. to realize the read and write control of DRAM. However, when the control signal timing output by the control module to SA, WL, CSL, etc. is incorrect, so that the timing of the memory read and write process does not meet the specified timing, the read and write data of the storage unit may be wrong. Based on the problems existing in the prior art, the DRAM read and write timing adjustment circuit provided in the embodiment of the present disclosure first obtains a test coding signal corresponding to the control signal, wherein the test coding signal corresponding to each control signal is stored in the DRAM.

[0023] After a control signal of the DRAM determination control module causes the read and write data of the storage unit in the DRAM to be erroneous, the test mode control signal generation module 10 first obtains the test coding signal corresponding to the control signal, and determines whether to generate the test mode control signal by comparing the coding value of the target coding bit of the test coding signal with the preset coding value. Specifically, when the coding value of the target coding bit of the test coding signal is the preset coding value, the test mode control signal is generated, and when the coding value of the target coding bit of the test coding signal is different from the preset coding value, the test mode control signal is not generated.

[0024] Among them, the preset encoding value is 1.

[0025] The delay module 20 generates a delay control signal after delaying the control signal that causes the read and write timing of the DRAM to be wrong for a preset period of time. By delaying the control signal that causes the read and write timing of the DRAM to be wrong to obtain the delay control signal, the adjustment module can adjust the pulse width of the control signal after generating the test mode control signal.

[0026] It should be noted that the delay module includes multiple delay devices, and the number of delay devices is related to the test mode control signal generated by the test mode control signal generating module. Therefore, under different test mode control signals, the delay control signal generated by the delay module is different.

[0027] The adjustment module 30 generates a target control signal according to the received test mode control signal, control signal and delay control signal. The generated target control signal is narrower or wider than the control signal pulse, so that the timing of the control signal output by the control module to SA, WL, CSL, etc. is changed, so that the timing of the DRAM read and write process meets the specified timing, avoiding errors in the read and write data of the storage unit.

[0028] The DRAM read / write timing adjustment circuit provided by the embodiment of the present disclosure, after the DRAM determines that a control signal of the control module causes the read / write data of the storage unit in the memory to be erroneous, firstly, the test mode control signal generation module obtains the test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generates a test mode control signal to the adjustment module, and the delay module delays the control signal that causes the read / write timing error of the DRAM for a preset time length and then generates a delay control signal, through the delay control signal, the adjustment module can adjust the pulse width of the control signal after generating the test mode control signal, and the adjustment module generates a target control signal according to the received test mode control signal, the control signal and the delay control signal, and the generated target control signal has a narrower or wider pulse than the control signal, so that the timing of the control signal output by the control module to SA, WL, CSL, etc. is changed, so that the timing of the DRAM read / write process meets the specified timing, and the read / write data of the storage unit is avoided.

[0029] Based on the above embodiments, Figure 2 is a schematic diagram of the structure of another DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure, such as Figure 2 As shown, the test mode control signal generating module 10 includes a test mode determining unit 11, a target test coding signal generating unit 12 and a test mode control signal generating unit 13; the test mode determining unit 11 is configured to obtain the coding value of the target coding bit of the test coding signal, and when the coding value of the target coding bit of the test coding signal is the same as the preset coding value, generate a first test signal to the target test coding signal generating unit; the target test coding signal generating unit 12 is configured to invert the test coding signal according to the first test signal to obtain a target test coding signal; the test mode control signal generating unit 13 is configured to generate a test mode control signal according to the target test coding signal.

[0030] Specifically, the test mode determination unit of the test mode control signal generating module generates a test signal by obtaining the relationship between the coding value of the target coding bit of the test coding signal and the preset coding value. When the coding value of the target coding bit of the test coding signal is the same as the preset coding value, a first test signal is generated; when the coding value of the target coding bit of the test coding signal is different from the preset coding value, a second test signal is generated.

[0031] It should be noted that when the target coding value of the test coding signal is the same as the preset coding value, the control signal corresponding to the test coding signal is characterized so that the read and write process of the DRAM does not meet the timing requirements, and when the target coding value of the test coding signal is different from the preset coding value, the control signal corresponding to the test coding signal is characterized so that the read and write process of the DRAM meets the timing requirements. Therefore, when the coding value of the target coding bit of the test coding signal is the same as the preset coding value, a first test signal is generated to the target test coding signal generating unit, so that when the target test coding signal generating unit receives the first test signal, it selects the input test coding signal and inverts the test coding signal to obtain the target test coding signal.

[0032] Specifically, when the target test coding signal generating unit 12 receives the first test signal, the target test coding signal generating unit 12 inverts the test coding signal to obtain the target test coding signal; when the target test coding signal generating unit receives the second test signal, the target test coding signal assigns zero to the coding value of each coding bit of the test coding signal and then outputs it.

[0033] Specifically, after receiving the target test coding signal, the test mode control signal generating unit 13 processes the coding value of each coding bit of the target test coding signal to determine whether to generate the test mode control signal.

[0034] In a specific embodiment, in combination with Figure 3 The test mode determination unit 11 includes a first latch SR1, a data input terminal of the first latch SR1 receives a coding value of a target coding bit of a test coding signal, an enable terminal of the first latch SR1 receives an enable signal, and a data output terminal of the first latch SR1 outputs a test signal.

[0035] like Figure 3 As shown, the data input end of the first latch SR1 receives the code value of the target code bit of the test code signal, and the enable end of the first latch SR1 receives the enable signal. When the enable end of the first latch SR1 is in the enable state, if the data input end of the first latch SR1 is 1, the first latch SR1 will store the code value of the target code bit of the test code signal input from the current data input end to the data output end when the rising edge of the next clock pulse arrives. That is, if the code value of the target code bit of the test code signal is 1, the first latch outputs the first test signal (1) to the target test code signal generation unit, and if the code value of the target code bit of the test code signal is 0, the first latch outputs the second test signal (0) to the target test code signal generation unit.

[0036] In the embodiment of the present disclosure, the test coding signal is Address<12:0>, and the target coding bit of the test coding signal is the seventh bit, that is, Address<12:0>. <7> , if Address <7> =1, then the first test signal Test generated by the test mode determination unit is 1. If Address <7> =0, the second test signal Test generated by the test mode determination unit is 0.

[0037] like Figure 4 As shown, the target test coding signal generating unit 12 includes a first inverter F1 and a first NOR gate NOR1, the input end of the first inverter F1 receives the test signal Test, the output end of the first inverter F1 is electrically connected to the first input end of the first NOR gate NOR1, the second input end of the first NOR gate NOR1 receives the test coding signal Address<12:0>, and the output end of the first NOR gate NOR1 outputs the target test coding signal TRA<12:0>.

[0038] Specifically, the first inverter F1 receives the test signal Test output by the first latch SR1. If the test signal output by the first latch SR1 is the first test signal (1), the first inverter F1 outputs a low level (0). If the test signal output by the first latch SR1 is the second test signal (0), the first inverter F1 outputs a high level (1). The first input end of the first NOR gate NOR1 receives the level signal output by the first inverter F1. The second input end of the first NOR gate NOR1 receives the test coding signal Address. <12:0>, when the level signal output by the first inverter F1 is a low level (0), the first NOR gate NOR1 inverts the code value of each code bit of the test code signal Address<12:0> received at the second input terminal and outputs the target test code signal TRA<12:0>. When the level signal output by the first inverter F1 is a high level (1), the first NOR gate NOR1 assigns zero to the code value of each code bit of the test code signal received at the second input terminal and outputs the target test code signal TRA<12:0>, that is, the target test code signal is not generated.

[0039] like Figure 5As shown, the test mode control signal generating unit 13 includes a first AND gate A1, a second AND gate A2, a third AND gate A3, a fourth AND gate A4, a fifth AND gate A5, a sixth AND gate A6, a seventh AND gate and a second latch SR2, and a first input terminal of the first AND gate A1 receives the code value TRA of the eleventh code bit of the target test code signal <11> The second input terminal of the first AND gate A1 receives the code value TRA of the tenth code bit of the target test code signal <10> The first input terminal of the second AND gate A2 receives the code value TRA of the ninth code bit of the target test code signal <9> The second input terminal of the second AND gate A2 receives the code value TRA of the eighth code bit of the target test code signal <8> The first input terminal of the third AND gate A3 receives the code value TRA of the sixth code bit of the target test code signal <6> The second input terminal of the third AND gate A3 receives the encoding value TRA of the fifth encoding bit of the target test encoding signal <5> , the output end of the first AND gate A1 is electrically connected to the first input end of the fourth AND gate A4, the output end of the second AND gate A2 is electrically connected to the second input end of the fourth AND gate A4, the output end of the fourth AND gate A4 is electrically connected to the first input end of the fifth AND gate A5, the output end of the third AND gate A3 is electrically connected to the second input end of the fifth AND gate A5, the output end of the fifth AND gate A5 is electrically connected to the first input end of the sixth AND gate A6, and the second input end of the sixth AND gate A6 receives the code value TRA of the twelfth code bit of the target test code signal <12> The output end of the sixth AND gate A6 is electrically connected to the first input end of the seventh AND gate A7, and the second input end of the seventh AND gate A7 receives the encoding value TRA of the fourth encoding bit of the target test encoding signal <4> The output end of the seventh AND gate A7 is electrically connected to the enable end of the second latch SR2, the data input end of the second latch SR2 receives the coding value TRA<3:0> of the zeroth coding bit to the third coding bit of the target test coding signal, and the data output end of the second latch SR2 outputs the test mode control signal Test mode code.

[0040] Specifically, Figure 5 As shown, when the coding value of the twelfth coding bit, the coding value of the eleventh coding bit, the coding value of the tenth coding bit, the coding value of the ninth coding bit, the coding value of the eighth coding bit, the coding value of the sixth coding bit, the coding value of the fifth coding bit and the coding value of the fourth coding bit of the target test coding signal are 1, the seventh AND gate outputs a high level to the second latch, the second latch is enabled, and the second latch outputs a test mode control signal according to the coding values ​​of the zeroth coding bit to the third coding bit of the target test coding signal received at the data input terminal.

[0041] Exemplarily, if the seventh AND gate outputs a high level to the second latch, and the coding value of the zeroth coding bit to the third coding bit of the target test coding signal received at the data input end of the second latch is 0001, the test mode control signal output by the second latch is 1 (i.e., a high level); if the seventh AND gate outputs a high level to the second latch, and the coding value of the zeroth coding bit to the third coding bit of the target test coding signal received at the data input end of the second latch is 0010, the test mode control signal output by the second latch is 2 (i.e., a high level); if the seventh AND gate outputs a high level to the second latch, and the coding value of the zeroth coding bit to the third coding bit of the target test coding signal received at the data input end of the second latch is 0100, the test mode control signal output by the second latch is 4 (i.e., a high level); if the seventh AND gate outputs a high level to the second latch, and the coding value of the zeroth coding bit to the third coding bit of the target test coding signal received at the data input end of the second latch is 1000, the test mode control signal output by the second latch is 8 (i.e., a high level). If the seventh AND gate outputs a high level to the second latch, and the code value of the zeroth code bit to the third code bit of the target test code signal received at the data input end of the second latch is 0000, the test mode control signal output by the second latch is 0 (that is, a low level). In addition, when the seventh AND gate outputs a low level to the second latch, no matter what the code value of the zeroth code bit to the third code bit of the target test code signal received at the data input end of the second latch is, the test mode control signal output by the second latch is 0 (that is, a low level).

[0042] It should be noted that different control signals correspond to different test mode control signals, and different test mode control signals have different magnitudes of pulse width adjustment for the control signal.

[0043] As a specific implementable method, combined with Fig. 6A and Figure 6B The adjustment module 30 includes an eighth AND gate A8 and a second NOR gate NOR2, the first input end of the eighth AND gate A8 receives the test mode control signal Test mode code, the second input end of the eighth AND gate A8 receives the delay control signal Dly Control Signal, the output end of the eighth AND gate A8 is electrically connected to the first input end of the second NOR gate NOR2, the second input end of the second NOR gate NOR2 receives the control signal ControlSignal, and the output end of the second NOR gate NOR2 outputs the target control signal Output.

[0044] Combination Fig. 6A and Figure 6BFirst, the eighth AND gate receives the test mode control signal and the delay control signal. The eighth AND gate takes the intersection of the test mode control signal and the delay control signal and outputs it to the second NOR gate. The second NOR gate takes the intersection of the test mode control signal and the delay control signal with the control signal and outputs the target control signal, thereby achieving an increase in the pulse width of the output target control signal compared to the control signal.

[0045] As another specific implementation method, combining Fig. 7A and Figure 7B The adjustment module 30 includes a second inverter F2, an OR gate OR and a NAND gate NA, the input end of the second inverter F2 receives the test mode control signal Test mode code, the output end of the second inverter F2 is electrically connected to the first input end of the OR gate OR, the second input end of the OR gate OR receives the delay control signal Dly Control Signal, the output end of the OR gate OR is electrically connected to the first input end of the NAND gate NA, the second input end of the NAND gate NA receives the control signal Control Signal, and the output end of the NAND gate NA outputs the target control signal Output.

[0046] Combination Fig. 7A and Figure 7B The second inverter inverts the test mode control signal and outputs it to the OR gate. Specifically, when the test mode control signal is at a high level, the second inverter outputs a low level to the first input terminal of the OR gate. Since the first input terminal of the OR gate is at a low level, the OR gate outputs the delayed control signal input at the second input terminal. The NAND gate intersects the delayed control signal and the control signal and then inverts them before outputting the target control signal, thereby achieving a reduction in the pulse width of the output target control signal compared to the control signal.

[0047] Based on the above embodiments, Figure 8 is a structural diagram of another DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure, such as Figure 8 As shown, the test mode control signal generating module also includes a test mode control signal inverting unit 14 and an XOR unit 15; the test mode control signal inverting unit 14 is configured to generate a reverse test mode control signal opposite to the test mode control signal according to the test mode control signal; the XOR unit 15 is configured to generate a target test mode control signal according to the test mode control signal and the reverse test mode control signal.

[0048] Among them, Fig. 9As shown, the test mode control signal inverting unit 14 at least includes a switch tube M, a capacitor C and a third inverter F3, the XOR unit includes an XOR gate XOR, the first end of the switch tube M is electrically connected to the power supply voltage node, the second end of the switch tube M and the first end of the capacitor C are electrically connected to the input end of the third inverter F3, the second end of the capacitor C is electrically connected to the voltage node, the output end of the third inverter F3 is electrically connected to the first input end of the XOR gate XOR, the second input end of the XOR gate XOR receives the test mode control signal Test mode code, and the output end of the XOR gate XOR outputs the target test mode control signal Tar Test mode code.

[0049] In the above embodiment, the adjustment of the DRAM read and write timing when the DRAM is in the test mode is exemplified. In order to adjust the DRAM read and write timing when the DRAM is in the normal working mode, at this time, by setting the test mode control signal generation module to also include a test mode control signal inversion unit and an XOR unit, first, the test mode control signal inversion unit receives the test mode control signal. When the test mode control signal is at a high level, the reverse test mode control signal output by the test mode control signal inversion unit is at a low level. When the test mode control signal is at a low level, the reverse test mode control signal output by the test mode control signal inversion unit is at a high level. At this time, the XOR unit receives the test mode control signal and the reverse test mode control signal respectively. Regardless of whether the test mode control signal is at a high level or a low level, the XOR unit will output a high level, that is, the target test mode control signal generated by the XOR unit is a high level, so that when the coding value of the target coding bit of the test coding signal is different from the preset coding value (that is, the DRAM is in the normal working mode), the DRAM read and write timing can also be adjusted.

[0050] As a specific implementation method, when the test mode control signal is at a high level, a control signal is output to the switch tube to control the switch tube to be turned on, the input end of the third inverter receives a high level, the third inverter outputs a low level to the XOR gate, the first input end of the XOR gate receives a low level, the second input end of the XOR gate receives a high level, and the target test mode control signal output by the XOR gate is a high level; when the test mode control signal is at a low level, a high voltage is connected to the second end of the capacitor to break down the capacitor, the input end of the third inverter receives a low level, the third inverter outputs a high level to the XOR gate, the first input end of the XOR gate receives a high level, the second input end of the XOR gate receives a low level, and the target test mode control signal output by the XOR gate is a high level. It is achieved that regardless of whether the coding value of the target coding bit of the test coding signal is the same as the preset coding value (that is, the DRAM normal working mode or the test working mode), the DRAM read and write timing can be adjusted.

[0051] An embodiment of the present disclosure further provides a DRAM, which includes the DRAM read and write timing adjustment circuit provided by the embodiment of the present disclosure and has the beneficial effects described in any of the above embodiments.

[0052] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0053] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A DRAM read / write timing adjustment circuit, characterized in that: include: Test mode control signal generation module, delay module and adjustment module; The test mode control signal generating module is configured to obtain a test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal according to the test coding signal, wherein the control signal is a control signal that causes a read and write timing error in the DRAM; The delay module is configured to receive a control signal and generate a delayed control signal after delaying the control signal for a preset time length; The adjustment module is configured to generate a target control signal according to the test mode control signal, the control signal and the delay control signal, wherein a pulse width of the target control signal is greater than or less than a pulse width of the control signal.

2. The circuit according to claim 1, characterized in that The test mode control signal generating module includes a test mode determining unit, a target test code signal generating unit and a test mode control signal generating unit; The test mode determination unit is configured to obtain a coding value of a target coding bit of the test coding signal, and generate a first test signal to the target test coding signal generation unit when the coding value of the target coding bit of the test coding signal is the same as a preset coding value; The target test code signal generating unit is configured to invert the test code signal according to the first test signal to obtain a target test code signal; The test mode control signal generating unit is configured to generate a test mode control signal according to the target test code signal.

3. The circuit according to claim 2, characterized in that The test mode determination unit includes a first latch, a data input terminal of the first latch receives a coding value of a target coding bit of the test coding signal, an enable terminal of the first latch receives an enable signal, and a data output terminal of the first latch outputs a test signal.

4. The circuit according to claim 2, characterized in that The target test code signal generating unit includes a first inverter and a first NOR gate, the input end of the first inverter receives a test signal, the output end of the first inverter is electrically connected to the first input end of the first NOR gate, the second input end of the first NOR gate receives the test code signal, and the output end of the first NOR gate outputs a target test code signal.

5. The circuit according to claim 2, characterized in that The test mode control signal generating unit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and a second latch, wherein a first input end of the first AND gate receives a code value of an eleventh code bit of the target test code signal, a second input end of the first AND gate receives a code value of a tenth code bit of the target test code signal, a first input end of the second AND gate receives a code value of a ninth code bit of the target test code signal, a second input end of the second AND gate receives a code value of an eighth code bit of the target test code signal, a first input end of the third AND gate receives a code value of a sixth code bit of the target test code signal, a second input end of the third AND gate receives a code value of a fifth code bit of the target test code signal, an output end of the first AND gate is electrically connected to a first input end of the fourth AND gate, and The output end of the second AND gate is electrically connected to the second input end of the fourth AND gate, the output end of the fourth AND gate is electrically connected to the first input end of the fifth AND gate, the output end of the third AND gate is electrically connected to the second input end of the fifth AND gate, the output end of the fifth AND gate is electrically connected to the first input end of the sixth AND gate, the second input end of the sixth AND gate receives the coding value of the twelfth coding bit of the target test coding signal, the output end of the sixth AND gate is electrically connected to the first input end of the seventh AND gate, the second input end of the seventh AND gate receives the coding value of the fourth coding bit of the target test coding signal, the output end of the seventh AND gate is electrically connected to the enable end of the second latch, the data input end of the second latch receives the coding values ​​of the zeroth coding bit to the third coding bit of the target test coding signal, and the data output end of the second latch outputs a test mode control signal.

6. The circuit according to claim 1, characterized in that The adjustment module includes an eighth AND gate and a second NOR gate, the first input end of the eighth AND gate receives the test mode control signal, the second input end of the eighth AND gate receives the delay control signal, the output end of the eighth AND gate is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the control signal, and the output end of the second NOR gate outputs the target control signal.

7. The circuit according to claim 1, characterized in that The adjustment module includes a second inverter, an OR gate and a NAND gate, the input end of the second inverter receives the test mode control signal, the output end of the second inverter is electrically connected to the first input end of the OR gate, the second input end of the OR gate receives the delay control signal, the output end of the OR gate is electrically connected to the first input end of the NAND gate, the second input end of the NAND gate receives the control signal, and the output end of the NAND gate outputs the target control signal.

8. The circuit according to claim 1, characterized in that The test mode control signal generating module further includes a test mode control signal inverting unit and an XOR unit; The test mode control signal inversion unit is configured to generate an inverse test mode control signal opposite to the test mode control signal according to the test mode control signal; The XOR unit is configured to generate a target test mode control signal according to the test mode control signal and the reverse test mode control signal.

9. The circuit according to claim 8, characterized in that The test mode control signal inversion unit at least includes a switch tube, a capacitor and a third inverter, the XOR unit includes an XOR gate, the first end of the switch tube is electrically connected to the power supply voltage node, the second end of the switch tube and the first end of the capacitor are electrically connected to the input end of the third inverter, the second end of the capacitor is electrically connected to the voltage node, the output end of the third inverter is electrically connected to the first input end of the XOR gate, the second input end of the XOR gate receives the test mode control signal, and the output end of the XOR gate outputs the target test mode control signal.

10. A DRAM, characterized in that: The invention comprises the circuit described in any one of claims 1 to 9.

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