Memory module and memory

Abstract

The invention discloses a storage module and a memory. The storage module comprises a main storage unit and a reference storage unit, the main storage unit comprises a storage area used for storing data, and the storage area executes erasing operation under the control of a storage control circuit; the reference storage unit is used for following the erasing operation of the main storage unit, so that an electric signal of the reference storage unit is consistent with an electric signal of the main storage unit, and a reference signal is determined according to the electric signal after each erasing operation. The reference signal can be matched with real-time states such as the erasing frequency of the main storage unit in the storage module and / or the current electric signal, the accuracy of the determined reference signal is improved, and then the accuracy of data reading according to the reference signal can be improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a storage module and a memory. Background Art

[0002] The memory can store data 0 or 1, and the distinction between data 0 and 1 can be obtained by comparing the storage unit (cell) with the reference voltage or current. Taking the flash non-volatile memory as an example, if the current of the storage unit of data 1 (which can be recorded as cell 1) is about 20uA, and the current of the storage unit of data 0 (which can be recorded as cell 0) is about 5uA. Then the reference can be designed to be 12.5uA, so that the data 0 stored in cell 0 and the data 1 stored in cell 1 can be accurately read.

[0003] The inventors have found that in non-volatile memory, the characteristics of the storage unit will change with the increase of the number of erase and write times. The degradation of the storage unit characteristics caused by the increase of the number of erase and write times can be represented by the endurance characteristic of the memory, where the endurance characteristic is used to characterize the degree of performance loss corresponding to the repeated operation of the corresponding storage unit; taking flash as an example, the current of cell 1 is 20uA when it is used for the first time out of the factory. After 100,000 erase and write times, the current of cell 1 may drop to 10uA. If the reference benchmark is still 12.5uA at this time, the data stored in cell 1 will be read incorrectly; similarly, the current of cell 0 will also increase with the increase of the number of erase and write times.

[0004] In some memories, a fixed reference of a bandgap reference source (BGR) is used as a reference reference when reading data; in some other memories, an independent storage unit is configured, and the current of this storage unit is programmed to be a current reference parameter such as 12.5uA, and this reference storage unit current is used as a reference reference; the reference reference determined by the above scheme deviates from the actual state of at least some storage units in the memory after the number of erase and write times of the memory increases, which can easily affect the accuracy of the data reading operation of the storage unit. Summary of the invention

[0005] In view of this, the present application provides a storage module and a memory to solve the problem that the reference benchmark determined by the traditional solution deviates from the actual state of at least part of the storage modules in the memory after the number of memory erase and write times increases, thereby easily affecting the accuracy of the storage module data reading operation.

[0006] The present application provides a storage module, comprising a main storage unit and a reference storage unit;

[0007] The main storage unit includes a storage area for storing data, and the storage area performs an erase and write operation under the control of a storage control circuit;

[0008] The reference storage unit is used to follow the erase and write operations of the main storage unit, so that the electrical signal of the reference storage unit is consistent with the electrical signal of the main storage unit, and the reference signal is determined according to the electrical signal after each erase and write operation.

[0009] Optionally, the erase operation includes a data write 1 operation; the reference storage unit includes a first storage area; the first storage area is used to follow the data write 1 operation for the main storage unit, and after each execution of the data write 1 operation, its electrical signal is consistent with the electrical signal after the main storage unit performs the same operation.

[0010] Optionally, the reference storage unit also includes a first current acquisition unit; the input end of the first current acquisition unit is connected to the output end of the first storage area, and the output end is used to output the reference signal, which is used to determine the reference signal according to a first preset ratio of the electrical signal of the first storage area.

[0011] Optionally, the first current acquisition unit includes a first current mirror; the first current mirror includes a first MOS tube and a second MOS tube; the source of the first MOS tube is used to access a preset voltage, the gate is connected to the gate of the second MOS tube, and the drain serves as the input end of the first current acquisition unit, and is used to access the current output by the first storage area; the source of the second MOS tube is used to access the preset voltage, and the drain serves as the output end of the first current acquisition unit, and is used to access the reference signal.

[0012] Optionally, the reference storage unit includes a second storage area and a third storage area; the second storage area is used to follow the data write 1 operation of the main storage unit, and after each data write 1 operation is performed, its electrical signal is consistent with the electrical signal of the main storage unit after performing the same operation; the third storage area is used to follow the data write 0 operation of the main storage unit, and after each data write 0 operation is performed, its electrical signal is consistent with the electrical signal of the main storage unit after performing the same operation.

[0013] Optionally, the reference storage unit also includes a second current acquisition unit; a first input end of the second current acquisition unit is connected to an output end of the second storage area, a second input end is connected to an output end of the third storage area, and an output end is used to output the reference signal, and is used to determine the reference signal based on the sum of the electrical signals corresponding to the second storage area and the third storage area respectively.

[0014] Optionally, the second current acquisition unit includes an adder and a second current mirror; the first input end of the adder serves as the first input end of the second current acquisition unit, connected to the output end of the second storage area, the second input end serves as the second input end of the second current acquisition unit, connected to the output end of the third storage area, and the output end is connected to the input end of the second current mirror; the output end of the second current mirror is used to output a reference signal.

[0015] Optionally, the main storage unit and the reference storage unit perform various operations synchronously.

[0016] The present application also provides a memory, which includes a plurality of any of the above-mentioned storage modules.

[0017] Optionally, the above-mentioned memory also includes a storage control circuit; the storage control circuit is used to obtain a reference signal output by the reference storage unit, detect the operating current of the main storage unit, and perform a data reading operation according to the operating current and the reference signal.

[0018] In the above-mentioned storage module and memory of the present application, the reference storage unit can follow the main storage unit to perform erase and write operations, so that the reference storage unit can follow the endurance characteristics of the main storage unit, and the electrical signal after the reference storage unit performs the erase and write operation is consistent with the electrical signal after the main storage unit performs the corresponding erase and write operation. Therefore, the reference signal can be determined in real time according to the electrical signal after each erase and write operation is performed, so that the reference signal matches the real-time status such as the erase and write times and / or the current electrical signal of the main storage unit in the storage module, thereby improving the accuracy of the determined reference signal, and further improving the accuracy of data reading based on the reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a schematic diagram of the storage module structure of an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of the storage module structure of another embodiment of the present application;

[0022] Figure 3 is a schematic diagram of the storage module structure of another embodiment of the present application;

[0023] Figure 4 is a schematic diagram of the first current mirror structure of an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of the storage module structure of another embodiment of the present application;

[0025] Figure 6 is a schematic diagram of the storage module structure of another embodiment of the present application;

[0026] Figure 7 Schematic diagram of a reference memory cell structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0028] In a first aspect, the present application provides a storage module, which can be a storage array block of a non-volatile memory, which can be used as an erase unit. Figure 1 As shown, the above-mentioned storage module includes a main storage unit 100 and a reference storage unit 200. The main storage unit 100 and the reference storage unit 200 can be mounted on the same control line, wherein the control line can include a word line; the main storage unit 100 and the reference storage unit 200 can also be mounted on different control lines respectively, for example, the main storage unit 100 can be mounted on the first word line WL1, and the reference storage unit 200 can be mounted on the second word line WL2, and the first word line WL1 and the second word line WL2 are turned on at the same time; therefore, each step of operation and each working state of the reference storage unit 200 are kept consistent with the main storage unit 100.

[0029] The main memory unit 100 includes a storage area for storing data, which can be controlled by a storage control circuit ( Figure 1 The erase and write operation is performed under the control of the memory area (not shown). Optionally, the storage area can be used to store data such as 1 or 0, and can also be used for data in other forms (such as binary sequences, etc.).

[0030] The reference memory unit 200 is used to follow the erase and write operation of the main memory unit 100, so that the electrical signal of the reference memory unit 200 is consistent with the electrical signal of the main memory unit 100, and the reference signal is determined according to the electrical signal after each erase and write operation. Optionally, the electrical signal may include a signal such as a current, and accordingly, the reference signal may include a reference current.

[0031] Specifically, the erase and write operation may include a data write 1 operation and a data write 0 operation, etc. The main storage unit 100 may include at least one storage area for performing erase and write operations, so that the reference storage unit 200 can follow at least one of the data write 1 operation and the data write 0 operation in the main storage unit 100, thereby following the endurance characteristics of the storage area of ​​the main storage unit 100, so that the electrical signal of the corresponding storage area in the reference storage unit 200 is consistent with the electrical signal after the main storage unit 100 performs the corresponding erase and write operation. The reference storage unit 200 is also used to determine a reference signal such as a reference current according to the electrical signal after each erase and write operation is performed, so that the reference signal matches the real-time status such as the erase and write times and / or the current electrical signal of the main storage unit 100 in the storage module, improves the accuracy of the determined reference signal, and thus improves the accuracy of data reading based on the reference signal.

[0032] In the above-mentioned storage module, the reference storage unit 200 can follow the main storage unit 100 to perform erase and write operations, so that the reference storage unit 200 can follow the endurance characteristics of the main storage unit 100, and the electrical signal after the reference storage unit 200 performs the erase and write operation is consistent with the electrical signal after the main storage unit 100 performs the corresponding erase and write operation. Therefore, the reference signal can be determined in real time according to the electrical signal after each erase and write operation is performed, so that the reference signal matches the real-time status such as the erase and write times and / or the current electrical signal of the main storage unit 100 in the storage module, thereby improving the accuracy of the determined reference signal, and then the accuracy of data reading based on the reference signal can be improved.

[0033] In some embodiments, the erase operation includes a data write 1 operation. Figure 2 As shown, the reference memory unit 200 includes a first memory area 211. The first memory area 211 is used to follow the data write 1 operation of the main memory unit 100, thereby following the endurance characteristics generated by each data write 1 operation performed by the main memory unit 100, so that after the main memory unit 100 performs each data write 1 operation, the electrical signal of the first memory area 211 remains consistent with the electrical signal used for the main memory unit 100.

[0034] In some examples, reference Figure 3 As shown, the reference storage unit 200 further includes a first current acquisition unit 212. The input end of the first current acquisition unit 212 is connected to the output end of the first storage area 211, and the output end is used to output the reference signal; the first current acquisition unit 212 is used to determine the reference signal according to a first preset ratio of the electrical signal of the first storage area 211.

[0035] Optionally, the electrical signal includes a current signal, and the reference signal includes a reference current. The first preset ratio can be set according to factors such as current characteristics after the main storage unit 100 performs various operations; for example, the first preset ratio can be set to a value such as 60%. When the current of cell 1 corresponding to the data write 1 operation in the main storage unit 100 is 20uA (such as when the main storage unit 100 just starts working), the current output from the first storage area 211 to the first current acquisition unit 212 is 20uA, and the reference current output by the first current acquisition unit 212 is 20uA*60%=12uA; when the current of cell 1 in the main storage unit 100 is 10uA (such as after the main storage unit 100 performs 100,000 erases and writes), the current output from the first storage area 211 to the first current acquisition unit 212 is 10uA, and the reference current output by the first current acquisition unit 212 is 10uA*60%=6uA.

[0036] In this embodiment, the first storage area 211 follows the data write 1 operation of the main storage unit 100, so that the electrical signal of the first storage area 211 is consistent with the electrical signal of the main storage unit 100 after each data write 1 operation is performed, so that the first current acquisition unit 212 can accurately determine the reference signal according to the first preset ratio of the electrical signal of the first storage area 211. The structure used in the process of determining the reference signal is simple, and on the basis of real-time adjustment of the reference signal, the structure of the reference storage unit 200 can be simplified as much as possible.

[0037] Specifically, the first current acquisition unit 212 can be implemented by using a current processing structure such as a current mirror; for example, Figure 4 As shown, the first current acquisition unit 212 includes a first current mirror; the first current mirror includes a first MOS transistor P1 and a second MOS transistor P2; optionally, the first MOS transistor P1 and the second MOS transistor P2 can be PMOS transistors respectively. The source of the first MOS transistor P1 is used to access a preset voltage, the gate is connected to the gate of the second MOS transistor P2, and the drain is used as the input end of the first current acquisition unit to access the current output by the first storage area 211; the source of the second MOS transistor P2 is used to access the preset voltage, and the drain is used as the output end of the first current acquisition unit 212 to access the reference current.

[0038] Optionally, the sizes of the first MOS transistor P1 and the second MOS transistor P2 can be determined according to a first preset ratio so that the ratio of the current of the drain of the second MOS transistor P2 (i.e., the reference current) to the current of the drain of the first MOS transistor P1 (i.e., the current output by the first storage area 211) is the first preset ratio.

[0039] In some embodiments, reference Figure 5As shown, the reference memory cell 200 includes a second memory area 221 and a third memory area 222. The second memory area 221 is used to follow the data write 1 operation of the main memory cell 100, thereby following the endurance characteristics of the main memory cell 100 after performing the data write 1 operation, so that the electrical signal of the second memory area 221 is consistent with the electrical signal after following the main memory cell 100 after performing the data write 1 operation. The third memory area 222 is used to follow the data write 0 operation of the main memory cell 100, thereby following the endurance characteristics of the main memory cell 100 after performing the data write 1 operation, so that the electrical signal of the third memory area 222 is consistent with the electrical signal after following the main memory cell 100 after performing the data write 0 operation.

[0040] In some examples, reference Figure 6 As shown, the reference storage unit 200 also includes a second current acquisition unit 223; the first input end of the second current acquisition unit 223 is connected to the output end of the second storage area 221, the second input end is connected to the output end of the third storage area 222, and the output end is used to output a reference signal; the second current acquisition unit 223 is used to determine the reference signal according to the sum of the electrical signals corresponding to the second storage area 221 and the third storage area 222, so that the reference signal is based on the electrical signals corresponding to the second storage area 221 and the third storage area 222, that is, based on the real-time currents corresponding to cell 1 and cell 0 in the main storage unit 100, respectively, which can ensure the accuracy of the determined reference signal.

[0041] Optionally, the second current acquisition unit 223 may be implemented by a current mirror structure, for example, it may sequentially implement an addition function and a reference signal output function through a plurality of current mirror structures.

[0042] Optionally, the electrical signal is a current signal, and the reference signal includes a reference current. Figure 7 As shown, the second current acquisition unit 223 includes an adder 2231 and a second current mirror 2232; the first input end of the adder 2231 serves as the first input end of the second current acquisition unit 223, connected to the output end of the second storage area 221, the second input end serves as the second input end of the second current acquisition unit 223, connected to the output end of the third storage area 222, and the output end is connected to the input end of the second current mirror 2232; the output end of the second current mirror 2232 is used to output a reference current.

[0043] Specifically, the adder 2231 is used to sum the current parameters outputted from the second storage area 221 and the third storage area 222, and output the summed current to the second current mirror 2232. The second current mirror 2232 is used to output a reference current according to a second preset ratio of the summed current outputted from the adder 2231. Optionally, the second preset ratio can be set according to factors such as the current characteristics of each storage area in the main storage unit 100; for example, the second preset ratio can be set to a value such as 50%. When the current of cell 1 corresponding to the data write 1 operation in the main storage unit 100 is 20uA and the current of cell 0 corresponding to the data write 0 operation is 5uA (such as when the main storage unit 100 just starts to work), the current output from the second storage area 221 to the adder 2231 is 20uA, and the current output from the third storage area 222 to the adder 2231 is 5uA. At this time, the reference current output by the second current mirror 2232 is (20uA+5uA)*50%=12.5uA; when the current of cell 1 in the main storage unit 100 is 10uA, the current of cell 0 corresponding to the data write 0 operation is 5uA. 0 is 7uA (such as after the main storage unit 100 is erased and written 100,000 times), the current output from the second storage area 221 to the adder 2231 is 10uA, and the current output from the third storage area 222 to the adder 2231 is 7uA. At this time, the reference current output by the second current mirror 2232 is (10uA+7uA)*50%=8.5uA.

[0044] Optionally, the structure of the second current mirror 2232 may be the same as that of the first current mirror, and the second current mirror 2232 may also be implemented using other current mirror structures.

[0045] In some embodiments, the main memory unit 100 and the reference memory unit 200 perform various operations synchronously, so that the reference memory unit 200 does not consume extra time in the process of following the main memory unit 100 to perform the erase and write operation, and the writing environment of the two is consistent, which can make the following characteristics better.

[0046] In the above storage module, the reference storage unit 200 can follow the main storage unit 100 to perform erase and write operations, so that the reference storage unit 200 can follow the endurance characteristics of the main storage unit 100, and the electrical signal after the reference storage unit 200 performs the erase and write operation is consistent with the electrical signal after the main storage unit 100 performs the corresponding erase and write operation. Therefore, the reference signal can be determined in real time according to the electrical signal after each erase and write operation is performed, so that the reference signal matches the real-time status of the erase and write times and / or the current electrical signal of the main storage unit 100 in the storage module, thereby improving the accuracy of the determined reference signal, and then the accuracy of data reading based on the reference signal can be improved.

[0047] The second aspect of the present application provides a memory, which may be a non-volatile memory. Specifically, the memory includes a plurality of storage modules described in any of the above embodiments.

[0048] In some embodiments, the memory also includes a storage control circuit, which may also be referred to as a read control circuit, and the storage control circuit is respectively connected to a reference storage unit and a main storage unit; the storage control circuit is used to obtain a reference signal output by the reference storage unit, detect an operating current of the main storage unit, and perform a data read operation according to the operating current and the reference signal.

[0049] Optionally, the reference signal includes a reference current. The storage control circuit can obtain the reference current output by the reference storage unit, detect the operating current of the main storage unit, and perform a data reading operation according to the operating current and the reference current. Specifically, if the operating current of the main storage unit is greater than the reference current, data 1 is read out, and if the operating current of the main storage unit is less than the reference current, data 0 is read out.

[0050] In this embodiment, the reference current output by the reference storage unit matches the real-time status of the main storage unit such as the number of erase and write times and / or current current parameters, with high accuracy, making the data reading operation performed by the storage control circuit based on the reference current more accurate.

[0051] The inventors analyzed the performance of the above-mentioned memory, and took a non-volatile memory of a 64M (8K*8K) memory array as an example for explanation. The non-volatile memory can use a block (memory array block) as an erasing unit. The memory array block block can include a memory module, and a block can include 64 word lines (WLs). Therefore, the height of the reference memory cell in the non-volatile memory can be 8K / 64=128 word lines (WL) height. Each reference memory cell can have two storage areas (also called cells) on the WL corresponding to the reference memory cell, one storage area follows cell 1, and the other storage area follows data cell 0. Considering that the array corresponding to the reference memory cell cannot be too small, a 128*32 array can be selected as the array corresponding to the reference memory cell (reference cell array). At this time, the area occupied by the array corresponding to the reference storage unit in the entire memory is: 128*32 / (8K*8K), which is about 0.005%. It can be seen that the area corresponding to the reference storage unit in the entire memory is relatively small and can be ignored. Therefore, the above-mentioned memory can improve the accuracy of data reading operations while avoiding a significant increase in device area.

[0052] Optionally, in some embodiments, the number of WLs of the reference cell array may be increased to improve the tracking accuracy of the reference cell array to the array corresponding to the main storage unit (main array).

[0053] The above-mentioned memory includes the storage module described in any of the above-mentioned embodiments, and has all the beneficial effects of the storage module described in any of the above-mentioned embodiments, which will not be repeated here.

[0054] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.

[0055] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0056] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0057] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

Claims

1. A storage module, characterized in that: The storage module includes a main storage unit and a reference storage unit; The main storage unit includes a storage area for storing data, and the storage area performs an erase and write operation under the control of a storage control circuit; The reference storage unit is used to follow the erase and write operations of the main storage unit, so that the electrical signal of the reference storage unit is consistent with the electrical signal of the main storage unit, and the reference signal is determined according to the electrical signal after each erase and write operation.

2. The storage module according to claim 1, characterized in that: The erase operation includes a data write 1 operation; The reference storage unit includes a first storage area; The first storage area is used to follow the data write 1 operation for the main storage unit, and after each data write 1 operation is performed, its electrical signal is consistent with the electrical signal after the main storage unit performs the same operation.

3. The storage module according to claim 2, characterized in that: The reference storage unit further includes a first current acquisition unit; The input end of the first current acquisition unit is connected to the output end of the first storage area, and the output end is used to output the reference signal, which is used to determine the reference signal according to a first preset ratio of the electrical signal of the first storage area.

4. The storage module according to claim 3, characterized in that: The first current acquisition unit includes a first current mirror; the first current mirror includes a first MOS tube and a second MOS tube; The source of the first MOS tube is used to access a preset voltage, the gate is connected to the gate of the second MOS tube, and the drain serves as an input end of the first current acquisition unit and is used to access the current output by the first storage area; The source of the second MOS tube is used to access the preset voltage, and the drain serves as the output end of the first current acquisition unit and is used to access the reference signal.

5. The storage module according to claim 1, characterized in that: The reference storage unit includes a second storage area and a third storage area; The second storage area is used to follow the data write 1 operation of the main storage unit, and after each data write 1 operation is performed, its electrical signal is consistent with the electrical signal of the main storage unit after the same operation is performed; The third storage area is used to follow the data write 0 operation of the main storage unit, and after each data write 0 operation is performed, its electrical signal is consistent with the electrical signal of the main storage unit after performing the same operation.

6. The storage module according to claim 5, characterized in that: The reference storage unit also includes a second current acquisition unit; The first input end of the second current acquisition unit is connected to the output end of the second storage area, the second input end is connected to the output end of the third storage area, and the output end is used to output the reference signal, which is used to determine the reference signal according to the sum of the electrical signals corresponding to the second storage area and the third storage area respectively.

7. The storage module according to claim 6, characterized in that: The second current acquisition unit includes an adder and a second current mirror; The first input end of the adder serves as the first input end of the second current acquisition unit, connected to the output end of the second storage area; the second input end serves as the second input end of the second current acquisition unit, connected to the output end of the third storage area; the output end is connected to the input end of the second current mirror; the output end of the second current mirror is used to output a reference signal.

8. The storage module according to claim 1, characterized in that: The main memory unit and the reference memory unit perform respective operations in synchronization.

9. A memory, characterized in that: The memory comprises a plurality of storage modules according to any one of claims 1 to 8.

10. The memory according to claim 9, characterized in that: The memory also includes a storage control circuit; The storage control circuit is used to obtain a reference signal output by a reference storage unit, detect an operating current of a main storage unit, and perform a data reading operation according to the operating current and the reference signal.

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