Memory input interface function path test method, electronic equipment and medium
By generating a list of target input interface function paths and automatically generating test vectors using automatic test vector generation tool, the problem of the existing technology being unable to effectively test the memory input interface function paths is solved, and full-speed testing and chip operation frequency are improved.
Patent Information
- Application Number
- CN202411886157.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-11
AI Technical Summary
The prior art cannot effectively test the memory input interface function path, resulting in the inability to increase the chip operation frequency.
By obtaining the target input interface function path in the function input circuit connected to the memory input interface, a list of the target input interface function paths is generated, and the test vector is automatically generated using the automatic test vector generation tool, and the target output data is captured through the MBIST output circuit for comparison, so as to realize the testing of the memory input interface function path.
The workload required to test the function path of the input interface is reduced, full-speed testing is achieved, and the chip operation frequency is improved.
Smart Images
Figure CN119811458A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip testing technology, and in particular to a memory input interface functional path testing method, electronic equipment and medium. Background Art
[0002] During chip testing, the memory itself is usually tested for faults by using an MBIST (Memory Built-In Self-Test) circuit integrated inside the chip for testing semiconductor memory. Traditional chip testing tests the circuits around the memory by inserting a bypass circuit around the memory, and tests the memory interface by scanning the path. However, the MBIST circuit can only test internal faults of the memory, and cannot test the functional path of the memory input interface. The introduction of the bypass circuit cannot truly reflect the functional path of the input interface under the functional mode. In addition, the scan path excludes the memory, and the clock frequency is very low, which cannot reach the frequency that the memory actually needs to run, and the frequency of the memory often determines the highest operating frequency of the chip. It can be seen from this that implementing the test of the functional path of the memory input interface and improving the chip operating frequency have become technical problems that need to be solved urgently. Summary of the invention
[0003] The purpose of the present invention is to provide a memory input interface functional path testing method, electronic equipment and medium, which improve the memory input interface testing performance and increase the chip operating frequency.
[0004] According to a first aspect of the present invention, a method for testing a memory input interface functional path is provided, comprising:
[0005] Step S1, obtaining a target input interface functional path in a functional input circuit connected to a memory input interface, and generating a target input interface functional path list;
[0006] Step S2, the automatic test vector generation tool selects at least one target input interface function path from the target input interface function path list, and automatically generates a test vector based on the selected target input interface function path;
[0007] Step S3, inputting the generated test vector into the memory through the selected target input interface functional path, and creating a conversion on the memory input interface;
[0008] Step S4, capturing target output data through the MBIST output circuit, comparing the target output data with the preset value, if they are consistent, the test passes, otherwise, the test fails, and the MBIST output circuit is connected to the output interface of the memory.
[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.
[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.
[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the memory input interface function path test method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:
[0012] The present invention can reduce the workload required for testing input interface function paths by setting a target input interface function path list, and uses a function input circuit as an input circuit of a memory, and uses an MBIST output circuit as a capture circuit of target data, thereby reducing the number of test vectors generated, and all tests of target input interface function paths pass through the memory, thereby achieving full-speed testing and improving chip frequency. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 A flow chart of a method for testing a memory input interface functional path provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0016] The embodiment of the present invention provides a memory input interface function path testing method, such as Figure 1 As shown, including:
[0017] Step S1, obtaining a target input interface functional path in a functional input circuit connected to a memory input interface, and generating a target input interface functional path list.
[0018] Among them, the functional input circuit is a combinational logic circuit. The target input interface functional path is the input interface functional path that needs to be tested. It should be noted that there are usually multiple paths in the functional input circuit. If based on each input interface functional path, a large number of test vectors need to be generated, but in fact not every input interface functional path needs to be tested. By obtaining the target input interface functional path list, the generation of test vectors can be greatly reduced, and the efficiency of memory input interface functional path testing can be improved. In an embodiment of the present invention, the memory can specifically be a random access memory (Random Access Memory, referred to as RAM) or a read-only memory (Read-Only Memory, ROM). The input interface of the RAM includes a data input interface and an address input interface, and the input interface of the ROM only includes an address input interface.
[0019] Step S2: An automatic test vector generation tool (ATPG) selects at least one target input interface functional path from the target input interface functional path list, and automatically generates a test vector based on the selected target input interface functional path.
[0020] It should be noted that the automatic test vector generation tool can select one or more target input interface function paths for each test. In order to improve test efficiency, one test can cover as many target input interface function paths as possible.
[0021] Step S3: input the generated test vector into the memory through the selected target input interface functional path, and create a transition on the memory input interface.
[0022] It should be noted that since the test target is the input interface functional path, it is necessary to create a conversion on the storage input interface.
[0023] Step S4, capturing target output data through the MBIST output circuit, comparing the target output data with the preset value, if they are consistent, the test passes, otherwise, the test fails, and the MBIST output circuit is connected to the output interface of the memory.
[0024] Among them, the MBIST output circuit is a circuit integrated inside the chip for testing semiconductor memory. It should be noted that during the functional path test of the memory input interface, the ATPG tool is guided to control the memory input interface through the functional input circuit, but the data read by the memory is captured through the MBIST output circuit, which helps to reduce the overall pattern generation work required to observe the fault, and all test paths pass through the memory, so that the test path runs at the required operating frequency of the memory, realizing full-speed testing, thereby improving the chip operating frequency.
[0025] As an embodiment, the step S4 includes:
[0026] Step S5, determine whether all target input interface function paths in the target input interface function path list have been tested, if so, end the process, otherwise, return to step S2.
[0027] As an embodiment, the step S1 includes:
[0028] Step S11: Obtain the delay of each input interface functional path in the functional input circuit based on a static timing analysis tool.
[0029] Step S12: Arrange the delays of all input interface function paths in descending order.
[0030] Step S13: determine the first M preset input interface function paths as target input interface function paths.
[0031] Specifically, the input interface function paths ranked in the top X% can be determined as the top preset M input interface function paths, and X can be specifically set to 10 or 20, etc. A delay threshold can also be set, and the input interface function paths exceeding the delay threshold can be determined as the top preset M input interface function paths. It should be noted that the target input interface function path is the input interface function path that needs to be tested. By screening the target input interface function path, the input interface function paths that do not need to be tested can be filtered out in advance, thereby reducing the number of subsequent test vectors generated and improving the input interface function path test efficiency.
[0032] Step S14: input all target input interface function paths into an automatic test vector generation tool to generate a target input interface function path list.
[0033] As an embodiment, the memory is set as a random access memory, and the memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the data input interface, the step S3 includes:
[0034] Step S31: Based on the selected target input interface functional path, a first address is input through the address input interface, a first value is input through the data input interface, and the first value is written into the first address of the memory.
[0035] Step S32: based on the selected target input interface functional path, input a first address through the address input interface, input a second value through the data input interface, write the second value into the first address of the memory, thereby creating a conversion on the data input interface, wherein the first value and the second value are different values.
[0036] If it is necessary to test whether the target input interface function path connected to the data input interface is fixed to 0, the first value is set to 0 and the second value is set to 1. If it is necessary to test whether the target input interface function path connected to the data input interface is fixed to 1, the first value is set to 1 and the second value is set to 0.
[0037] The step S4 comprises:
[0038] Step S41, reading data from the first address as target output data through the MBIST output circuit, if the target output data is a preset value, and the preset value is equal to the second numerical value, then the functional path test of the target input interface connected to the currently selected data input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected data input interface fails.
[0039] It should be noted that if the target input interface functional path connected to the data input interface that needs to be tested has the problem of fixed connection of the first numerical value, then reading data from the first address by the MBIST output circuit is the first numerical value, and the test fails. If the target input interface functional path connected to the data input interface that needs to be tested has no problem, then reading data from the first address by the MBIST output circuit is the second numerical value, and the test passes.
[0040] As an embodiment, the memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the address input interface, step S3 includes:
[0041] Step C31: Based on the selected target input interface functional path, a second address is input through the address input interface, a third value is input through the data input interface, and the third value is written into the second address of the memory.
[0042] Step C32: based on the selected target input interface functional path, input a third address through the address input interface, input a third value through the data input interface, write the third value into the third address of the memory, thereby creating a conversion on the address input interface, wherein the third address and the second address are different addresses.
[0043] The step S4 comprises:
[0044] Step C41, reading data from the third address as target output data through the MBIST output circuit, if the target output data is a preset value, the preset value is the third numerical value, then the functional path test of the target input interface connected to the currently selected address input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected address input interface fails.
[0045] It should be noted that step C31-step C32 has written the same data in different addresses. If there is a fault in the target input interface functional path connected to the selected address input interface, then reading data from the third address by the MBIST output circuit is not the third numerical value, and the test fails. If there is no fault in the target input interface functional path connected to the selected address input interface, then reading data from the third address by the MBIST output circuit is the third numerical value, and the test passes.
[0046] As an embodiment, the memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the data input interface and the address input interface, step S3 includes:
[0047] Step D31: Based on the selected target input interface functional path, a fourth address is input through the address input interface, a fourth value is input through the data input interface, and the fourth value is written into the fourth address of the memory;
[0048] Step D32: based on the selected target input interface functional path, input a fifth address through the address input interface, input a fifth value through the data input interface, write the fifth value into the fifth address of the memory, create a conversion on the data input interface and the address input interface, the fourth value and the fifth value are different values, and the fourth address and the fifth address are different addresses;
[0049] The step S4 comprises:
[0050] Step D41, reading data from the fifth address as target output data through the MBIST output circuit, if the target output data is a preset value, the preset value is the fifth numerical value, then the functional path test of the target input interface connected to the currently selected data input interface and the address input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected data input interface and the address input interface fails.
[0051] It should be noted that if there is no fault in the target input interface functional path corresponding to the current test target, the data read from the fifth address through the MBIST output circuit is equal to the fifth numerical value, and the test passes; if there is a fault in the target input interface functional path corresponding to the current test target, the data read from the fifth address through the MBIST output circuit is not equal to the fifth numerical value, and the test fails.
[0052] The embodiment of the present invention can reduce the workload required for testing the input interface function path by setting the target input interface function path list, and uses the function input circuit as the input circuit of the memory, and uses the MBIST output circuit as the capture circuit of the target data, thereby reducing the number of test vectors generated, and the tests of all target input interface function paths pass through the memory, thereby realizing full-speed testing and improving the chip frequency.
[0053] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.
[0054] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.
[0055] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.
[0056] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.
Claims
1. A memory input interface functional path testing method, characterized in that: include: Step S1, obtaining a target input interface functional path in a functional input circuit connected to a memory input interface, and generating a target input interface functional path list; Step S2, the automatic test vector generation tool selects at least one target input interface function path from the target input interface function path list, and automatically generates a test vector based on the selected target input interface function path; Step S3, inputting the generated test vector into the memory through the selected target input interface functional path, and creating a conversion on the memory input interface; Step S4, capturing target output data through the MBIST output circuit, comparing the target output data with the preset value, if they are consistent, the test passes, otherwise, the test fails, and the MBIST output circuit is connected to the output interface of the memory.
2. The method according to claim 1, characterized in that The step S4 then includes: Step S5, determine whether all target input interface function paths in the target input interface function path list have been tested, if so, end the process, otherwise, return to step S2.
3. The method according to claim 1, characterized in that The step S1 comprises: Step S11, obtaining the delay of each input interface functional path in the functional input circuit based on a static timing analysis tool; Step S12: Arrange the delays of all input interface function paths in descending order; Step S13: determining the first M preset input interface function paths as target input interface function paths; Step S14: input all target input interface function paths into an automatic test vector generation tool to generate a target input interface function path list.
4. The method according to claim 1, characterized in that: The memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the data input interface, step S3 includes: Step S31: Based on the selected target input interface functional path, a first address is input through the address input interface, a first value is input through the data input interface, and the first value is written into the first address of the memory; Step S32: inputting a first address through the address input interface based on the selected target input interface functional path, inputting a second value through the data input interface, and writing the second value into the first address of the memory, thereby creating a conversion on the data input interface, wherein the first value and the second value are different values; The step S4 comprises: Step S41, reading data from the first address as target output data through the MBIST output circuit, if the target output data is a preset value, and the preset value is equal to the second numerical value, then the functional path test of the target input interface connected to the currently selected data input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected data input interface fails.
5. The method according to claim 1, characterized in that The memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the address input interface, step S3 includes: Step C31: Based on the selected target input interface functional path, a second address is input through the address input interface, a third value is input through the data input interface, and the third value is written into the second address of the memory; Step C32: inputting a third address through the address input interface based on the selected target input interface functional path, inputting a third value through the data input interface, and writing the third value into the third address of the memory, thereby creating a conversion on the address input interface, wherein the third address and the second address are different addresses; The step S4 comprises: Step C41, reading data from the third address as target output data through the MBIST output circuit, if the target output data is a preset value, the preset value is the third numerical value, then the functional path test of the target input interface connected to the currently selected address input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected address input interface fails.
6. The method according to claim 1, characterized in that The memory input interface includes a data input interface and an address input interface. If the current test target is a target input interface functional path connected to the data input interface and the address input interface, step S3 includes: Step D31: Based on the selected target input interface functional path, a fourth address is input through the address input interface, a fourth value is input through the data input interface, and the fourth value is written into the fourth address of the memory; Step D32: based on the selected target input interface functional path, input a fifth address through the address input interface, input a fifth value through the data input interface, write the fifth value into the fifth address of the memory, create a conversion on the data input interface and the address input interface, the fourth value and the fifth value are different values, and the fourth address and the fifth address are different addresses; The step S4 comprises: Step D41, reading data from the fifth address as target output data through the MBIST output circuit, if the target output data is a preset value, the preset value is the fifth numerical value, then the functional path test of the target input interface connected to the currently selected data input interface and the address input interface passes, otherwise, the functional path test of the target input interface connected to the currently selected data input interface and the address input interface fails.
7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.
8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.