Test method and test system

Abstract

The invention discloses a testing method and a testing system, and relates to the technical field of chip testing. The test method comprises the following steps: inputting random data into a flash memory chip; adjusting the operation frequency of the flash memory chip, and performing read-write operation of random data under each adjusted operation frequency; recording a data value of error bits in the read-write operation under each operation frequency; according to the recording result, hardware parameters of the flash memory chip are generated; the hardware parameters comprise a maximum set value and a minimum set value, the maximum set value is the maximum value of the hardware parameters in the data values without errors under the operation frequency, and the minimum set value is the minimum value of the hardware parameters in the data values without errors under the operation frequency; according to the test method provided by the embodiment of the invention, the operation complexity and the possibility of human errors are reduced by simulating the condition of the flash memory chip under the actual read-write operation.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a testing method and a testing system. Background Art

[0002] With the continuous advancement of technology, the performance of Nand Flash (flash memory chip) has been significantly improved in terms of storage density, read and write speed, durability, etc. However, with the increase in system complexity and application requirements, how to accurately evaluate Nand Flash signals, especially under high load and actual working environment, has become a key challenge in the design and development process. Traditional test tools, such as oscilloscopes and logic analyzers, can help engineers perform basic timing and waveform analysis on signals. However, in actual applications, storage devices equipped with Nand Flash usually have complex multi-layer circuits and need to face large-scale data transmission and high-load scenarios. These tools often find it difficult to provide comprehensive and true performance feedback, and oscilloscopes and logic analyzers need to be manually configured and debugged, which is complicated to operate and prone to human errors. Summary of the invention

[0003] The purpose of the present application is to provide a testing method and a testing system, which can reduce the operational complexity and the possibility of human error by simulating the actual read and write operations of a flash memory chip.

[0004] The present application discloses a testing method, which is applied to a flash memory chip. The testing method comprises the following steps:

[0005] Input random data into the flash memory chip;

[0006] Adjusting the operating frequency of the flash memory chip, and performing random data read and write operations at each adjusted operating frequency;

[0007] Recording the data value of the error bit in the read and write operations at each operating frequency; and

[0008] Generate the hardware parameters of the flash memory chip according to the recorded results;

[0009] Among them, the hardware parameters include a maximum setting value and a minimum setting value. The maximum setting value is the maximum value of the hardware parameter among the data values ​​without errors at the operating frequency, and the minimum setting value is the minimum value of the hardware parameter among the data values ​​without errors at the operating frequency.

[0010] Optionally, the step of inputting random data into the flash memory chip includes:

[0011] Send the command of inputting random data generated by the host computer to the test socket;

[0012] The test socket receives the above command and inputs random data into the flash memory chip according to the command.

[0013] Optionally, in the step of adjusting the operating frequency of the flash memory chip and performing random data read and write operations at each adjusted operating frequency, the operating frequency ranges from 0 Hz to 265 Hz.

[0014] Optionally, the testing method further comprises the steps of:

[0015] According to the generated hardware parameters of the flash memory chip, a delay phase-locked loop of the flash memory chip is set;

[0016] Wherein, the delay locked loop is located between the maximum data value and the minimum data value.

[0017] Optionally, the read-write operation includes a read operation and a write operation;

[0018] In the test of the read operation, when writing data, the operating frequency of the flash memory chip is fixed to a low frequency, and when reading data, the operating frequency of the flash memory chip is gradually increased;

[0019] In the test of the write operation, when reading data, the operating frequency of the flash memory chip is fixed to a low frequency, and when writing data, the operating frequency of the flash memory chip is gradually increased.

[0020] Optionally, the low frequency is between 0 and 30 Hz.

[0021] Optionally, the step of recording erroneous data values ​​in the read and write operations at each operating frequency includes:

[0022] Establish a read window and a write window for recording;

[0023] Draw a reading window according to the erroneous data values ​​appearing in the reading data;

[0024] The write window is drawn according to the erroneous data value appearing in the write data.

[0025] Optionally, in the step of recording the erroneous data values ​​in the read and write operations at each operating frequency, when performing a read operation, at the same operating frequency, the written data is compared with the read data to determine whether an erroneous data value occurs;

[0026] When performing a write operation, at the same operating frequency, the read data is compared with the written data to determine whether an erroneous data value occurs.

[0027] Optionally, the test socket compares random data in the read and write operations to obtain the number of error bits.

[0028] The present application also discloses a test system, which is applied to a flash memory chip. The test system comprises a test socket and a host computer. The host computer is electrically connected to the test socket. The test socket is used to place the flash memory chip.

[0029] Wherein, the host computer and the test socket test the flash memory chip through the above-mentioned test method.

[0030] Compared with the existing method of testing flash memory chips through traditional testing tools such as oscilloscopes, logic analyzers, etc., the testing method of the present application can simulate the actual read and write operations of the flash memory chip, and can more realistically simulate the behavior under the workload. By analyzing the data in the read and write operations, the maximum data value and the minimum data value at which the flash memory chip runs stably at the operating frequency can be obtained, and the hardware parameters of the flash memory chip are generated based on the data, which is convenient for designers to adjust and set the operating strategy of the flash memory chip according to the hardware parameters, avoid settings that may cause errors, and provide comprehensive and true performance feedback. In addition, the testing method of this embodiment does not require manual configuration and debugging like an oscilloscope and a logic analyzer, reducing the complexity of operation and the possibility of human error. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0032] Figure 1 is a step flow chart of a testing method of the first embodiment of the present application;

[0033] Figure 2 is a detailed flow chart of the step of inputting random data into a flash memory chip in a testing method of the first embodiment of the present application;

[0034] Figure 3 is a flow chart of the overall steps of a testing method of the first embodiment of the present application;

[0035] Figure 4 is a flow chart of steps for establishing a read window and a write window in a test method of the first embodiment of the present application;

[0036] Figure 5 is a schematic diagram of a first embodiment of the present application when the reading window is normal;

[0037] Figure 6is a schematic diagram of a case where the reading window is abnormal in the first embodiment of the present application;

[0038] Figure 7 is a schematic diagram of the first embodiment of the present application when the writing window is normal;

[0039] Figure 8 is a schematic diagram of a case where the write window is abnormal in the first embodiment of the present application;

[0040] Fig. 9 It is a structural diagram of a test system of the second embodiment of the present application.

[0041] Among them, 100, flash memory chip; 200, host computer; 300, test socket; 400, test system. DETAILED DESCRIPTION

[0042] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0043] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.

[0044] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present application.

[0045] In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] The present application is described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0047] like Figure 1 As shown, as a first embodiment of the present application, a testing method is disclosed, the testing method is applied to a flash memory chip, and the testing method comprises the steps of:

[0048] Input random data into the flash memory chip;

[0049] Specifically, the test method of this embodiment is run through a host computer and a test socket, the flash memory chip is installed on the test socket, the flash memory chip is communicated with the test socket, and the test socket is communicated with the host computer;

[0050] Adjusting the operating frequency of the flash memory chip, and performing random data read and write operations at each adjusted operating frequency;

[0051] Specifically, the operating frequency of the flash memory chip is adjusted from a low frequency to a high frequency, and a data read and write operation is performed after each frequency adjustment;

[0052] Record the data value of the error bit (Error Bit) in the read and write operations at each operating frequency; and

[0053] Specifically, by comparing the data in the read operation and the write operation, it is determined whether an error bit occurs, so as to count the maximum data value and the minimum data value without an error bit at each operating frequency. Generally, a test socket or a host computer is used to compare the random data in the read and write operations, and the number of error bits is obtained by comparing the read data with the written data.

[0054] Generate the hardware parameters of the flash memory chip according to the recorded results;

[0055] Among them, the hardware parameters include a maximum setting value and a minimum setting value. The maximum setting value is the maximum value of the hardware parameter among the data values ​​without errors at the operating frequency, and the minimum setting value is the minimum value of the hardware parameter among the data values ​​without errors at the operating frequency.

[0056] In this embodiment, random data is written to the flash memory chip, and the operating frequency of the flash memory chip is gradually adjusted so that the flash memory chip can perform read and write operations in a simulated real operation state, thereby obtaining close to real operation data, and then generating the hardware parameters of the flash memory chip according to the obtained operation data and the maximum data value and the minimum data value without error bits. Compared with the existing method of testing the flash memory chip through traditional testing tools such as oscilloscopes and logic analyzers, the testing method of the present application can simulate the actual read and write operation of the flash memory chip, and can more realistically simulate the behavior under the workload. By analyzing the data in the read and write operation, the maximum data value and the minimum data value of the flash memory chip running stably at the operating frequency can be obtained, and the hardware parameters of the flash memory chip are generated according to the data, which is convenient for designers to adjust and set the operation strategy of the flash memory chip according to the hardware parameters, avoid settings that may cause errors, and provide comprehensive and real performance feedback. In addition, the testing method of this embodiment does not require manual configuration and debugging like oscilloscopes and logic analyzers, reducing the complexity of operation and the possibility of human errors.

[0057] like Figure 2 As shown, further, the step of inputting random data into the flash memory chip includes:

[0058] Send the command of inputting random data generated by the host computer to the test socket;

[0059] Specifically, the host computer may be a terminal device such as a computer or a server, and the test socket is a test socket for loading a flash memory chip, which may be loaded with different types of flash memory chips or may only be loaded with a single type of flash memory chip. The designer may select and design according to the actual situation, which will not be described in detail here;

[0060] The test socket receives the above command and inputs random data into the flash memory chip according to the command.

[0061] Specifically, the communication connection between the test socket and the host computer can be achieved by setting up a communication interface and a corresponding communication cable. After the host computer transmits a command to input random data to the test socket, the test socket receives the command and inputs the random data into a flash memory chip set on the test socket according to the command so that the flash memory chip can perform read and write operations. It should be noted that the random data can be pre-stored in the test socket or stored in the host computer, and input into the test socket together with the command of the host computer to be input into the flash memory chip.

[0062] Wherein, in the step of adjusting the operating frequency of the flash memory chip and performing random data read and write operations at each adjusted operating frequency, the operating frequency ranges from 0 Hz to 265 Hz, and the distribution of the operating frequencies can be divided into 52 Hz, 57 Hz, 62 Hz, 67 Hz, 72 Hz, 77 Hz, 82 Hz, 87 Hz, 92 Hz, 97 Hz, 105 Hz, 115 Hz, 125 Hz, 135 Hz, 145 Hz, 155 Hz, 165 hz, 175hz, 185hz, 195hz, 205hz, 215hz, 225hz, 235hz, 245hz, 255hz, 265hz and the like, and a random data write operation and a read operation are performed at each operating frequency to obtain the test result at the operating frequency; of course, the operating frequency can also be divided according to actual conditions, which can be 1hz or 5hz apart. Designers can make adjustments according to actual conditions, which will not be elaborated here.

[0063] like Figure 3 As shown, after generating the hardware parameters of the flash memory chip according to the recording results, the testing method further includes the steps of:

[0064] According to the generated hardware parameters of the flash memory chip, a delay-locked loop (DDL) of the flash memory chip is set, and the delay-locked loop is located between the maximum data value and the minimum data value.

[0065] In the test method of this embodiment, the hardware parameters generated after the random data read and write operation is performed on the flash memory chip can also be used to adjust the delay phase-locked loop of the flash memory chip according to the obtained hardware parameters, so that the flash memory chip can be maintained in a normal operating state when it is subsequently used, and the read and write latch delay period can be automatically adjusted according to the test method of this embodiment to ensure that the DQS signal and the DQS_90 signal are locked at a stable offset. It should be noted that the delay phase-locked loop can be an average value between the maximum data value and the minimum data value, so that the flash memory chip can maintain a longer service life when in use.

[0066] Furthermore, in the above-mentioned test method, the read-write operation includes a read operation and a write operation;

[0067] In the test of the read operation, when writing data, the operating frequency of the flash memory chip is fixed to a low frequency, and the stability of the read is tested at a stable write frequency to avoid the impact caused by the frequency of writing data being too high. When reading data, the operating frequency of the flash memory chip is gradually increased to test the read stability of the flash memory chip at different frequencies;

[0068] In the test of the write operation, when reading data, the operating frequency of the flash memory chip is fixed to a low frequency to ensure that the reading process does not affect the stability of the write operation. When writing data, the operating frequency of the flash memory chip is gradually increased to test the writing stability of the flash memory chip at different frequencies. It should be noted that the above-mentioned low frequency can be between 0 and 30 Hz (MHz), and in the present embodiment, 20 Hz is preferred.

[0069] The test method of this embodiment, when performing read and write operation tests, maintains a low frequency of writing data during the read operation to ensure that the write process does not affect the stability of the read operation, and when performing the write operation, maintains a low frequency of reading data to ensure that the read process does not affect the stability of the write operation, avoiding factors that affect the test results during the test process to ensure the accuracy of the test.

[0070] In addition, if Figure 4 As shown, in order to make the test results easy for the tester to understand, the step of recording the erroneous data values ​​in the read and write operations at each operating frequency includes:

[0071] Establish a read window and a write window for recording;

[0072] Specifically, a read window (Read Pass Window) and a write window (Write Pass Window) are established in the host computer for recording;

[0073] Draw a reading window according to the erroneous data values ​​appearing in the reading data;

[0074] The write window is drawn according to the erroneous data value appearing in the write data.

[0075] Specifically, in the read window and the write window, a horizontal axis coordinate and a vertical axis coordinate are established, the horizontal axis coordinate is the operating frequency of the flash memory chip, and the vertical axis coordinate is DQS_DLL_level (i.e., hardware parameters). According to the maximum setting value of the hardware parameter in the data value without error at each operating frequency, the maximum value hardware parameter boundary line is drawn, and according to the minimum setting value of the hardware parameter in the data value without error at each operating frequency, the minimum value hardware parameter boundary line is drawn to obtain the read window and the write window. The read window and the write window of a normal flash memory chip are respectively as follows: Figure 5 and Figure 7As shown in the figure, the tester can easily understand the test results of the flash memory chip and comprehensively evaluate the read and write stability of the flash memory chip in the real working environment based on the read window and write window. In addition, through the read window and write window, the tester can also understand the specific operating frequency of the flash memory chip when the read error and write error occur. The read window and write window of the abnormal flash memory chip are as follows: Figure 6 and Figure 8 As shown, the flash memory chip can be analyzed in a targeted manner to facilitate subsequent repairs, or the operating frequency of the flash memory chip can be adjusted so that the flash memory chip avoids using an erroneous operating frequency for read and write operations in actual use. In general, in this embodiment, the test results are displayed by setting a read window and a write window, so that the tester can understand the test results of the flash memory chip in a simple and easy-to-understand manner, and comprehensively evaluate the read and write stability of the flash memory chip in a real working environment based on the read window and the write window, and can also analyze the abnormal flash memory chip in a targeted manner to facilitate subsequent repairs, etc., providing convenience for relevant testers.

[0076] It should be noted that in the step of recording the erroneous data values ​​in the read and write operations at each operating frequency, when performing a read operation, at the same operating frequency, the written data is compared with the read data to determine whether an erroneous data value, i.e., an error bit, occurs at the operating frequency; and when performing a write operation, at the same operating frequency, the read data is compared with the written data to determine whether an erroneous data value, i.e., an error bit, occurs at the operating frequency. Furthermore, when the flash memory chip performs a read and write operation, the size of the random data is tested in order from large to small, i.e., the size of the random data is reduced in order until no error bit occurs in the read and write operations.

[0077] like Fig. 9 As shown, as a test system of the present application, it is applied to flash memory chips, and the test system includes a test socket and a host computer, the host computer is electrically connected to the test socket, and the test socket is used to place the flash memory chip; wherein the host computer and the test socket test the flash memory chip through the test method described in the above embodiment.

[0078] The test system of the present application can simulate the conditions of the flash memory chip under actual read and write operations during testing, and can more realistically simulate the behavior under workload. By analyzing the data in the read and write operations, the maximum and minimum data values ​​at which the flash memory chip can operate stably at the operating frequency can be obtained, and the hardware parameters of the flash memory chip can be generated based on the data, so that designers can adjust and set the operating strategy of the flash memory chip according to the hardware parameters, avoid settings that may cause errors, and provide comprehensive and true performance feedback.

[0079] It should be noted that the limitations on the various steps involved in this solution, without affecting the implementation of the specific solution, are not deemed to limit the order of the steps. The steps written in front can be executed first, or later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0080] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0081] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A testing method, applied to a flash memory chip, characterized in that: Includes steps: Input random data into the flash memory chip; Adjusting the operating frequency of the flash memory chip, and performing random data read and write operations at each adjusted operating frequency; Record the data value of the error bit in the read and write operations at each operating frequency; as well as Generate the hardware parameters of the flash memory chip according to the recorded results; Among them, the hardware parameters include a maximum setting value and a minimum setting value. The maximum setting value is the maximum value of the hardware parameter among the data values ​​without errors at the operating frequency, and the minimum setting value is the minimum value of the hardware parameter among the data values ​​without errors at the operating frequency.

2. The testing method according to claim 1, characterized in that: The step of inputting random data into the flash memory chip comprises: Send the command of inputting random data generated by the host computer to the test socket; The test socket receives the above command and inputs random data into the flash memory chip according to the command.

3. The testing method according to claim 1, characterized in that: In the step of adjusting the operating frequency of the flash memory chip and performing random data read and write operations at each adjusted operating frequency, the operating frequency ranges from 0 Hz to 265 Hz.

4. The testing method according to claim 1, characterized in that: Also includes the steps: According to the generated hardware parameters of the flash memory chip, a delay phase-locked loop of the flash memory chip is set; Wherein, the delay locked loop is located between the maximum data value and the minimum data value.

5. The testing method according to claim 1, characterized in that: The read-write operation includes a read operation and a write operation; In the test of the read operation, when writing data, the operating frequency of the flash memory chip is fixed to a low frequency, and when reading data, the operating frequency of the flash memory chip is gradually increased; In the test of the write operation, when reading data, the operating frequency of the flash memory chip is fixed to a low frequency, and when writing data, the operating frequency of the flash memory chip is gradually increased.

6. The testing method according to claim 5, characterized in that: The low frequency is between 0 and 30 Hz.

7. The testing method according to claim 1, characterized in that: The step of recording the data value that has errors in the read and write operations at each operating frequency comprises: Establish a read window and a write window for recording; Draw a reading window according to the erroneous data values ​​appearing in the reading data; The write window is drawn according to the erroneous data value appearing in the write data.

8. The testing method according to claim 1, characterized in that: In the step of recording the erroneous data values ​​in the read and write operations at each operating frequency, when performing a read operation, at the same operating frequency, the written data is compared with the read data to determine whether an erroneous data value occurs; When performing a write operation, at the same operating frequency, the read data is compared with the written data to determine whether an erroneous data value occurs.

9. The testing method according to claim 1, characterized in that: The test socket compares the random data in the read and write operations to obtain the number of error bits.

10. A test system, applied to flash memory chips, characterized in that: It includes a test socket and a host computer, the host computer is electrically connected to the test socket, and the test socket is used to place the flash memory chip; Wherein, the host computer and the test socket test the flash memory chip by the test method described in any one of claims 1 to 9 above.

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