Intrinsic epitaxial growth method, semiconductor structure and semiconductor device

Abstract

The invention provides an intrinsic epitaxial growth method, a semiconductor structure and a semiconductor device, and the method comprises the steps: providing a semiconductor substrate, and forming a buried layer in the semiconductor substrate; placing the semiconductor substrate in a normal pressure epitaxial device; baking the semiconductor substrate based on a preset baking temperature; and introducing reaction source gas and hydrogen into the normal-pressure epitaxial equipment, and growing an intrinsic epitaxial layer on the surface of the semiconductor substrate. The semiconductor structure is obtained by adopting the intrinsic epitaxial growth method. The semiconductor device comprises the semiconductor structure. According to the invention, the epitaxial layer is grown by using the normal-pressure epitaxial equipment, so that the diffusion of the buried layer is more easily inhibited, the growth process of the intrinsic epitaxial layer is simplified, the growth efficiency of the intrinsic epitaxial layer is improved, and the production process requirements of the ultrahigh-resistance intrinsic epitaxial layer can be met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an intrinsic epitaxial growth method, a semiconductor structure and a semiconductor device. Background Art

[0002] In the prior art, the method of growing an epitaxial layer on a high-concentration buried layer includes: using a reduced-pressure epitaxial device (dichlorosilane DCS as the silicon source) to perform repeated high-temperature purge (to push the buried layer forward), then lowering the temperature and performing repeated purge (to inhibit the diffusion of the buried layer), and then selecting a lower temperature to grow the epitaxial layer. This method takes a long process time, resulting in low production efficiency of semiconductor structures and semiconductor devices. In addition, high-temperature purge can cause some back-sealing materials such as chlorides to become loose, and particles will be generated on the base, affecting the quality and yield of semiconductor devices. At the same time, the surface resistivity of the intrinsic epitaxial layer grown using the prior art can only reach greater than 100 ohms·cm, which cannot meet the growth process requirements of some ultra-high resistance intrinsic epitaxial layers.

[0003] Therefore, it is necessary to provide a process method that can meet the requirements of ultra-high resistance intrinsic epitaxial layer and improve the efficiency of epitaxial layer growth.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In response to the problems in the prior art, the purpose of the present application is to provide an intrinsic epitaxial growth method, a semiconductor structure and a semiconductor device, which uses normal pressure epitaxial equipment to grow the epitaxial layer, makes it easier to suppress the diffusion of the buried layer, eliminates the high-temperature and low-temperature purge processes, prevents the buried layer doping from being diffused out by long-term purge, simplifies the intrinsic epitaxial layer growth process, and improves the intrinsic epitaxial layer growth efficiency, so as to meet the production process requirements of ultra-high resistance intrinsic epitaxial layers.

[0006] The first aspect of the present application provides an intrinsic epitaxial growth method, comprising:

[0007] Providing a semiconductor substrate, wherein a buried layer is formed in the semiconductor substrate;

[0008] Placing the semiconductor substrate in a normal pressure epitaxial growth device;

[0009] Baking the semiconductor substrate based on a preset baking temperature;

[0010] Reaction source gas and hydrogen are introduced into the atmospheric pressure epitaxial growth equipment to grow an intrinsic epitaxial layer on the surface of the semiconductor substrate.

[0011] In some embodiments, the preset baking temperature is 1120°C to 1140°C.

[0012] In some embodiments, the reaction source gas is trichlorosilane gas.

[0013] In some embodiments, the flow rate of the trichlorosilane gas is set to 4L to 6L per minute.

[0014] In some embodiments, the flow rate of hydrogen is set to 40-45 L per minute.

[0015] In some embodiments, the buried layer in the semiconductor substrate is a high-concentration buried layer with a concentration greater than 2E15.

[0016] In some embodiments, the intrinsic epitaxial layer is an ultra-high resistance intrinsic epitaxial layer.

[0017] In some embodiments, the surface resistivity of the intrinsic epitaxial layer is greater than 1000 ohm·cm, and the resistivity at a surface depth of 2.5 μm is greater than 400 ohm·cm.

[0018] A second aspect of the present application provides a semiconductor structure obtained by using the intrinsic epitaxial growth method described in the first aspect.

[0019] A third aspect of the present application provides a semiconductor device, comprising the semiconductor structure of the second aspect.

[0020] The intrinsic epitaxial growth method, semiconductor structure and semiconductor device provided in this application have the following advantages:

[0021] The present application uses normal pressure epitaxial equipment to grow the epitaxial layer, which makes it easier to suppress the diffusion of the buried layer, eliminate the high temperature and low temperature purge processes, prevent the diffusion of the buried layer doping due to long-term purge, simplify the intrinsic epitaxial layer growth process, and improve the intrinsic epitaxial layer growth efficiency, which can meet the production process requirements of the ultra-high resistance intrinsic epitaxial layer; the present application uses normal pressure epitaxial equipment, which has a simpler equipment structure and lower cost than the reduced pressure epitaxial equipment in the prior art, and is also conducive to reducing the preparation cost of semiconductor structures and semiconductor devices. The intrinsic epitaxial growth method of the present application can be applied to the preparation of semiconductor structures with intrinsic epitaxial layers in various types of semiconductor devices, such as high-frequency devices, power devices, integrated chips, sensors, etc., so the intrinsic epitaxial growth method has a wide range of applications.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a flow chart of an intrinsic epitaxial growth method according to an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of an intrinsic epitaxial growth process in one embodiment of the present application;

[0026] Figure 3 It is a schematic diagram of the temperature change of the intrinsic epitaxial layer grown by high temperature purge and low temperature purge;

[0027] Figure 4 is a schematic diagram of temperature variation during the growth process of an intrinsic epitaxial layer in one embodiment of the present application;

[0028] Figure 5 This is a schematic diagram of the variation of the resistivity of the intrinsic epitaxial layer grown by the present application with depth according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the same reference numerals represent the same or similar structures, and thus their repeated description will be omitted. "or" and "or" in the specification may both mean "and" or "or".

[0030] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0031] In the intrinsic epitaxial growth method in the prior art, a reduced pressure epitaxial device is used, and high temperature purge and low temperature purge are used to advance the buried layer and inhibit the diffusion of the buried layer. This method has a relatively complicated process flow, which affects the efficiency of the growth of the intrinsic epitaxial layer, thereby affecting the preparation efficiency of the semiconductor device, and is not suitable for preparing an ultra-high resistance intrinsic epitaxial layer. In order to solve this technical problem, the present application provides a new intrinsic epitaxial growth method, which uses normal pressure epitaxial equipment, omits the high temperature purge and low temperature purge processes, has higher production efficiency, and can grow an ultra-high resistance intrinsic epitaxial layer.

[0032] like Figure 1 As shown, the first aspect of the present application provides an intrinsic epitaxial growth method, comprising:

[0033] S100: providing a semiconductor substrate, wherein a buried layer is formed in the semiconductor substrate;

[0034] In semiconductor device manufacturing, a buried layer is a special area located at a certain depth inside the semiconductor substrate. It is formed by specific process technologies such as ion implantation or epitaxial growth. The buried layer is usually intentionally manufactured to change the electrical performance and physical properties of semiconductor devices. For example, by forming a buried layer with a different conductivity type from the substrate in a silicon substrate through doping, the current conduction path and electric field distribution of the device can be adjusted;

[0035] In this embodiment, the buried layer in the semiconductor substrate is a high-concentration buried layer with a concentration greater than 2E15, which means that the number of impurity atoms contained in each cubic centimeter of volume in this buried layer region is greater than 2E15. However, the present application is not limited thereto, and in other alternative implementations, the concentration of the buried layer may also be other values, which also fall within the protection scope of the present application;

[0036] S200: placing the semiconductor substrate in a normal pressure epitaxial growth device;

[0037] In atmospheric pressure epitaxial growth equipment, the epitaxial growth process is carried out under pressure conditions close to atmospheric pressure. The pressure in the reaction chamber is usually around one standard atmospheric pressure. Under atmospheric pressure, the reaction source gas decomposes on the high-temperature substrate surface and deposits silicon atoms, thereby growing a silicon epitaxial layer.

[0038] The reduced pressure epitaxial equipment used in the prior art is carried out under a pressure environment lower than atmospheric pressure; compared with the reduced pressure epitaxial equipment in the prior art, the atmospheric pressure epitaxial equipment used in the present application has a simpler structure, mainly including basic components such as a reaction chamber, a gas supply system, a heating system and an exhaust gas treatment system, and the pressure control requirements of the reaction chamber are not high, and a complex vacuum system is not required, and the cost of the equipment is lower;

[0039] When using normal pressure epitaxial equipment to grow ultra-high resistance intrinsic epitaxy, the expansion coefficient of the material doped in the buried layer under normal pressure conditions is small, making it easier to suppress the diffusion of the buried layer. Therefore, even if high-temperature purge and low-temperature purge are not used, the diffusion of the buried layer can be suppressed, and long-term purge can be prevented from diffusing the buried layer doping.

[0040] S300: baking the semiconductor substrate based on a preset baking temperature;

[0041] Baking helps to activate the atoms on the surface of the substrate, making them more active and conducive to the epitaxial growth reaction; when the substrate is heated to a certain temperature, the chemical bond energy and activity of the surface atoms will change. For example, for some compound semiconductor substrates, the appropriate baking temperature can relax the chemical bonds of the surface atoms. During epitaxial growth, the gaseous source material is more likely to react with these active surface atoms, thereby growing a high-quality intrinsic epitaxial layer;

[0042] The baking temperature is a key parameter. If the temperature is too low, impurities may not be effectively removed and surface atoms may not be activated; but if the temperature is too high, the substrate material itself may be damaged.

[0043] In this embodiment, the preset baking temperature is 1120° C. to 1140° C., and in the process of growing the intrinsic epitaxial layer, the baking temperature in the reaction chamber is maintained at 1120° C. to 1140° C.; the baking temperature here is only a preferred implementation range, and is not intended to limit the protection scope of the present application. In other alternative implementations, other baking temperature ranges may also be used, which also fall within the protection scope of the present application;

[0044] S400: introducing a reaction source gas and hydrogen into the atmospheric pressure epitaxial growth equipment to grow an intrinsic epitaxial layer on the surface of the semiconductor substrate. During the intrinsic epitaxial growth process, hydrogen H2 can be used as a carrier gas to transport the reaction source gas to the substrate surface. The presence of hydrogen helps to reduce defects in the epitaxial layer. During the growth process, it can suppress some side reactions that may cause defects.

[0045] Intrinsic epitaxial growth refers to a growth method in which the epitaxial layer grown during the growth of semiconductor materials is the same as the substrate material and no impurities are deliberately introduced. Intrinsic semiconductors refer to pure semiconductor materials without the influence of impurities and defects. Their conductivity is mainly determined by the carriers (electrons and holes) generated by the intrinsic excitation of the material itself. In intrinsic epitaxial growth, the goal is to obtain an epitaxial layer with high-quality crystal structure and intrinsic electrical properties.

[0046] In this embodiment, the reaction source gas is trichlorosilane gas (TCS (SiHCL3)). Trichlorosilane can provide silicon atoms to grow a silicon epitaxial layer on the surface of the substrate for manufacturing high-performance semiconductor devices. For example, in the manufacturing process of silicon-based transistors, a high-quality silicon epitaxial layer is provided to improve the electrical properties of the device. Trichlorosilane can obtain a high-purity product through a sophisticated chemical synthesis and purification process. In the semiconductor industry, a high-purity silicon source is crucial. This high purity can ensure the quality of the grown silicon epitaxial layer or polysilicon, reduce the interference of impurities on the electrical properties of semiconductor devices, and thus improve the performance and reliability of the device. In addition, trichlorosilane has a high chemical activity. Under appropriate temperature and reaction conditions, it can easily decompose and release silicon atoms. This high activity enables it to effectively deposit silicon atoms on the surface of the substrate and grow a high-quality silicon epitaxial layer, and the reaction rate can be controlled by adjusting parameters such as temperature and gas flow.

[0047] Due to the high activity and good deposition performance of trichlorosilane, it can grow a silicon epitaxial layer of a certain thickness in a relatively short time. The physical and chemical properties of trichlorosilane enable it to adapt to the operating conditions of existing atmospheric pressure epitaxial equipment, such as temperature range, pressure range and gas flow control. And the raw materials for the preparation of trichlorosilane are relatively easy to obtain. It is mainly prepared by the reaction of silicon powder and hydrogen chloride. Silicon powder and hydrogen chloride have a relatively stable supply in the industry and the cost is relatively low.

[0048] By adopting the present application, a normal pressure epitaxial device is selected to grow the epitaxial layer, which makes it easier to suppress the diffusion of the buried layer, eliminate the high temperature and low temperature purge processes, prevent the buried layer doping from being diffused out by long-term purge, simplify the intrinsic epitaxial layer growth process, and improve the intrinsic epitaxial layer growth efficiency, which can meet the production process requirements of the ultra-high resistance intrinsic epitaxial layer; the present application adopts normal pressure epitaxial equipment, which has a simpler equipment structure and lower cost than the reduced pressure epitaxial equipment in the prior art, and is also conducive to reducing the preparation cost of semiconductor structures and semiconductor devices. The intrinsic epitaxial growth method of the present application can be applied to the preparation of semiconductor structures with intrinsic epitaxial layers in various types of semiconductor devices, such as high-frequency devices, power devices, integrated chips, sensors, etc., so the intrinsic epitaxial growth method has a wide range of applications.

[0049] In addition, compared with decompression or other complex epitaxial equipment, atmospheric pressure epitaxial equipment has a relatively simple structure and no complex vacuum system, making the operation and maintenance of the equipment relatively easy. In terms of operation, since there is no need for complex vacuum pumping, filling, and maintaining vacuum, the operation process of the equipment is simpler, the technical requirements for operators are relatively low, the possibility of operating errors is reduced, and the training cost and time of operators are also reduced. Atmospheric pressure epitaxial equipment does not have the potential safety risks brought by high vacuum systems, such as vacuum leakage, vacuum pump failure, and other safety issues that may be caused. The equipment operates under normal pressure, and the operator can observe the operating status of the equipment more intuitively, discover and deal with potential safety hazards in a timely manner, and improve the safety and reliability of the equipment. During the equipment maintenance and maintenance process, atmospheric pressure epitaxial equipment is also relatively safe, and the operator does not need to operate in a high vacuum environment, reducing the possibility of safety accidents caused by improper operation.

[0050] Figure 2 It is a schematic diagram of the intrinsic epitaxial growth process of an embodiment of the present application. Among them, the convection layer refers to the area where the reaction gas forms convection under the action of thermal drive or other dynamic factors (such as gas flow). In this area, the movement of gas molecules is relatively complex, including various modes of movement such as rising, falling and translation. Good convection can make the reaction gas more evenly distributed in the reaction chamber, which is conducive to the uniformity of epitaxial layer growth. Factors such as the temperature distribution of the reaction chamber, the position and flow of the gas inlet and outlet will affect the characteristics of the convection layer. The present application improves the uniformity of epitaxial layer growth by maintaining the temperature during epitaxial growth at 1120℃~1140℃ and designing the flow rate of the reaction gas. The retention layer refers to a thin gas layer in the reaction chamber, close to the surface of the substrate. In this area, the diffusion rate of gas molecules is relatively slow, and the flow state of the gas is different from that of the convection layer. The existence of the retention layer has an important influence on the epitaxial growth process. The reaction gas needs to pass through the retention layer to reach the substrate surface for reaction. The thickness of the retention layer and the gas diffusion characteristics will affect the supply rate of the reaction gas. The characteristics of the retention layer can be improved by increasing the temperature of the reaction chamber, increasing the pressure of the reaction gas, or optimizing the type of reaction gas. The present application maintains the temperature of the epitaxial growth process at 1120°C to 1140°C, selects trichlorosilane gas and hydrogen as reaction gases, and designs the flow rate of the reaction gas, which is conducive to improving the characteristics of the retention layer, thereby improving the characteristics of the grown intrinsic epitaxial layer.

[0051] Figure 3 This is a schematic diagram of the temperature change when growing the intrinsic epitaxial layer using high-temperature purge and low-temperature purge. Figure 4 It is a schematic diagram of temperature change during the growth process of the intrinsic epitaxial layer in one embodiment of the present application. Figure 3 and Figure 4 The ordinate represents the temperature in the reaction chamber, and the abscissa represents each process stage (Time). In the prior art, high-temperature purge can effectively ensure the quality of the epitaxial layer. Low-temperature purge is widely used in the pretreatment and post-treatment stages of various intrinsic epitaxial growth processes, and is a basic cleaning and protection measure. In the process of intrinsic epitaxial growth, "purge" mainly refers to the purging process, which is used to remove impurity gases, residual reaction gases or other unnecessary substances in the reaction chamber. High-temperature purge and low-temperature purge are mainly divided according to the temperature during purging. High-temperature purge usually refers to a purging operation performed at a relatively high temperature. This temperature is generally close to or in the reaction temperature range during epitaxial growth, which may be between several hundred degrees Celsius and more than one thousand degrees Celsius. The specific temperature depends on the semiconductor material grown and the process requirements. For example, in the epitaxial growth process of silicon (Si), the high-temperature purge temperature may be around 1000-1200°C. Low-temperature purge is a purge performed at a lower temperature, which is usually lower than the epitaxial growth reaction temperature, and may be between room temperature and several hundred degrees Celsius. For example, in some compound semiconductor epitaxial growth processes, the low-temperature purge temperature can be between 50-200°C. Figure 3 and Figure 4 It can be seen that in the process flow of the prior art, multiple steps of high-temperature purge and multiple steps of low-temperature purge are required, the process flow is very complicated, and the growth efficiency is low. In the process of intrinsic epitaxial layer growth in this application, multiple steps of high-temperature purge and multiple steps of low-temperature purge are removed, and only a baking stage is set, which simplifies the process flow.

[0052] In this embodiment, the flow rate of the reaction gas is further adjusted to increase the growth rate of the intrinsic epitaxial layer. Specifically, the gas flow rate of trichlorosilane gas is increased in the present application, and the hydrogen flow rate is reduced. The gas flow rate of trichlorosilane gas is set to about 2 times the previous value, and the gas flow rate of hydrogen gas is reduced from 6X to 4X. By reducing the flow rate of hydrogen, the present application is conducive to thinning the retention layer, and is more conducive to the diffusion of buried layer materials into the troposphere and being carried away, reducing the impact during the epitaxial growth process. At the same time, reducing hydrogen can also increase the growth rate of the epitaxial layer. By increasing the growth rate of the epitaxial layer, the growth rate of the epitaxial layer is made greater than the diffusion rate of the buried layer to achieve the purpose of increasing the resistivity of the epitaxial layer.

[0053] For example, in this embodiment, the flow rate of the trichlorosilane gas is set to 4L to 6L per minute, and can be further optionally set to 5L per minute. The flow rate of the hydrogen is set to 40 to 45L per minute. The numerical values ​​of the flow rate of the trichlorosilane gas and the flow rate of the hydrogen are only examples and are not intended to limit the scope of protection of this application. In other alternative embodiments, the flow rate of the trichlorosilane gas and the flow rate of the hydrogen can also use other numerical values, which also fall within the scope of protection of this application. Therefore, in this embodiment, by selecting the reaction gas and adjusting the flow rate of the reaction gas, the growth rate of the intrinsic epitaxial layer is increased, so that the growth rate of the intrinsic epitaxial layer reaches 2.2 to 3μm / min, so that the growth rate of the intrinsic epitaxial layer is greater than the diffusion rate of the buried layer to achieve the purpose of increasing the resistivity of the epitaxial layer, thereby being more suitable for the preparation of ultra-high resistance intrinsic epitaxial layers.

[0054] In this embodiment, the intrinsic epitaxial layer is an ultra-high resistance intrinsic epitaxial layer, wherein the surface resistivity of the intrinsic epitaxial layer is greater than 1000 ohm·cm, and the resistivity at a surface depth of 2.5 μm is greater than 400 ohm·cm. Figure 5 This is a schematic diagram of the change in resistivity of an intrinsic epitaxial layer grown by the present invention with depth according to an embodiment of the present invention, wherein the abscissa is the surface depth of the intrinsic epitaxial layer in μm, and the ordinate is the resistivity in ohm·cm. Figure 5 A1-A7 represent different groups of data for the experiment. Figure 5 It can be seen that after adopting the intrinsic epitaxial growth method of the present application, by selecting the normal pressure epitaxial equipment, the reaction gas and the design of the reaction gas flow rate, the ultra-high resistance epitaxial layer is grown on the high-concentration buried layer substrate, and the resistivity at the surface depth of 2.5μm is greater than 400 ohm cm, and the surface resistivity is greater than 1000 ohm cm. In addition, the present application greatly improves the preparation efficiency of the intrinsic epitaxial layer, so that the WPH (Wafer Per Hour, wafer per hour) of the semiconductor structure prepared by the intrinsic epitaxial layer is optimized from 2.13 to 4.28, an increase of 100%. The improvement of WPH is directly related to the production capacity of the semiconductor factory. For large-scale semiconductor manufacturing companies, increasing WPH can produce more chips in the same time to meet the market's growing demand for semiconductor products. Higher WPH also helps to amortize fixed costs. Semiconductor manufacturing equipment is expensive, and fixed costs such as plant construction are also high. By increasing the number of wafers processed per hour, the production cost per unit wafer can be reduced.

[0055] The second aspect of the present application provides a semiconductor structure obtained by the intrinsic epitaxial growth method described in the first aspect. The semiconductor structure may be a part of a hierarchical structure in a semiconductor device. The semiconductor structure includes at least a substrate and an intrinsic epitaxial layer formed on the surface of the substrate, and the intrinsic epitaxial layer is prepared by steps S100 to S400 of the above-mentioned intrinsic epitaxial growth method. In this embodiment, the intrinsic epitaxial layer is an ultra-high resistance intrinsic epitaxial layer. The surface resistivity of the intrinsic epitaxial layer is greater than 1000 ohms·cm, and the resistivity at a surface depth of 2.5 μm is greater than 400 ohms·cm. By using the intrinsic epitaxial growth method of the present application to grow an ultra-high resistance intrinsic epitaxial layer in the semiconductor structure of a semiconductor device, the growth quality and growth efficiency of the semiconductor structure can be improved, a higher WPH can be obtained, the preparation efficiency of the semiconductor structure can be improved, and the preparation cost of the semiconductor device can be reduced.

[0056] The semiconductor devices here are, for example, high-frequency devices, power devices, integrated chips, sensors, etc. For example, in integrated circuit manufacturing, the ultra-high resistance intrinsic epitaxial layer can be used as part of the isolation structure, which can reduce the parasitic capacitance and parasitic resistance between different devices and improve the integration and performance of the circuit; in power devices such as transistors, the ultra-high resistance intrinsic epitaxial layer can be used to optimize the drift region of the device. By adjusting the thickness and resistance characteristics of the intrinsic epitaxial layer, the withstand voltage and on-resistance of the device can be controlled. By adopting the intrinsic epitaxial growth method of the present application to grow the ultra-high resistance intrinsic epitaxial layer in the semiconductor structure of the semiconductor device, the growth quality and growth efficiency of the intrinsic epitaxial layer in the semiconductor structure can be improved, a higher WPH can be obtained, the preparation efficiency of the semiconductor device can be improved, and the preparation cost of the semiconductor device can be reduced.

[0057] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. An intrinsic epitaxial growth method, characterized in that: include: Providing a semiconductor substrate, wherein a buried layer is formed in the semiconductor substrate; Placing the semiconductor substrate in a normal pressure epitaxial growth device; Baking the semiconductor substrate based on a preset baking temperature; Reaction source gas and hydrogen are introduced into the atmospheric pressure epitaxial growth equipment to grow an intrinsic epitaxial layer on the surface of the semiconductor substrate.

2. The intrinsic epitaxial growth method according to claim 1, characterized in that: The preset baking temperature is 1120°C to 1140°C.

3. The intrinsic epitaxial growth method according to claim 1, characterized in that: The reaction source gas is trichlorosilane gas.

4. The intrinsic epitaxial growth method according to claim 3, characterized in that: The flow rate of the trichlorosilane gas is set to 4L to 6L per minute.

5. The intrinsic epitaxial growth method according to claim 1, characterized in that: The flow rate of the hydrogen is set to 40-45 L per minute.

6. The intrinsic epitaxial growth method according to claim 1, characterized in that: The buried layer in the semiconductor substrate is a high-concentration buried layer with a concentration greater than 2E15.

7. The intrinsic epitaxial growth method according to claim 1, characterized in that: The intrinsic epitaxial layer is an ultra-high resistance intrinsic epitaxial layer.

8. The intrinsic epitaxial growth method according to claim 7, characterized in that: The surface resistivity of the intrinsic epitaxial layer is greater than 1000 ohm·cm, and the resistivity at a surface depth of 2.5 μm is greater than 400 ohm·cm.

9. A semiconductor structure, characterized in that: The method is obtained by using the intrinsic epitaxial growth method according to any one of claims 1 to 8.

10. A semiconductor device, characterized in that: Comprising the semiconductor structure as claimed in claim 9.

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