Preparation method of bonded wafer
During the preparation of the SOI wafer, a smooth top silicon layer is formed using ion implantation and silicon etching processes, and a planarization process is carried out below 1100°C, which solves the problem of slip line defects caused by high temperature processes and significantly improves the quality of the wafer edge.
Patent Information
- Application Number
- CN202411941058.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-11
AI Technical Summary
During the high-temperature planarization process of SOI wafers, internal defects in the crystal are easily generated or amplified, resulting in serious slip line defects on the edges of the wafer.
By providing the device wafer and the support wafer, an ion implantation process is performed after the oxide layer is formed, bonded wafers are formed, and peeled off to retain the top silicon layer. The top silicon layer is then subjected to a silicon etching process to reduce surface roughness and a planarization process is performed below 1100°C.
The surface roughness of the top silicon layer is reduced, making the surface smoother before the planarization process, reducing the temperature of the planarization process, thereby reducing the thermal stress and improving the slip line defects at the edge of the wafer.
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Figure CN119811992A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a bonded wafer. Background Art
[0002] Silicon on insulator (SOI) technology has now become one of the mainstream products in most electronic materials fields. It can replace bulk single crystals in some semiconductor devices to significantly improve certain electrical properties of the devices. Therefore, it has received widespread attention and research, and the manufacture of high-quality SOI wafers has become an important development trend.
[0003] As the size of SOI wafers increases, the gravity and stress they are subject to during the heat treatment process also increase significantly, which makes it easier for heat treatment, especially high-temperature processes exceeding 1100°C, to produce or amplify internal crystal defects, which can easily cause SOI wafers to be scrapped. The most obvious and influential type of defect is the slip line defect. In the preparation process of SOI wafers, the high-temperature flattening process exceeding 1100°C is an important cause of slip line defects on the edge of the wafer, and the higher the temperature, the more serious the edge slip line. Summary of the invention
[0004] The object of the present invention is to provide a method for preparing a bonded wafer to improve the slip line defect at the edge of the wafer.
[0005] In order to achieve the above object, the present invention provides a method for preparing a bonded wafer, comprising:
[0006] Providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer;
[0007] performing an ion implantation process on the device wafer;
[0008] Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off a portion of the device wafer, and retaining a portion of the device wafer as a top silicon layer after stripping;
[0009] Performing a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer;
[0010] A planarization process is performed on the top silicon layer, and a temperature of the planarization process is less than or equal to 1100° C.
[0011] Optionally, the silicon etching process is a wet etching process.
[0012] Optionally, the etchant of the silicon etching process includes HF and O3.
[0013] Optionally, the concentration of HF is 0.5% to 10%, where the percentage is mass percentage.
[0014] Optionally, the concentration of O3 is 10PPM to 30PPM.
[0015] Optionally, after performing the silicon etching process, the thickness of the top silicon layer removed is
[0016] Optionally, the temperature of the planarization process is 1000°C to 1100°C.
[0017] Optionally, before performing the silicon etching process, the thickness of the top silicon layer is
[0018] Optionally, before performing the planarization process, a thermal strengthening process is also performed on the bonded wafer.
[0019] Optionally, after performing the planarization process, a thinning process is further performed on the top silicon layer, and the thinning process includes a furnace tube oxidation process and a wet etching process performed in sequence to thin the top silicon layer.
[0020] In the preparation method of the bonded wafer provided by the present invention, it includes: providing a device wafer and a support wafer, an oxide layer is formed on the surface of the device wafer and / or the support wafer, and performing an ion implantation process on the device wafer; bonding the side of the device wafer after ion implantation with the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip part of the device wafer, and retaining part of the device wafer as the top silicon layer after stripping; performing a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer; performing a flattening process on the top silicon layer, and the temperature of the flattening process is less than or equal to 1100°C. In the present invention, performing a silicon etching process on the top silicon layer after stripping can reduce the surface roughness of the top silicon layer, so that the surface of the top silicon layer is smoother before the flattening process, and when performing the flattening process, the temperature of the flattening process can be reduced to reduce thermal stress, thereby improving the slip line defects at the edge of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A flow chart of a method for preparing a bonded wafer provided in one embodiment of the present invention.
[0022] Figure 2 This is an atomic force microscope (AFM) image of the top silicon layer after peeling in the method for preparing a bonded wafer provided by an embodiment of the present invention.
[0023] Figure 3An atomic force microscope image of the top silicon layer after silicon etching in the method for preparing a bonded wafer provided in one embodiment of the present invention.
[0024] Figure 4 Map diagram of edge slip lines in Comparative Example 1 and Comparative Example 4 in the method for preparing a bonded wafer provided by an embodiment of the present invention.
[0025] Figure 5 Map diagram of edge slip lines in Comparative Examples 2 and 3 of the method for preparing a bonded wafer provided in one embodiment of the present invention. DETAILED DESCRIPTION
[0026] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0027] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0028] Figure 1 This is a flow chart of the method for preparing a bonded wafer provided in this embodiment. Please refer to Figure 1 , this embodiment provides a method for preparing a bonded wafer, comprising:
[0029] Step S1: providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer;
[0030] Step S2: performing an ion implantation process on the device wafer;
[0031] Step S3: bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off a portion of the device wafer, and retaining a portion of the device wafer as a top silicon layer after stripping;
[0032] Step S4: performing a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer;
[0033] Step S5: performing a planarization process on the top silicon layer, and the temperature of the planarization process is less than or equal to 1100° C.
[0034] The following is a detailed description of the method for preparing the bonded wafer provided in this embodiment.
[0035] Execute step S1: provide a device wafer and a support wafer, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 500μm to 800μm, for example, 775μm, and the thickness difference between the device wafer and the support wafer can be less than 0.5μm, and the thickness difference is the difference between the maximum thickness and the minimum thickness, but is not limited thereto. Clean and oxidize the device wafer and / or the support wafer in sequence to form an oxide layer on the surface of the device wafer and / or the support wafer, and the thickness of the oxide layer can be less than It is not limited thereto; specifically, an oxide layer may be formed on the surface of a device wafer, an oxide layer may be formed on the surface of a support wafer, or an oxide layer may be formed on the surfaces of a device wafer and a support wafer.
[0036] Execute step S2: perform an ion implantation process on the device wafer to form an ion implantation layer in the device wafer. The ion implantation layer mainly plays a role in stripping and splitting. The implanted ions in the ion implantation process may include hydrogen ions (single hydrogen ion implantation may be used), but are not limited thereto. Other inert ions may also be used. In this embodiment, the implantation beam current of the ion implantation process may be 10 mA to 20 mA, the implantation energy of the ion implantation process may be 45 keV to 65 keV, and the implantation dose of the ion implantation process may be 1×10 16 atom / cm 2 ~6×10 16 atom / cm 2 .
[0037] Execute step S3: bond the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, specifically, bond the side of the device wafer with the ion implantation layer to the support wafer, and the bonding method may be hydrophilic bonding. After bonding, peel and split the device wafer from the ion implantation layer of the device wafer to peel off a portion of the thickness of the device wafer, and retain a portion of the device wafer on the support wafer; after peeling, the retained portion of the device wafer serves as the top silicon layer, the support wafer serves as the substrate layer, and the oxide layer between the device wafer and the support wafer serves as the insulating buried oxide layer. In this embodiment, after peeling and before performing the silicon etching process, the thickness of the top silicon layer may be After stripping, the bonded wafer may be cleaned on both sides by a single-wafer cleaning machine.
[0038] Execute step S4: perform a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer. In this embodiment, the silicon etching process is a wet etching process, and the etchant of the silicon etching process includes HF and O3. The concentration of HF can be 0.5% to 10%, and the percentage is the mass percentage. The concentration of O3 can be 10PPM to 30PPM (PPM is parts per million by mass); after the silicon etching process is performed, the removal thickness of the top silicon layer is preferably If the thickness of the top silicon layer removed is too large, it will affect the thickness difference of the top silicon layer. If the thickness of the top silicon layer removed is too small, a good flat surface cannot be obtained. Therefore, the thickness of the top silicon layer removed is preferably In this embodiment, a silicon etching process is performed on the top silicon layer after stripping. The silicon etching process can reduce the surface roughness of the top silicon layer, so that the surface of the top silicon layer is smoother (having a certain degree of smoothness) before the planarization process, and planarization treatment is required later.
[0039] Figure 2 A schematic diagram of the surface roughness after peeling in the method for preparing a bonded wafer provided in this embodiment, Figure 3 This is a schematic diagram of the surface roughness of the bonded wafer after silicon etching in the method for preparing the bonded wafer provided in this embodiment. Figure 2 and Figure 3 , the figure illustrates an atomic force microscope image of a top silicon layer of 10μm*10μm after stripping and silicon etching. The conditions of the preparation process are to provide a device wafer and a support wafer, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 773μm to 777μm, and the thickness difference between the device wafer and the support wafer is less than 0.5μm; the device wafer is cleaned and oxidized to form an oxide layer on the surface of the device wafer, and the thickness of the oxide layer is The device wafer is subjected to an ion implantation process. The implanted ions in the ion implantation process are hydrogen ions. The implantation energy of the ion implantation process may be 60 keV. The implantation dose of the ion implantation process may be 5.5×10 16 atom / cm 2 ; Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off part of the device wafer, retaining part of the device wafer as the top silicon layer after stripping, and then performing a silicon etching process on the bonded wafer in sequence, wherein the silicon etching process adopts the etching parameters in this embodiment, and the thickness of the top silicon layer removed is Combination Figure 2 It can be seen that the surface of the top silicon layer after peeling is rough (surface roughness Rq is about 8nm), with large bumps (manifested in the more obvious contrast in color depth); when performing the silicon etching process to remove the top silicon layer After the thickness of Figure 3 It can be seen that the surface roughness of the top silicon layer has improved after silicon etching (surface roughness Rq is about 3.5nm), and the undulations are smaller than those of Figure 2 is smaller, indicating that the silicon etching process is able to reduce the surface roughness of the top silicon layer.
[0040] Furthermore, before executing the planarization process, a thermal strengthening process is also performed on the bonded wafer. The strengthening temperature can be 900℃~1250℃, the strengthening time can be 0.5h~3h, and an oxygen-containing or hydrogen-containing inert gas (the inert gas can be Ar, N2, He) is used during strengthening, but it is not limited to this.
[0041] Execute step S5: perform a planarization process (high-temperature non-contact planarization) on the top silicon layer, and the temperature of the planarization process is less than or equal to 1100°C. In the prior art, the temperature of the planarization process is higher than 1100°C (generally about 1200°C), and the planarization process exceeding 1100°C will cause serious slip line defects at the edge of the wafer. In this embodiment, since the silicon etching process can reduce the surface roughness of the top silicon layer, the surface of the top silicon layer is smoother before the planarization process. When performing the planarization process, the temperature of the planarization process can be reduced (less than or equal to 1100°C) to reduce thermal stress, thereby improving the slip line defects at the edge of the wafer. In this embodiment, the temperature of the planarization process cannot be too high or too low. If the temperature of the planarization process is too high, greater thermal stress will be generated. If the temperature of the planarization process is too low, a better planarized surface cannot be obtained. Therefore, the temperature of the planarization process is preferably 1000°C to 1100°C.
[0042] Furthermore, after executing the planarization process, a thinning process is also performed on the top silicon layer. The thinning process includes a furnace tube oxidation process and a wet etching process performed in sequence to thin the top silicon layer. The furnace tube oxidation process includes a dry oxygen oxidation process and / or a wet oxygen oxidation process. The furnace tube oxidation process is used to oxidize the top silicon layer in the bonded wafer, thereby forming an oxide layer on the surface of the top silicon layer. Subsequently, a wet etching process can be used to remove the formed oxide layer to achieve thinning of the top silicon layer. The thinning of the top silicon layer is completed according to the target thickness value of the top silicon layer.
[0043] Four comparative examples are provided below to further illustrate the method for preparing the bonded wafer provided in this embodiment.
[0044] In comparative example 1, a device wafer and a support wafer are provided, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 773 μm to 777 μm, and the thickness difference between the device wafer and the support wafer is less than 0.5 μm; the device wafer is cleaned and oxidized to form an oxide layer on the surface of the device wafer, and the thickness of the oxide layer is The device wafer is subjected to an ion implantation process. The implanted ions in the ion implantation process are hydrogen ions. The implantation energy of the ion implantation process may be 60 keV. The implantation dose of the ion implantation process may be 5.5×10 16 atom / cm 2 ; The side of the device wafer after ion implantation is bonded to the support wafer to form a bonded wafer, and the bonded wafer is peeled off to peel off part of the device wafer. After peeling, part of the device wafer is retained as the top silicon layer. The bonded wafer is then subjected to a thermal strengthening process, a planarization process and a thinning process in sequence to make the top silicon layer reach the target thickness value, wherein the temperature of the planarization process is 1200°C.
[0045] In comparative example 2, a device wafer and a support wafer are provided, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 773 μm to 777 μm, and the thickness difference between the device wafer and the support wafer is less than 0.5 μm; the device wafer is cleaned and oxidized to form an oxide layer on the surface of the device wafer, and the thickness of the oxide layer is The device wafer is subjected to an ion implantation process. The implanted ions in the ion implantation process are hydrogen ions. The implantation energy of the ion implantation process may be 60 keV. The implantation dose of the ion implantation process may be 5.5×10 16 atom / cm 2 ; Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off part of the device wafer, retaining part of the device wafer as the top silicon layer after stripping, and then sequentially performing a silicon etching process, a thermal strengthening process, a flattening process and a thinning process on the bonded wafer to make the top silicon layer reach a target thickness value, wherein the silicon etching process adopts the etching parameters in this embodiment, and the removal thickness of the top silicon layer is The temperature of the planarization process is 1100°C.
[0046] In comparative example 3, a device wafer and a support wafer are provided, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 773 μm to 777 μm, and the thickness difference between the device wafer and the support wafer is less than 0.5 μm; the device wafer is cleaned and oxidized to form an oxide layer on the surface of the device wafer, and the thickness of the oxide layer is The device wafer is subjected to an ion implantation process. The implanted ions in the ion implantation process are hydrogen ions. The implantation energy of the ion implantation process may be 60 keV. The implantation dose of the ion implantation process may be 5.5×10 16 atom / cm 2; Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off part of the device wafer, retaining part of the device wafer as the top silicon layer after stripping, and then sequentially performing a silicon etching process, a thermal strengthening process, a flattening process and a thinning process on the bonded wafer to make the top silicon layer reach a target thickness value, wherein the silicon etching process uses the etchant in this embodiment, but the removal thickness of the top silicon layer is The temperature of the planarization process is 1100°C.
[0047] In comparative example 4, a device wafer and a support wafer are provided, both of which are silicon wafers, and the thickness of the device wafer and the support wafer can be 773 μm to 777 μm, and the thickness difference between the device wafer and the support wafer is less than 0.5 μm; the device wafer is cleaned and oxidized to form an oxide layer on the surface of the device wafer, and the thickness of the oxide layer is The device wafer is subjected to an ion implantation process. The implanted ions in the ion implantation process are hydrogen ions. The implantation energy of the ion implantation process may be 60 keV. The implantation dose of the ion implantation process may be 5.5×10 16 atom / cm 2 ; Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off part of the device wafer, retaining part of the device wafer as the top silicon layer after stripping, and then sequentially performing a silicon etching process, a thermal strengthening process, a flattening process and a thinning process on the bonded wafer to make the top silicon layer reach a target thickness value, wherein the silicon etching process uses the etchant in this embodiment, but the removal thickness of the top silicon layer is The temperature of the planarization process is 1200°C.
[0048] Table 1 is a comparison table of the results of Comparative Examples 1 to 4. Figure 4 Map diagram of edge slip lines in Comparative Example 1 and Comparative Example 4 in the method for preparing a bonded wafer provided in this embodiment, Figure 5 Map of edge slip lines in Comparative Example 2 and Comparative Example 3 in the preparation method of the bonded wafer provided in this embodiment. Please refer to Table 1. In Comparative Example 1, no silicon etching process is performed, and a high temperature of 1200°C is used for the flattening process. After flattening, the surface roughness of the top silicon layer is good, but the number of edge slip lines of the wafer is relatively large, about 40 (such as Figure 4 In comparative example 2, a silicon etching process is performed after stripping to remove the top silicon layer. The thickness is 1000℃, and then the planarization process is carried out at a high temperature of 1100℃. After planarization, the surface roughness of the top silicon layer is good, and the number of edge slip lines of the wafer is very small, about 1 (such as Figure 5The green bright spot circled by the white circular dotted frame in the middle) can be ignored. In comparative example 3, a silicon etching process is performed after stripping to remove the top silicon layer. The thickness is 1000℃, and then the planarization process is carried out at a high temperature of 1100℃. After planarization, the surface roughness of the top silicon layer is good, and the number of edge slip lines of the wafer is very small, about 1 (such as Figure 5 The green bright spot circled by the white circular dotted frame in the middle) may be negligible, but the thickness difference of the top silicon layer is about 40μm. In comparative example 4, a silicon etching process is performed after stripping to remove the top silicon layer. The thickness of the wafer was then planarized at 1200°C. After planarization, the surface roughness of the top silicon layer was good, but the number of edge slip lines of the wafer was large, about 40 (such as Figure 4 The green highlight is circled by the white circular frame).
[0049]
[0050] Table 1. Comparative Example 1 to Comparative Example 4 Results Comparative Example 1
[0051] Therefore, by comparing the surface roughness of the top silicon layer after planarization, the number of edge slip lines, and the thickness difference of the top silicon layer, it can be seen that Comparative Example 2 is the best technical solution. Comparative Example 2 is the same as the content defined in this embodiment, indicating that the silicon etching process is performed after stripping, and the removal thickness of the top silicon layer in the silicon etching process is Combining the planarization process with a high temperature of less than or equal to 1100°C can improve the slip line defects at the edge of the wafer, and the top silicon layer has better surface roughness and thickness difference.
[0052] In summary, the preparation method of the bonded wafer provided by the present invention includes: providing a device wafer and a support wafer, an oxide layer is formed on the surface of the device wafer and / or the support wafer, and performing an ion implantation process on the device wafer; bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off part of the device wafer, and retaining part of the device wafer as the top silicon layer after stripping; performing a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer; performing a flattening process on the top silicon layer, and the temperature of the flattening process is less than or equal to 1100°C. In the present invention, performing a silicon etching process on the top silicon layer after stripping can reduce the surface roughness of the top silicon layer, so that the surface of the top silicon layer is smoother before the flattening process, and when performing the flattening process, the temperature of the flattening process can be reduced to reduce thermal stress, thereby improving the slip line defects at the edge of the wafer.
[0053] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A method for preparing a bonded wafer, characterized in that: include: Providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer; performing an ion implantation process on the device wafer; Bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer, and performing a stripping process on the bonded wafer to strip off a portion of the device wafer, and retaining a portion of the device wafer as a top silicon layer after stripping; Performing a silicon etching process on the top silicon layer to remove a portion of the thickness of the top silicon layer and reduce the surface roughness of the top silicon layer; A planarization process is performed on the top silicon layer, and a temperature of the planarization process is less than or equal to 1100° C.
2. The method for preparing a bonded wafer according to claim 1, wherein: The silicon etching process is a wet etching process.
3. The method for preparing a bonded wafer according to claim 2, wherein: The etchant of the silicon etching process includes HF and O3.
4. The method for preparing a bonded wafer according to claim 3, wherein: The concentration of HF is 0.5% to 10%, where the percentage is mass percentage.
5. The method for preparing a bonded wafer according to claim 3, wherein: The concentration of O3 is 10PPM to 30PPM.
6. The method for preparing a bonded wafer according to claim 1, wherein: After the silicon etching process is performed, the thickness of the top silicon layer removed is 7. The method for preparing a bonded wafer according to claim 1, wherein: The temperature of the planarization process is 1000°C to 1100°C.
8. The method for preparing a bonded wafer according to claim 1, wherein: Before performing the silicon etching process, the thickness of the top silicon layer is 9. The method for preparing a bonded wafer according to claim 1, wherein: Before performing the planarization process, a thermal strengthening process is also performed on the bonded wafer.
10. The method for preparing a bonded wafer according to claim 1, wherein: After performing the planarization process, a thinning process is further performed on the top silicon layer, wherein the thinning process includes a furnace tube oxidation process and a wet etching process performed in sequence to thin the top silicon layer.