Frame substrate and manufacturing method

Abstract

The present disclosure provides a frame substrate and a manufacturing method. Specifically, the frame substrate comprises a dielectric layer, a conductive copper pillar and a circuit layer. The dielectric layer comprises at least one cavity, the cavity penetrates through the dielectric layer. The conductive copper pillar is located in the dielectric layer. The circuit layer is located on the surface of the dielectric layer and connected to the conductive copper pillar. Such technical solution, the conductive copper pillar in the frame substrate is connected to the circuit layer, and after embedding the components, it is not necessary to open the window to connect the conductive copper pillar again, which helps to save the processing technology.

Description

Technical Field

[0001] This disclosure relates to the field of packaging technology, and in particular to a frame substrate and its manufacturing method. Background Technology

[0002] With technological advancements, electronic products are widely used in all aspects of production and daily life. At the same time, users not only demand increasingly higher performance from electronic products, but also smaller and thinner dimensions. These demands lead to increasingly complex circuits in electronic components and circuit boards, making integration, miniaturization, systematization, and multifunctionality inevitable trends. In improving the functionality and further miniaturizing of electronic products, more efficient and precise packaging of integrated circuits and components plays a crucial role, with embedded packaging of components being a key area for breakthroughs. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to provide a frame substrate and a method for manufacturing it.

[0004] To achieve the above objectives, this disclosure provides a method for manufacturing a frame substrate, comprising:

[0005] (a) A support plate is provided, wherein a metal layer is disposed on the support plate;

[0006] (b) A first photoresist pattern layer comprising a conductive copper pillar window and a sacrificial copper wall window is formed on the metal layer of the carrier plate;

[0007] (c) A conductive copper pillar is formed in the conductive copper pillar opening, a sacrificial copper wall is formed in the sacrificial copper wall opening, and the first photoresist pattern layer is removed;

[0008] (d) A laminated dielectric layer; wherein the thickness of the dielectric layer is greater than the height of the conductive copper pillar;

[0009] (e) A window is made in the dielectric layer to form a blind hole that exposes the end face of the conductive copper pillar and a blind groove that exposes the end face of the sacrificial copper wall.

[0010] (f) A circuit layer connecting the conductive copper pillars is formed on the dielectric layer;

[0011] (g) Remove the support plate;

[0012] (h) Etching the sacrificial copper wall to form a frame substrate with a cavity; wherein the cavity penetrates the dielectric layer.

[0013] In some embodiments, the difference between the thickness of the dielectric layer and the height of the conductive copper pillar is 10 to 100 μm.

[0014] In some embodiments, the material of the dielectric layer includes at least one of free liquid crystal polymer, BT resin, semi-cured prepreg, ABF film, epoxy resin, and polyimide resin.

[0015] In some embodiments, step (b) includes:

[0016] The first photoresist pattern layer is obtained by attaching a film to the carrier plate, exposing it, and developing it.

[0017] In some embodiments, step (c) involves forming the conductive copper pillar and the sacrificial copper wall by electroplating.

[0018] In some embodiments, step (d) further includes:

[0019] A third copper layer is formed by laminating copper foil on the dielectric layer; wherein the third copper layer is located on the side of the dielectric layer away from the carrier plate.

[0020] In some embodiments, step (f) includes:

[0021] (f1) Chemical copper plating is performed on the through-hole;

[0022] (f2) A second photoresist pattern layer is formed by attaching a film to the third copper layer, exposing it, and developing it.

[0023] (f3) Electroplating fills the hollowed-out areas of the second photoresist pattern layer to form the circuit layer;

[0024] (f4) Remove the second photoresist pattern layer;

[0025] (f5) Etch the third copper layer.

[0026] In some embodiments, step (e) involves creating a window in the dielectric layer using a laser drilling process.

[0027] In some embodiments, the metal layer of the carrier plate includes a first copper layer and a second copper layer sequentially disposed on the carrier layer; the first copper layer and the second copper layer are physically bonded to each other;

[0028] Step (g) includes:

[0029] Separate the first copper layer and the second copper layer;

[0030] The dry film is used to mask the circuit layer, and the second copper layer is etched.

[0031] Based on the same inventive concept, this disclosure also provides a frame substrate, including a dielectric layer, conductive copper pillars, and a circuit layer; wherein, the dielectric layer includes at least one cavity, the cavity penetrating the dielectric layer; the conductive copper pillars are located within the dielectric layer and the height of the conductive copper pillars is less than the thickness of the dielectric layer; the circuit layer is located on the surface of the dielectric layer; the side of the dielectric layer near the circuit layer includes a blind via and the circuit layer is connected to the conductive copper pillars via the blind via.

[0032] As can be seen from the above, the frame substrate and manufacturing method provided in this disclosure, by creating blind vias on the exposed conductive copper pillar end faces and blind grooves on the exposed sacrificial copper wall end faces through opening windows in the dielectric layer, can achieve etching of the sacrificial copper wall without grinding and thinning, thus simplifying the process and reducing material costs. Furthermore, by omitting the grinding and thinning process, the uniformity of the dielectric layer surface can be effectively ensured, which helps improve the quality of subsequent embedded packaging. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This diagram illustrates a structural schematic of a frame substrate provided by related technologies;

[0035] Figure 2 This diagram illustrates a structural schematic of a frame substrate provided in an embodiment of the present disclosure;

[0036] Figures 3(a) to 3(k) This diagram shows a cross-sectional or top view of the intermediate structure of each step in a method for manufacturing a frame substrate according to an embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0038] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. In the accompanying drawings, for better understanding and ease of description, the thickness and shape of some layers and regions may be exaggerated.

[0039] When using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used in conjunction with the terms “closely to” or “directly.”

[0040] When one element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0041] Figure 1 A schematic diagram of a frame substrate provided by related technologies is shown. For example... Figure 1 As shown, the frame substrate 10 can be a polymer frame 16 and through-hole copper pillars 14. The polymer frame 16 includes an array of buried chip frames 12, and the through-hole copper pillars 14 are located on the outer periphery of the buried chip frames 12; wherein, the buried chip frames 12 are used to embed chips.

[0042] The method for fabricating the frame substrate 10 may include: a) obtaining a sacrificial carrier and applying a copper seed layer on the sacrificial carrier; b) applying a photolithographic dry film on the carrier; c) patterning the dry film and forming sacrificial copper pillar vias and copper vias; d) depositing copper on the carrier to form sacrificial copper pillars and via copper pillars; e) laminating the via copper pillars and sacrificial copper pillars with a polymer dielectric; f) thinning and planarizing the ends of the exposed copper pillars; g) removing the sacrificial carrier and seed layer; h) applying an etch-resistant photolithographic dry film and patterning to expose the sacrificial copper pillars; i) etching to remove the sacrificial copper pillars to form a buried core frame; j) removing the etch-resistant photolithographic dry film.

[0043] Using this technical solution results in a long processing flow and high cost; step e) requires pressing a relatively thick dielectric material and then thinning the plate, which consumes a lot of materials and is costly; moreover, the uniformity of the plate thickness is poor, which affects the quality of subsequent embedded devices on the frame substrate.

[0044] Furthermore, after the device is placed behind the embedded core frame 12, a dielectric layer is usually laminated to achieve embedding. The laminated dielectric layer often covers the through-hole copper pillar 14. In order to bring out the through-hole copper pillar 14, the dielectric layer also needs to be windowed to facilitate the connection between the circuit layer and the through-hole copper pillar 14. The whole process involves many steps and is complex.

[0045] In view of this, the frame substrate and manufacturing method provided in this disclosure, by creating blind vias on the exposed conductive copper pillar end faces and blind grooves on the exposed sacrificial copper wall end faces through opening windows in the dielectric layer, can achieve etching of the sacrificial copper wall without grinding and thinning, thus achieving the technical effect of simplifying the process flow and reducing material costs. Furthermore, by omitting the grinding and thinning process, the uniformity of the dielectric layer surface can be effectively ensured, which helps to improve the quality of subsequent embedded packaging.

[0046] In a first aspect, embodiments of this disclosure provide a frame substrate. For example... Figure 2 As shown, the frame substrate includes a dielectric layer 700, conductive copper pillars 301, and a circuit layer 600. The dielectric layer 700 includes at least one cavity 701 penetrating the dielectric layer 700. The conductive copper pillars 301 are located within the dielectric layer 700 and their height is less than the thickness of the dielectric layer 700. The circuit layer 600 is located on the surface of the dielectric layer 700, and the side of the dielectric layer 700 closest to the circuit layer 600 includes a blind via, allowing the circuit layer 600 to connect to the conductive copper pillars 301 via the blind via. Here, the cavity 701 is used to embed components, including but not limited to active components (e.g., transistors, IC chips, logic circuit elements, power amplifiers), passive components (capacitors, inductors, resistors), or combinations thereof.

[0047] In this technical solution, the conductive copper pillars 301 in the frame substrate are connected to the circuit layer 600 via blind vias. After subsequent embedding of components, there is no need to open windows again to connect the conductive copper pillars 301, which helps to save on processing technology.

[0048] Secondly, embodiments of this disclosure provide a method for manufacturing a frame substrate. Figures 3(a) to 3(k) This diagram shows a cross-sectional schematic of the intermediate structure of each step in a method for manufacturing a frame substrate according to an embodiment of the present disclosure. For example... Figures 3(a) to 3(k) As shown, the manufacturing method includes:

[0049] First, a support plate 100 is provided—step (a), as shown in Figure 3(a).

[0050] In some embodiments, the carrier plate 100 includes a carrier layer 101 and a first copper layer 102 and a second copper layer 103 sequentially disposed on the carrier layer 101; the first copper layer 102 and the second copper layer 103 are physically bonded to each other. It should be noted that the first copper layer 102 and the second copper layer 103 can be physically separated.

[0051] Next, a first photoresist pattern layer 200, including a conductive copper pillar window 201 and a sacrificial copper wall window 202, is formed on the carrier plate 100—step (b), as shown in Figures 3(b) and 3(c). Here, Figure 3(c) is a top view of Figure 3(b).

[0052] For example, a first photoresist pattern layer 200 is obtained by applying a film, exposing, and developing the film on a carrier plate 100.

[0053] Then, a conductive copper pillar 301 is formed in the conductive copper pillar window 201, a sacrificial copper wall 302 is formed in the sacrificial copper wall window 202, and the first photoresist pattern layer 200 is removed—step (c), as shown in Figures 3(d) and 3(e); wherein, Figure 3(e) is a top view of Figure 3(d).

[0054] In some embodiments, the conductive copper pillar 301 and the sacrificial copper wall 302 are formed by electroplating. It should be noted that the second copper layer 103 can be used as a seed layer for electroplating.

[0055] Next, a dielectric layer 400 and a third copper layer 401 are laminated; wherein the thickness of the dielectric layer 400 is greater than the height of the conductive copper pillar 301—step (d), as shown in Figure 3(f). It should be noted that the third copper layer 401 can be a thin copper foil, and the third copper layer 401 is located on the side of the dielectric layer 400 away from the carrier plate 100.

[0056] It should be understood that the height of the conductive copper pillar 301 and the height of the sacrificial copper wall 302 can be the same. In this case, if the thickness of the dielectric layer 400 is greater than the height of the conductive copper pillar 301, the thickness of the dielectric layer 400 is also greater than the height of the sacrificial copper wall 302.

[0057] Optionally, the material of the dielectric layer 400 includes one of the group consisting of free liquid crystal polymers, BT (bismaleimidetriazine) resin, prepreg, ABF (Ajinomoto Build-up) film, epoxy resin and polyimide resin, but this disclosure is not limited thereto.

[0058] Alternatively, the material of the dielectric layer 400 may include glass fiber.

[0059] In some embodiments, the difference between the thickness of the dielectric layer 400 and the height 301 of the conductive copper pillar is 10 to 100 μm, for example, 20 μm, 40 μm, 50 μm, 55 μm, 70 μm, or 100 μm.

[0060] Laminating a third copper layer 401 onto the dielectric layer 400 allows the dielectric layer to be sandwiched between the upper and lower metal layers (e.g., between the second copper layer 103 and the third copper layer 401). Since the metal layers have the same coefficient of thermal expansion, when the dielectric layer 400 is thermo-cured, the dielectric layer 400 can be rigidly constrained by the upper and lower metal layers to remain flat and will not warp or deform due to the difference in the coefficient of thermal expansion.

[0061] Then, windows are made in the dielectric layer 400 and the third copper layer 401 to form a through blind hole 501 on the end face of the exposed conductive copper pillar 301 and a blind groove 502 on the end face of the exposed sacrificial copper wall 302—step (e), as shown in Figure 3(g).

[0062] Alternatively, windows may be created in the dielectric layer 400 and the third copper layer 401 using laser drilling, laser drilling, or mechanical drilling processes.

[0063] By exposing the end face of the sacrificial copper wall 302 through a window, the sacrificial copper wall 302 can be etched without the need for grinding and thinning processes. This effectively shortens the processing flow, reduces dielectric material loss, and thus lowers the manufacturing cost of the frame substrate. Furthermore, compared to grinding, the thickness, thickness uniformity, and surface smoothness of the frame substrate are effectively controlled, improving the quality of subsequent embedded devices.

[0064] Next, a circuit layer 600 connecting the conductive copper pillar 301 is formed on the dielectric layer 400—step (f), as shown in Figure 3(h).

[0065] In some embodiments, step (f) includes:

[0066] (f1) Chemical copper plating is performed on the blind via 501;

[0067] (f2) A second photoresist pattern layer is formed by laminating a film on the third copper layer 400, exposing it, and developing it.

[0068] (f3) Electroplating fills the hollowed-out area of ​​the second photoresist pattern layer to form a circuit layer 600;

[0069] (f4) Remove the second photoresist pattern layer;

[0070] (f5) Etch the third copper layer.

[0071] Here, the third copper layer 401 serves as a seed layer, and the step of forming the seed layer can be omitted, which helps to save on the process flow.

[0072] By exposing the end face of the conductive copper pillar 301 through a window, the circuit layer 600 can be easily connected to the conductive copper pillar 301. This eliminates the need for the step of connecting the circuit layer and the conductive copper pillar 301 after embedding the device, thus achieving a technical effect of saving process time. In other words, the technical solution of this disclosure replaces the three steps of thinning, applying the dielectric layer, and windowing in related technologies with a one-step window opening, significantly saving process time and cost.

[0073] Then, remove the support plate 100—step (g), as shown in Figures 3(i) and 3(j).

[0074] In some embodiments, step (g) includes:

[0075] Separate the first copper layer 102 and the second copper layer 103;

[0076] Dry film is used to mask the circuit layer 600, and the second copper layer 103 is etched.

[0077] Finally, the sacrificial copper wall 302 is etched to form a frame substrate 700 with a cavity 701; wherein the cavity 701 penetrates the dielectric layer 400—step (h), as shown in Figure 3(k).

[0078] It should be noted that before etching the sacrificial copper wall 302, the area outside the sacrificial copper wall 302 is protected by dry film masking.

[0079] It should be understood that the number of cavities 701 can be one or more. Depending on the number of cavities 701, a corresponding number of sacrificial copper walls can be set, and this disclosure does not limit this.

[0080] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0081] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a frame substrate, characterized in that, include: (a) A support plate is provided, wherein the support plate has a metal layer; (b) A first photoresist pattern layer comprising a conductive copper pillar window and a sacrificial copper wall window is formed on the metal layer of the carrier plate; (c) A conductive copper pillar is formed in the conductive copper pillar opening, a sacrificial copper wall is formed in the sacrificial copper wall opening, and the first photoresist pattern layer is removed; (d) A dielectric layer and a third copper layer are laminated; wherein the thickness of the dielectric layer is greater than the height of the conductive copper pillar; the third copper layer is located on the side of the dielectric layer away from the carrier plate; (e) Create a blind hole to expose the end face of the conductive copper pillar and a blind groove to expose the end face of the sacrificial copper wall by opening windows in the dielectric layer and the third copper layer; (f) A circuit layer connecting the conductive copper pillars is formed on the dielectric layer; (g) Remove the support plate; (h) The sacrificial copper wall is etched via the blind trench to form a frame substrate with a cavity; wherein the cavity penetrates the dielectric layer.

2. The manufacturing method according to claim 1, characterized in that, The difference between the thickness of the dielectric layer and the height of the conductive copper pillar is 10~100 μm.

3. The manufacturing method according to claim 1, characterized in that, The material of the dielectric layer includes at least one of free liquid crystal polymer, BT resin, semi-cured prepreg, ABF film, epoxy resin and polyimide resin.

4. The manufacturing method according to claim 1, characterized in that, Step (b) includes: The first pattern layer is obtained by applying a film to the carrier plate, exposing it, and developing it.

5. The manufacturing method according to claim 1, characterized in that, Step (c) involves forming the conductive copper pillars and the sacrificial copper wall by electroplating.

6. The manufacturing method according to claim 1, characterized in that, Step (f) includes: (f1) Chemical copper plating is performed on the via; (f2) A second photoresist pattern layer is formed by laminating a film onto the third copper layer, exposing it, and developing it. (f3) Electroplating fills the hollowed-out areas of the second photoresist pattern layer to form the circuit layer; (f4) Remove the second photoresist pattern layer; (f5) Etch the third copper layer.

7. The manufacturing method according to claim 1, characterized in that, Step (e) involves creating windows in the dielectric layer using a laser drilling process.

8. The manufacturing method according to claim 1, characterized in that, The metal layer of the support plate includes a first copper layer and a second copper layer disposed sequentially on the support layer; the first copper layer and the second copper layer are physically bonded to each other; Step (g) includes: Separate the first copper layer and the second copper layer; The dry film is used to mask the circuit layer, and the second copper layer is etched.

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