Chip multi-layer heterogeneous integration method, device, equipment and storage medium

Abstract

The present invention provides a method, device, equipment and storage medium for multi-layer heterogeneous integration of chips. Among them, the method includes: performing deep learning analysis on the design parameters of the memory-computation integrated chip to generate a chip layout plan, and using a graph neural network to dynamically adjust the computing task allocation and data storage functions to obtain an optimized chip design plan; performing deep learning modeling on the micro-bumps based on the design plan, designing and forming a micro-bump array through an electroplating process; generating a through-silicon via distribution plan for the silicon wafer based on the chip design plan, and forming a through-silicon via structure on the silicon wafer; performing flip-chip processing on the chip and performing multi-layer stacking with the silicon wafer having through-silicon vias to form a multi-layer heterogeneous integration structure. This method realizes the dynamic optimization of the chip computing task and storage location by combining the micro-bump array and through-silicon vias after adjusting the computing task allocation and data storage functions, and improves the performance and integration efficiency of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip integration, and particularly to a method, device, equipment and storage medium for multi-layer heterogeneous integration of chips. Background Art

[0002] With the continuous progress of semiconductor technology, the memory-compute integrated chip, as a new type of computing architecture, has become one of the important technical paths to solve the bottleneck of the traditional von Neumann architecture. The memory-compute integrated chip integrates storage units and computing units, effectively improving the computing speed and reducing the energy consumption by reducing the frequency of data transmission between the memory and the processor. Such chips have broad application prospects in the fields of artificial intelligence, deep learning, edge computing, etc.

[0003] Existing memory-compute integrated chips mainly rely on traditional planar integration technology. Although this technology has good process maturity in the initial stage, with the increase of computing requirements, the limitations of two-dimensional planar integration gradually emerge. To further improve chip performance, heterogeneous integration technology has been proposed, which realizes more compact and efficient system integration by stacking chip layers with different functions. However, existing heterogeneous integration technologies still have certain bottlenecks in the layout, task allocation, and storage management of multi-layer chips.

[0004] Current heterogeneous integration technologies lack a dynamic optimization mechanism for chip computing tasks and data storage, resulting in uneven resource allocation and reduced computing efficiency in practical applications. Summary of the Invention

[0005] The main purpose of the present invention is to solve the technical problem that existing heterogeneous integration technologies lack a dynamic optimization mechanism for chip computing tasks and data storage, resulting in uneven resource allocation and reduced computing efficiency in practical applications.

[0006] The first aspect of the present invention provides a method for multi-layer heterogeneous integration of chips, and the method for multi-layer heterogeneous integration of chips includes:

[0007] Performing deep learning analysis on the design parameters of a memory-compute integrated chip to obtain a chip layout scheme, and dynamically adjusting the computing task allocation function and data storage location function of the memory-compute integrated chip by using a graph neural network according to the chip layout scheme to obtain a design scheme of the memory-compute integrated chip;

[0008] According to the design scheme of the memory-compute integrated chip, performing deep learning modeling on the microbumps on the memory-compute integrated chip to obtain a microbump design scheme, and electroplating the pads of the memory-compute integrated chip according to the microbump design scheme to obtain a microbump array;

[0009] Based on the in-memory computing integrated chip design scheme, a through-silicon via distribution scheme for the silicon wafer corresponding to the in-memory computing integrated chip is generated, and a through-silicon via structure is formed on the silicon wafer according to the through-silicon via distribution scheme;

[0010] Using a machine vision system and a time series prediction model, the in-memory computing integrated chip with a microbump array is flip-chip processed and multi-layer stacked with the silicon wafer having through-silicon vias to obtain a multi-layer heterogeneous integration structure.

[0011] Optionally, in the first implementation manner of the first aspect of the present invention, the deep learning analysis of the design parameters of the in-memory computing integrated chip to obtain a chip layout scheme, and according to the chip layout scheme, using a graph neural network to dynamically adjust the computing task allocation function and data storage location function of the in-memory computing integrated chip, the in-memory computing integrated chip design scheme includes:

[0012] Perform multi-objective optimization analysis and thermal distribution prediction modeling on the functional unit distribution, data flow pattern, and power consumption constraint of the in-memory computing integrated chip to obtain a thermally optimized layout scheme;

[0013] According to the thermally optimized layout scheme, use a recurrent neural network to dynamically predict the performance of the in-memory computing integrated chip under different workloads to obtain a performance prediction model;

[0014] Based on the performance prediction model, use a graph neural network to perform deep learning analysis on the functional units and data flow of the in-memory computing integrated chip to obtain a task allocation strategy;

[0015] Based on the task allocation strategy, use a reinforcement learning algorithm to model and optimize the storage hierarchy of the in-memory computing integrated chip to obtain a storage optimization scheme;

[0016] Integrate the task allocation strategy and the storage optimization scheme, and use a multi-agent collaborative learning algorithm to perform collaborative optimization on the overall chip architecture to obtain an in-memory computing integrated chip design scheme.

[0017] Optionally, in the second implementation manner of the first aspect of the present invention, the deep learning modeling of the microbumps on the in-memory computing integrated chip is performed according to the in-memory computing integrated chip design scheme to obtain a microbump design scheme, and the pads of the in-memory computing integrated chip are electroplated according to the microbump design scheme to obtain a microbump array, including:

[0018] Perform multi-dimensional analysis on the pad distribution, signal type, and current demand in the in-memory computing integrated chip design scheme to obtain a microbump distribution scheme; according to the microbump distribution scheme, perform parametric modeling on the geometric shape and size of the microbumps to obtain a microbump morphology model;

[0019] Based on the microbump topography model, perform finite element analysis on the stress distribution and thermal expansion characteristics of the microbumps to obtain microbump mechanical property data, and based on the microbump mechanical property data, predict the reliability of the microbumps under different working conditions to obtain a reliability evaluation model;

[0020] According to the reliability evaluation model, use a deep reinforcement learning network to optimize the microbump design to obtain an optimized microbump design scheme, and according to the microbump design scheme, use a generative adversarial network to generate multiple sets of microbump electroplating process parameters to obtain an electroplating process parameter set;

[0021] According to the electroplating process parameter set, perform selective area electroplating treatment on the pads of the in-memory computing integrated chip to obtain a microbump array.

[0022] Optionally, in the third implementation manner of the first aspect of the present invention, generating a through-silicon via distribution scheme of the silicon wafer corresponding to the in-memory computing integrated chip based on the in-memory computing integrated chip design scheme, and forming a through-silicon via structure on the silicon wafer according to the through-silicon via distribution scheme includes:

[0023] Perform deep learning analysis on the functional unit layout and signal transmission requirements in the in-memory computing integrated chip design scheme to obtain an initial through-silicon via distribution scheme, and use a graph neural network to model the interconnection relationship between the through-silicon vias in the initial through-silicon via distribution scheme to obtain a through-silicon via network model;

[0024] Based on the through-silicon via network model, perform electromagnetic simulation on the electrical performance and crosstalk characteristics of the through-silicon vias to obtain through-silicon via electrical characteristic data, and use a long short-term memory network to predict the performance of the through-silicon vias under high-frequency signal transmission to obtain a performance prediction result;

[0025] Globally optimize the initial through-silicon via distribution scheme according to the performance prediction result to obtain a through-silicon via distribution scheme, and perform photolithography and development processing on the silicon wafer according to the through-silicon via distribution scheme to obtain a through-silicon via etching pattern;

[0026] Use a deep reinforcement learning algorithm to dynamically optimize the plasma etching parameters to obtain an adaptive etching control strategy, perform plasma etching treatment on the silicon wafer, and use the adaptive etching control strategy to perform real-time parameter adjustment during the etching process to obtain a through-silicon via structure.

[0027] Optionally, in the fourth implementation manner of the first aspect of the present invention, using a machine vision system and a time series prediction model to perform flip-chip processing on the in-memory computing integrated chip with a microbump array and perform multi-layer stacking with the silicon wafer having through-silicon vias to obtain a multi-layer heterogeneous integration structure includes:

[0028] Use a machine vision system to collect images and identify features on the surface of the in-memory computing integrated chip and silicon wafer, obtain position information, and use a time series prediction model to predict the deformation during the flip-chip process based on the position information to obtain dynamic compensation parameters;

[0029] Based on the dynamic compensation parameters, flip and pre-align the in-memory computing integrated chip to obtain a preliminary flip-chip structure, and use a deep reinforcement learning algorithm for fine adjustment to obtain a flip-chip - silicon wafer structure with high-precision alignment;

[0030] Optimize the welding parameters of the flip-chip - silicon wafer structure to obtain the optimal flip-chip welding process parameters, and perform thermocompression welding treatment according to the optimal parameters to obtain a single-layer flip-chip integrated structure;

[0031] Use the machine vision system to detect the single-layer flip-chip integrated structure, analyze the welding interface characteristics of the single-layer flip-chip integrated structure to obtain a quality evaluation result, and based on the quality evaluation result, optimize the subsequent stacking parameters to obtain multi-layer stacking process parameters;

[0032] According to the multi-layer stacking process parameters, stack multiple single-layer flip-chip integrated structures layer by layer, and use an acoustic sensor to monitor and dynamically adjust the stacking parameters during the layer-by-layer stacking process to obtain a multi-layer heterogeneous integrated structure.

[0033] Optionally, in the fifth implementation manner of the first aspect of the present invention, the use of a machine vision system to collect images and identify features on the surface of the in-memory computing integrated chip and silicon wafer, obtain position information, and use a time series prediction model to predict the deformation during the flip-chip process based on the position information to obtain dynamic compensation parameters includes:

[0034] Use a machine vision system to collect multi-spectral images of the surface of the in-memory computing integrated chip and silicon wafer to obtain multi-dimensional image data, and extract and analyze the microstructure features of the multi-dimensional image data to obtain high-precision three-dimensional surface profile information;

[0035] Based on the high-precision three-dimensional surface profile information, identify and locate the key alignment marks on the surface of the in-memory computing integrated chip and silicon wafer to obtain position information, and use a time series prediction model to perform time series analysis on the position information to obtain position change trend data;

[0036] According to the position information, combine a thermodynamic model and finite element analysis to simulate and calculate the deformation caused by thermal expansion and mechanical stress during the flip-chip process, obtain a deformation prediction result, and generate corresponding compensation parameter sensitivity data according to the deformation prediction result;

[0037] According to the compensation parameter sensitivity data, use a multi-objective optimization algorithm to generate corresponding dynamic compensation parameters.

[0038] Optionally, in the sixth implementation manner of the first aspect of the present invention, detecting the single-layer flip-chip integrated structure by using the machine vision system, analyzing the welding interface characteristics of the single-layer flip-chip integrated structure, obtaining a quality evaluation result, and based on the quality evaluation result, optimizing subsequent stacking parameters to obtain multi-layer stacking process parameters, including:

[0039] Performing multi-angle and multi-spectral imaging on the single-layer flip-chip integrated structure to obtain a multi-modal data set, and processing the multi-modal data set by using a multi-modal image fusion algorithm to extract comprehensive characteristics of the welding interface and obtain an enhanced welding interface image;

[0040] Based on the welding interface image, using a deep learning image segmentation algorithm to accurately locate and extract the contour of the welding interface, obtaining a three-dimensional reconstruction model of the welding interface, and extracting microscopic morphology, void distribution, and metal interconnection structure characteristics from the three-dimensional reconstruction model to obtain quantitative interface characteristic parameters;

[0041] Performing quality evaluation of the welding interface according to the quantitative interface characteristic parameters to obtain a quality evaluation result, and using a genetic algorithm to optimize and search the stacking process parameters according to the quality evaluation result to obtain a stacking parameter set;

[0042] Generating statistical characteristics and reliability evaluation results of the stacking process based on the stacking parameter set, and based on an adaptive control strategy of a preset fuzzy PID, performing real-time monitoring and dynamic analysis on the statistical characteristics and reliability evaluation results during the stacking process to obtain multi-layer stacking process parameters.

[0043] The second aspect of the present invention provides a chip multi-layer heterogeneous integration device, and the chip multi-layer heterogeneous integration device includes:

[0044] A scheme design module, configured to perform deep learning analysis on design parameters of a memory-computation integrated chip to obtain a chip layout scheme, and according to the chip layout scheme, dynamically adjust the computing task allocation function and data storage location function of the memory-computation integrated chip by using a graph neural network to obtain a memory-computation integrated chip design scheme;

[0045] A micro-bump preparation module, configured to perform deep learning modeling of micro-bumps on the memory-computation integrated chip according to the memory-computation integrated chip design scheme to obtain a micro-bump design scheme, and perform electroplating treatment on pads of the memory-computation integrated chip according to the micro-bump design scheme to obtain a micro-bump array;

[0046] A through-silicon via preparation module, configured to generate a through-silicon via distribution scheme of a silicon wafer corresponding to the memory-computation integrated chip based on the memory-computation integrated chip design scheme, and form a through-silicon via structure on the silicon wafer according to the through-silicon via distribution scheme;

[0047] A flip-chip integrated module is used to perform flip-chip processing on a memory-in-compute integrated chip with a microbump array by using a machine vision system and a time series prediction model, and perform multi-layer stacking with the silicon wafer having through-silicon vias to obtain a multi-layer heterogeneous integrated structure.

[0048] In a third aspect of the present invention, there is provided a chip multi-layer heterogeneous integration device, including: a memory and at least one processor, wherein instructions are stored in the memory, and the memory and the at least one processor are interconnected by a circuit; the at least one processor calls the instructions in the memory to cause the chip multi-layer heterogeneous integration device to execute the steps of the above-mentioned chip multi-layer heterogeneous integration method.

[0049] In a fourth aspect of the present invention, there is provided a computer-readable storage medium, in which instructions are stored, and when it runs on a computer, it causes the computer to execute the steps of the above-mentioned chip multi-layer heterogeneous integration method.

[0050] For the above-mentioned chip multi-layer heterogeneous integration method, device, equipment and storage medium, by performing in-depth learning analysis on the design parameters of the memory-in-compute integrated chip, a chip layout scheme is generated, and the graph neural network is used to dynamically adjust the calculation task allocation and data storage function to obtain an optimized chip design scheme; based on the design scheme, in-depth learning modeling of microbumps is performed, and a microbump array is designed and formed by an electroplating process; based on the chip design scheme, a through-silicon via distribution scheme of the silicon wafer is generated, and a through-silicon via structure is formed on the silicon wafer; the chip is flip-chip processed and multi-layer stacked with the silicon wafer having through-silicon vias to form a multi-layer heterogeneous integrated structure. This method realizes the dynamic optimization of the chip calculation task and storage location by combining the microbump array and through-silicon vias after adjusting the calculation task allocation and data storage function, and improves the performance and integration efficiency of the chip.

[0051] Other features and advantages of the present invention will be described in the following specification, and some of them will become obvious from the specification or be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, claims and drawings.

[0052] To make the above-mentioned objectives, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and detailed descriptions are made in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic diagram of the first embodiment of the chip multi-layer heterogeneous integration method in the embodiment of the present invention;

[0054] Figure 2Schematic diagram of an embodiment of the chip multi-layer heterogeneous integration device in the embodiment of the present invention;

[0055] Figure 3 Schematic diagram of an embodiment of the chip multi-layer heterogeneous integration device in the embodiment of the present invention. Detailed implementation manners

[0056] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but optionally further includes other unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0058] For the convenience of understanding this embodiment, first, a chip multi-layer heterogeneous integration method disclosed in the embodiments of the present invention will be introduced in detail. As Figure 1 shown, this method includes the following steps:

[0059] 101. Perform in-depth learning analysis on the design parameters of the memory-computation integrated chip to obtain a chip layout plan, and according to the chip layout plan, use a graph neural network to dynamically adjust the computing task allocation function and data storage location function of the memory-computation integrated chip to obtain a memory-computation integrated chip design plan;

[0060] In an embodiment of the present invention, the design parameters of the in-memory computing integrated chip are analyzed through deep learning to obtain a chip layout plan. According to the chip layout plan, the computing task allocation function and data storage location function of the in-memory computing integrated chip are dynamically adjusted using a graph neural network, and the in-memory computing integrated chip design plan obtained includes: performing multi-objective optimization analysis and thermal distribution prediction modeling on the functional unit distribution, data flow pattern, and power consumption constraint of the in-memory computing integrated chip to obtain a thermally optimized layout plan; according to the thermally optimized layout plan, dynamically predicting the performance of the in-memory computing integrated chip under different workloads using a recurrent neural network to obtain a performance prediction model; based on the performance prediction model, performing deep learning analysis on the functional units and data flow of the in-memory computing integrated chip using a graph neural network to obtain a task allocation strategy; based on the task allocation strategy, modeling and optimizing the storage hierarchy of the in-memory computing integrated chip using a reinforcement learning algorithm to obtain a storage optimization plan; integrating the task allocation strategy and the storage optimization plan, and using a multi-agent collaborative learning algorithm to perform collaborative optimization on the overall chip architecture to obtain an in-memory computing integrated chip design plan.

[0061] Specifically, in the process of multi-objective optimization analysis of the functional unit distribution, data flow pattern, and power consumption constraint of the in-memory computing chip, by establishing a complex mathematical model, these factors are taken as optimization objectives, and optimization methods such as genetic algorithms or particle swarm algorithms are used to search for the best functional unit layout scheme. At the same time, combined with the thermal distribution prediction modeling technology, the finite element analysis method is adopted to simulate the thermal distribution of the chip under different working conditions. This thermal distribution prediction model takes into account factors such as the chip's geometric structure, material properties, and power consumption distribution. By solving the heat conduction equation, the temperature distribution of each part of the chip is obtained. Combining the multi-objective optimization results with the thermal distribution prediction results, through an iterative optimization process, a thermal optimization layout scheme that achieves a balance in performance, power consumption, and thermal management is finally obtained. Based on the obtained thermal optimization layout scheme, the performance of the in-memory computing chip under different workloads is dynamically predicted using a recurrent neural network in the next step. This step first requires constructing a recurrent neural network model containing long short-term memory (LSTM) units. This model takes the thermal optimization layout scheme of the chip as input and also considers different workload scenarios. Through training with a large amount of historical data, the recurrent neural network learns the dynamic characteristics of the chip's performance changing with the workload. In the prediction stage, the model can predict the performance metrics of the chip at different time points, such as computing throughput and memory access latency, according to the given workload sequence. This dynamic prediction ability enables the subsequent optimization process to better adapt to the performance changes of the chip in actual applications. After having the performance prediction model, the functional units and data flow of the in-memory computing chip are further analyzed through deep learning using a graph neural network. In this step, the functional units of the chip are abstracted as nodes in the graph, while the data flow is represented as the edges between the nodes. The graph neural network model can capture the complex interaction relationships and data dependencies between the functional units by learning this graph structure. Specifically, advanced graph neural network architectures such as graph convolutional network (GCN) or graph attention network (GAT) are used to aggregate and update the node features and edge features. Through the stacking and training of multiple layers of graph neural networks, the model gradually learns a higher-level representation of the chip structure. Based on this learned representation, task allocation algorithms, such as graph partitioning or community detection methods, are applied to obtain the optimal computing task allocation strategy. On the basis of obtaining the task allocation strategy, a reinforcement learning algorithm is then used to model and optimize the memory hierarchy of the in-memory computing chip. This process first constructs a reinforcement learning environment, where the state space includes information such as the current memory hierarchy structure, data distribution, and access pattern, and the action space includes operations such as data migration and cache policy adjustment. Reinforcement learning algorithms such as deep Q-network (DQN) or policy gradient are used to optimize the structure and management strategy of the memory hierarchy by continuously interacting with the environment and learning.The reinforcement learning agent learns the optimal storage optimization scheme by maximizing the long-term reward (such as the reciprocal of the overall access latency), including the capacity allocation of each level of storage, the data placement strategy, and the prefetch mechanism, etc. Finally, in order to obtain the globally optimal integrated memory and computing chip design scheme, a multi-agent collaborative learning algorithm is used to collaboratively optimize the overall chip architecture. At this stage, the task allocation strategy and storage optimization scheme obtained previously are used as the initial strategies of different agents. Each agent is responsible for optimizing an aspect of the chip design, such as computing resource allocation, storage management, communication optimization, etc. By constructing a shared environment model, multiple agents can learn and optimize their respective strategies simultaneously. Algorithms such as the Multi-Agent Deep Deterministic Policy Gradient (MADDPG) are used to enable each agent to consider the behaviors of other agents and the performance of the overall system while optimizing its own objectives. Through iterative training and policy updates, multiple agents gradually reach a balanced and coordinated solution. Finally, the optimization results of all agents are integrated to form a comprehensive integrated memory and computing chip design scheme.

[0062] 102. According to the integrated memory and computing chip design scheme, perform deep learning modeling on the microbumps on the integrated memory and computing chip to obtain a microbump design scheme, and perform electroplating treatment on the pads of the integrated memory and computing chip according to the microbump design scheme to obtain a microbump array;

[0063] In an embodiment of the present invention, the performing deep learning modeling on the microbumps on the integrated memory and computing chip according to the integrated memory and computing chip design scheme to obtain a microbump design scheme, and performing electroplating treatment on the pads of the integrated memory and computing chip according to the microbump design scheme to obtain a microbump array includes: performing multi-dimensional analysis on the pad distribution, signal type, and current demand in the integrated memory and computing chip design scheme to obtain a microbump distribution scheme; performing parametric modeling on the geometric shape and size of the microbumps according to the microbump distribution scheme to obtain a microbump morphology model; based on the microbump morphology model, performing finite element analysis on the stress distribution and thermal expansion characteristics of the microbumps to obtain microbump mechanical property data, and predicting the reliability of the microbumps under different working conditions according to the microbump mechanical property data to obtain a reliability evaluation model; optimizing the microbump design by using a deep reinforcement learning network according to the reliability evaluation model to obtain an optimized microbump design scheme, and using a generative adversarial network to generate multiple groups of microbump electroplating process parameters according to the microbump design scheme to obtain an electroplating process parameter set; performing selective area electroplating treatment on the pads of the integrated memory and computing chip according to the electroplating process parameter set to obtain a microbump array.

[0064] Specifically, for the deep learning modeling of microbumps according to the in-memory computing chip design scheme, it is first necessary to conduct multi-dimensional analysis on the pad distribution, signal type, and current requirements in the chip design scheme. By establishing a multi-dimensional data analysis model, factors such as the spatial position of pads, signal transmission characteristics, and current load are comprehensively considered. Using clustering algorithms such as K-means or hierarchical clustering methods, pads with similar characteristics are grouped. At the same time, dimensionality reduction techniques such as principal component analysis (PCA) or t-SNE are applied to extract key features to better understand the overall pattern of pad distribution. Based on these analysis results, combined with the functional layout and signal transmission requirements of the chip, a preliminary microbump distribution scheme is generated. Next, according to the obtained microbump distribution scheme, parametric modeling of the geometric shape and size of microbumps is carried out. This step uses computer-aided design (CAD) technology to abstract the shape of microbumps into a series of geometric parameters, such as height, diameter, top curvature, etc. By establishing a parametric model, the geometric features of microbumps can be flexibly adjusted. To more accurately describe the morphology of microbumps, advanced surface modeling techniques such as non-uniform rational B-splines (NURBS) are used to precisely capture the contour and surface features of microbumps. This parametric microbump morphology model lays the foundation for subsequent analysis and optimization. Based on the established microbump morphology model, the next step is to perform finite element analysis on the stress distribution and thermal expansion characteristics of microbumps. This process first requires the construction of a three-dimensional finite element model of microbumps, including the mesh generation of the geometric model, the definition of material properties, and the setting of boundary conditions. By solving the thermo-mechanical coupling equations, the stress distribution and deformation of microbumps under different temperature and load conditions are simulated. Factors such as the viscoelastic behavior of solder, interface stress concentration effects, and fatigue damage during thermal cycling are considered in the analysis. Through a large number of finite element simulations, mechanical property data of microbumps under various working conditions are obtained, including key indicators such as stress-strain curves, thermal expansion coefficients, and fatigue life. Based on the obtained mechanical property data of microbumps, a microbump reliability evaluation model is further constructed. This step uses machine learning techniques, such as algorithms like support vector machine (SVM) or random forest, to establish the mapping relationship between microbump reliability and its geometric parameters, material properties, and working conditions. By inputting a large amount of historical data and simulation results for training, the model learns the key factors affecting microbump reliability and their complex interactions. In the prediction stage, this model can quickly evaluate the reliability performance of microbumps under different application scenarios based on the given microbump design parameters and working conditions. Based on the established reliability evaluation model, the microbump design is then optimized using a deep reinforcement learning network. This process constructs a reinforcement learning environment where the state space includes the geometric parameters, material properties of microbumps, and the current reliability evaluation results, and the action space includes the adjustment operations on these parameters.Adopt algorithms such as Deep Q-Network (DQN) or Advantage Actor-Critic (A2C), and gradually learn the optimal design strategy by continuously trying different design schemes and evaluating their performance. The reinforcement learning agent optimizes the design of microbumps by maximizing the long-term reward (such as the weighted sum of reliability metrics), while balancing factors such as manufacturing difficulty and cost. After a large number of iterations and learning, an optimized microbump design scheme is finally obtained. In order to convert the optimized microbump design scheme into actual manufacturing parameters, a Generative Adversarial Network (GAN) is used to generate multiple sets of microbump electroplating process parameters. In this step, the generator network of the GAN takes the design parameters of the microbumps as input and generates corresponding electroplating process parameters, such as current density, electroplating time, additive ratio, etc. The discriminator network then evaluates whether the generated process parameters meet the actual manufacturing requirements and empirical rules. Through the adversarial training of the generator and the discriminator, the system can generate an electroplating process parameter set that not only meets the design requirements but also has feasibility. Finally, according to the generated electroplating process parameter set, selective area electroplating treatment is performed on the pads of the in-memory computing chip. This process first requires the preparation of an accurate photolithography mask to ensure electroplating only in the specified pad area. Advanced electroplating equipment, such as pulse reverse electroplating or jet electroplating technology, is used to precisely control the current density and electroplating time. During the electroplating process, the thickness and uniformity of the electroplated layer are monitored in real time, and parameter fine-tuning is performed if necessary. Through a multi-step electroplating process, a microbump structure that meets the design requirements is formed layer by layer. Finally, surface treatment and quality inspection are performed on the formed microbump array to ensure that its geometric dimensions, surface morphology, and mechanical properties meet the design specifications.

[0065] 103. Based on the in-memory computing chip design scheme, generate the through-silicon via distribution scheme of the silicon wafer corresponding to the in-memory computing chip, and form a through-silicon via structure on the silicon wafer according to the through-silicon via distribution scheme;

[0066] In one embodiment of the present invention, generating a through-silicon via (TSV) distribution scheme for a silicon wafer corresponding to the in-memory computing integrated chip based on the in-memory computing integrated chip design scheme, and forming a TSV structure on the silicon wafer according to the TSV distribution scheme includes: performing deep learning analysis on the functional unit layout and signal transmission requirements in the in-memory computing integrated chip design scheme to obtain an initial TSV distribution scheme, and using a graph neural network to model the interconnection relationship between TSVs in the initial TSV distribution scheme to obtain a TSV network model; based on the TSV network model, performing electromagnetic simulation on the electrical performance and crosstalk characteristics of TSVs to obtain TSV electrical characteristic data, and using a long short-term memory network to predict the performance of TSVs under high-frequency signal transmission to obtain a performance prediction result; globally optimizing the initial TSV distribution scheme according to the performance prediction result to obtain a TSV distribution scheme, and performing photolithography and development processes on the silicon wafer according to the TSV distribution scheme to obtain a TSV etching pattern; using a deep reinforcement learning algorithm to dynamically optimize the plasma etching parameters to obtain an adaptive etching control strategy, and performing plasma etching on the silicon wafer, and adjusting the real-time parameters using the adaptive etching control strategy during the etching process to obtain a TSV structure.

[0067] Specifically, first, a deep learning analysis is performed on the functional unit layout and signal transmission requirements in the in-memory computing chip design scheme. In this step, a convolutional neural network (CNN) is used to extract features from the chip layout diagram to identify key functional units and signal paths. At the same time, natural language processing techniques are used to analyze the design specification documents to extract signal transmission requirements and performance metrics. By integrating this information into a multi-modal deep learning model, the system can understand the functional distribution and interconnection requirements of the chip, thereby generating an initial through-silicon via (TSV) distribution scheme. Next, a graph neural network (GNN) is used to model the interconnection relationships between the TSVs in the initial TSV distribution scheme. In this process, each TSV is regarded as a node in the graph, and the signal transmission paths between the TSVs are represented as edges. By applying graph convolution or graph attention mechanisms, the GNN can capture the topological structure and local features of the TSV network. Through multiple layers of graph convolution operations, the model gradually learns the high-level representations of the nodes, which not only contain the features of individual TSVs but also encode information about their positions and connection relationships in the entire network. After training, the GNN model outputs a complete TSV network model that can accurately reflect the complex interconnection relationships between the TSVs. Based on the obtained TSV network model, the next step is to perform electromagnetic simulations on the electrical performance and crosstalk characteristics of the TSVs. This process uses advanced electromagnetic field solvers, such as the finite-difference time-domain method (FDTD) or the method of moments, to construct an accurate three-dimensional model of the TSVs and their surrounding structures. By setting appropriate boundary conditions and excitation sources, the propagation characteristics of high-frequency signals in the TSV network are simulated. The simulation process takes into account factors such as the dispersion characteristics of materials, the skin effect, and the electromagnetic coupling between adjacent TSVs, thereby obtaining comprehensive electrical characteristic data of the TSVs, including key parameters such as impedance, insertion loss, return loss, and crosstalk. To predict the performance of the TSVs under high-frequency signal transmission, a long short-term memory network (LSTM) is used for modeling. The LSTM network takes the electrical characteristic data obtained from the electromagnetic simulation as the input sequence and learns the temporal characteristics of signal transmission in the TSV network. Through training, the LSTM model can capture the long-term dependencies in the signal transmission process and predict the signal quality at different frequencies and transmission distances. This predictive ability enables the system to evaluate the performance of the TSV network under various operating conditions and provide a basis for subsequent optimization. According to the performance prediction results output by the LSTM network, a global optimization of the initial TSV distribution scheme is carried out. This step uses multi-objective optimization algorithms, such as the non-dominated sorting genetic algorithm (NSGA-II) or multi-objective particle swarm optimization (MOPSO), considering multiple objectives such as signal integrity, power consumption, and area utilization. During the optimization process, the algorithm adjusts the positions, sizes, and densities of the TSVs to find the Pareto optimal solution set under the premise of meeting the design rules. From these solutions, the best TSV distribution scheme is selected based on the decision-maker's preferences or adaptive selection strategies.With the optimized through-silicon via (TSV) distribution scheme, the next step is to perform lithography and development processes to obtain the TSV etching pattern. This process first requires designing and fabricating a high-precision lithography mask to accurately reflect the TSV distribution pattern. Then, a photoresist is coated on the surface of the silicon wafer, and exposure is carried out using advanced lithography equipment (such as extreme ultraviolet lithography machines). After exposure, the wafer undergoes a development process to form an etching pattern corresponding to the TSV distribution. To precisely control the TSV etching process, a deep reinforcement learning algorithm is used to dynamically optimize the plasma etching parameters. A reinforcement learning environment is constructed, where the state space includes information such as the current etching depth, sidewall angle, and surface roughness, and the action space includes adjustable parameters such as radio frequency power, gas flow rate, and chamber pressure. Through interaction with a simulation environment or an actual etching system, the reinforcement learning agent gradually learns the optimal etching strategy. This adaptive etching control strategy can dynamically adjust the etching parameters according to real-time monitoring data to cope with various changes and uncertainties during the etching process. Finally, using the obtained adaptive etching control strategy, the silicon wafer is subjected to plasma etching. During the etching process, a real-time monitoring system continuously collects key parameters such as etching depth and sidewall angle. These data are input into the deep reinforcement learning model, and the model outputs optimal etching parameter adjustment suggestions based on the current state. The control system adjusts the operating parameters of the plasma etching equipment, such as radio frequency power and gas component ratio, in real time according to these suggestions. Through this closed-loop control mechanism, the system can precisely control the etching process to ensure that the formed TSV structure meets the design requirements, including key indicators such as aspect ratio, sidewall perpendicularity, and surface quality.

[0068] 104. Use a machine vision system and a time series prediction model to perform flip-chip processing on a memory-integrated computing chip with a microbump array, and stack it with the silicon wafer having through-silicon vias in multiple layers to obtain a multi-layer heterogeneous integration structure.

[0069] In one embodiment of the present invention, the use of a machine vision system and a time series prediction model to perform flip-chip processing on a memory-computation integrated chip with a micro bump array and perform multi-layer stacking with the silicon wafer having through-silicon vias to obtain a multi-layer heterogeneous integration structure includes: using the machine vision system to collect images and identify features on the surfaces of the memory-computation integrated chip and the silicon wafer to obtain position information, and using the time series prediction model to predict the deformation during the flip-chip process based on the position information to obtain dynamic compensation parameters; based on the dynamic compensation parameters, flipping and pre-aligning the memory-computation integrated chip to obtain a preliminary flip-chip structure, and using a deep reinforcement learning algorithm for fine adjustment to obtain a flip-chip-silicon wafer structure with high-precision alignment; optimizing the welding parameters of the flip-chip-silicon wafer structure to obtain the optimal flip-chip welding process parameters, and performing thermocompression welding treatment according to the optimal parameters to obtain a single-layer flip-chip integrated structure; using the machine vision system to detect the single-layer flip-chip integrated structure, analyzing the welding interface characteristics of the single-layer flip-chip integrated structure to obtain a quality evaluation result, and based on the quality evaluation result, optimizing the subsequent stacking parameters to obtain multi-layer stacking process parameters; according to the multi-layer stacking process parameters, stacking multiple single-layer flip-chip integrated structures layer by layer, and using an acoustic sensor to monitor and dynamically adjust the stacking parameters during the layer-by-layer stacking process to obtain a multi-layer heterogeneous integration structure.

[0070] Specifically, first, a machine vision system is used to collect images and identify features on the in-memory computing integrated chip and the surface of the silicon wafer to obtain position information. Subsequently, these position information are analyzed through a time series prediction model to predict the possible deformations during the flip-chip process, thereby obtaining dynamic compensation parameters. These parameters provide an important basis for subsequent precise alignment. Based on the obtained dynamic compensation parameters, the in-memory computing integrated chip is then flipped and pre-aligned. This process uses a high-precision robotic arm, in conjunction with a vision feedback system, to flip the chip to the correct direction. The pre-alignment stage adopts a rough positioning strategy to roughly align the chip to a predetermined position on the silicon wafer, forming a preliminary flip-chip structure. To achieve higher-precision alignment, a deep reinforcement learning algorithm is introduced for fine-tuning. This algorithm constructs a reinforcement learning environment, where the state space includes information such as the relative position and angular deviation between the chip and the silicon wafer, and the action space includes small translation and rotation operations. Through interaction with a high-precision displacement stage, the reinforcement learning agent gradually learns the optimal adjustment strategy. The algorithm uses methods such as Deep Q-Network (DQN) or Proximal Policy Optimization (PPO), and through a large number of iterative trainings, continuously optimizes the alignment actions. During the actual alignment process, the system continuously executes the learned optimal adjustment actions according to the real-time feedback position information until a preset precision threshold is reached, and finally obtains a high-precision aligned flip-chip-silicon wafer structure. After completing the precise alignment, the next step is to optimize the welding parameters for the flip-chip-silicon wafer structure. This process uses a multi-objective optimization algorithm, such as a genetic algorithm or a particle swarm optimization, considering multiple objectives such as welding strength, thermal stress distribution, and welding time. During the optimization process, the algorithm adjusts parameters such as the temperature curve, pressure distribution, and heating time, and under the premise of meeting the process constraints, searches for the optimal combination of welding process parameters. The optimization algorithm uses a thermodynamics model and finite element analysis to simulate the welding process under different parameters and evaluate the welding quality and reliability. Through multiple iterations and evaluations, the optimal flip-chip welding process parameters are finally determined. After obtaining the optimal welding process parameters, thermocompression bonding is performed. This step uses precision thermocompression bonding equipment to strictly control the temperature, pressure, and time. During the welding process, the system real-time monitors key parameters, such as temperature distribution and pressure uniformity, to ensure that the welding process is strictly carried out according to the optimized process parameters. At the same time, in-situ measurement techniques, such as acoustic emission or resistance measurement, are used to real-time monitor the formation process of the welding interface. This real-time monitoring and feedback mechanism can timely detect and correct abnormalities during the welding process, ensuring the consistency and reliability of the welding quality. After completing the thermocompression bonding, a single-layer flip-chip integrated structure is obtained. Subsequently, a machine vision system is used to detect the single-layer flip-chip integrated structure, analyze the welding interface characteristics, and obtain a quality evaluation result. Based on these results, the system optimizes the subsequent stacking parameters to generate multi-layer stacking process parameters. These parameters provide guidance for the subsequent multi-layer stacking process. Finally, according to the generated multi-layer stacking process parameters, multiple single-layer flip-chip integrated structures are stacked layer by layer.The stacking process uses precise alignment and pressing equipment to ensure the precise positioning and effective connection of each layer. During the layer-by-layer stacking process, the system integrates acoustic sensors for real-time monitoring. These sensors can capture tiny acoustic signals during the stacking process, which may indicate interface bonding, material deformation, or the formation of potential defects. The acoustic signals are collected in real-time through a high-speed data acquisition system and input into a pre-trained machine learning model for analysis. This model, which can be a deep learning model based on convolutional neural network (CNN) or recurrent neural network (RNN), can extract key features from complex acoustic signals and identify abnormal patterns during the stacking process. Based on the real-time feedback from acoustic monitoring, the system can dynamically adjust the stacking parameters. For example, if insufficient bonding of a certain layer is detected, the system may appropriately increase the pressure or extend the pressing time; if potential stress concentration is found, the temperature distribution or pressure uniformity may be adjusted. This dynamic adjustment strategy adopts a closed-loop control method, combining fuzzy logic or adaptive control algorithms, and continuously optimizes the stacking parameters according to real-time monitoring data and preset quality standards. In this way, the system can actively respond to various changes and challenges during the stacking process to ensure the stacking quality of each layer. As the layer-by-layer stacking progresses, the system continuously accumulates and analyzes process data, and uses machine learning algorithms to continuously optimize the stacking strategy. This adaptive learning mechanism enables the stacking process to continuously improve as the number of layers increases and adapt to special requirements that may occur at different levels. Finally, through this intelligent and adaptive layer-by-layer stacking process, the system successfully constructs a high-quality multi-layer heterogeneous integration structure.

[0071] Further, the method of using a machine vision system to collect images and identify features on the surface of the in-memory computing chip and the silicon wafer to obtain position information, and using a time series prediction model to predict the deformation during the flip-chip process based on the position information to obtain dynamic compensation parameters includes: using a machine vision system to collect multi-spectral images of the surface of the in-memory computing chip and the silicon wafer to obtain multi-dimensional image data, and extracting and analyzing the microstructure features of the multi-dimensional image data to obtain high-precision three-dimensional surface profile information; based on the high-precision three-dimensional surface profile information, identifying and positioning the key alignment marks on the surface of the in-memory computing chip and the silicon wafer to obtain position information, and performing time series analysis on the position information using a time series prediction model to obtain position change trend data; according to the position information, combining a thermodynamics model and finite element analysis, simulating and calculating the deformation caused by thermal expansion and mechanical stress during the flip-chip process to obtain a deformation prediction result and generating corresponding compensation parameter sensitivity data according to the deformation prediction result; according to the compensation parameter sensitivity data, using a multi-objective optimization algorithm to generate corresponding dynamic compensation parameters.

[0072] Specifically, first, a machine vision system is used to collect multi-spectral images of the chip and the surface of the silicon wafer. This step employs a high-resolution multi-spectral camera to simultaneously capture image information in the visible light, near-infrared, and ultraviolet bands. Multi-spectral imaging technology can reveal the subtle features and potential defects on the material surface, which may be difficult to identify in a single band. The collected multi-dimensional image data then enters the processing stage, where advanced image processing algorithms, such as wavelet transform or principal component analysis, are used to denoise and enhance the images. Next, microstructural feature extraction and analysis are performed on the enhanced multi-dimensional image data. This process uses deep learning models, such as convolutional neural networks (CNNs) or U-Net architectures, to perform semantic segmentation and feature recognition on the images. The models are trained with a large amount of labeled data and can accurately identify the tiny structures on the chip and the surface of the silicon wafer, such as protrusions, depressions, edge contours, etc. By fusing the information from multiple spectral channels, the system generates high-precision three-dimensional surface profile information. This three-dimensional reconstruction technology combines traditional stereo vision algorithms and deep learning methods and can accurately capture the micron-level height variations on the surface. Based on the obtained high-precision three-dimensional surface profile information, the system further identifies and locates the key alignment marks on the surface of the in-memory computing chip and the silicon wafer. These alignment marks are specially designed geometric patterns or feature points. The identification process uses template matching algorithms combined with deep learning object detection networks, such as FasterR-CNN or YOLO, to locate these marks with high precision. Through the comprehensive analysis of multiple mark points, the system calculates the precise position and attitude information of the chip and the silicon wafer. After obtaining the position information, the system uses a time series prediction model to analyze this data. Recurrent neural network structures, such as long short-term memory networks (LSTMs) or gated recurrent units (GRUs), are used to model the time series of the position data. These models can capture the long-term dependencies and short-term fluctuations of the position changes, thus predicting the future position change trends. The training data of the models includes a large amount of position time series data collected during the historical alignment process, enabling them to adapt to different alignment scenarios and environmental conditions. The predicted position change trend data provides important input for subsequent deformation analysis. Combining these data, the system further uses thermodynamic models and finite element analysis methods to simulate and calculate the possible deformations during the flip-chip process. The thermodynamic model takes into account factors such as the thermal expansion coefficient of the material and the ambient temperature change, while the finite element analysis simulates the impact of mechanical stress on the chip and the silicon wafer. This complex simulation process requires high-performance computing resources and usually uses parallel computing technology to accelerate the analysis. The simulation results show the tiny deformations and displacements that the chip and the silicon wafer may undergo under different temperature and pressure conditions. Based on the deformation prediction results obtained from the simulation, the system generates corresponding compensation parameter sensitivity data. This step involves performing sensitivity analysis on multiple influencing factors, including temperature change, pressure distribution, material properties, etc.Using the orthogonal experimental design or Monte Carlo simulation method, systematically evaluate the influence degree of different parameters on the final alignment accuracy. This analysis helps to identify the most critical influencing factors and provides a basis for formulating subsequent compensation strategies. Finally, based on the compensation parameter sensitivity data, the system uses a multi-objective optimization algorithm to generate dynamic compensation parameters. This optimization process considers multiple objectives simultaneously, such as alignment accuracy, operation time, energy consumption, etc. Using advanced multi-objective optimization algorithms such as NSGA-II (Non-dominated Sorting Genetic Algorithm II) or MOEA / D (Multi-Objective Evolutionary Algorithm Based on Decomposition), the system searches for the optimal solution in the parameter space. During the optimization process, the algorithm needs to balance the trade-offs between different objectives and find a set of Pareto-optimal compensation parameters. These parameters include the position fine-tuning amount during the alignment process, pressure distribution adjustment, temperature control strategy, etc.

[0073] Furthermore, use the machine vision system to detect the single-layer flip-chip integrated structure, analyze the welding interface characteristics of the single-layer flip-chip integrated structure, obtain the quality assessment result, and based on the quality assessment result, optimize the subsequent stacking parameters to obtain the multi-layer stacking process parameters, including: performing multi-angle and multi-spectral imaging on the single-layer flip-chip integrated structure to obtain a multi-modal data set, and using a multi-modal image fusion algorithm to process the multi-modal data set to extract the comprehensive characteristics of the welding interface and obtain an enhanced welding interface image; based on the welding interface image, using a deep learning image segmentation algorithm to accurately locate and extract the contour of the welding interface to obtain a three-dimensional reconstruction model of the welding interface, and extracting microscopic morphology, void distribution, and metal interconnect structure characteristics from the three-dimensional reconstruction model to obtain quantitative interface characteristic parameters; performing quality assessment of the welding interface according to the quantitative interface characteristic parameters to obtain the quality assessment result, and using a genetic algorithm to optimize and search the stacking process parameters according to the quality assessment result to obtain a stacking parameter set; generating statistical characteristics and reliability assessment results of the stacking process based on the stacking parameter set, and based on the adaptive control strategy of the preset fuzzy PID, performing real-time monitoring and dynamic analysis on the statistical characteristics and reliability assessment results during the stacking process to obtain the multi-layer stacking process parameters.

[0074] Specifically, first, a machine vision system is used to perform multi-angle and multi-spectral imaging on the single-layer flip-chip integrated structure. This step employs a high-precision multi-spectral camera array to simultaneously capture images in multiple bands such as visible light, infrared, and X-rays from different angles. The multi-angle imaging technology can provide three-dimensional information of the welding interface, while multi-spectral imaging can reveal the characteristics and potential defects of different material layers. These image data together constitute a rich multi-modal dataset, providing a comprehensive information basis for subsequent analysis. Next, an advanced multi-modal image fusion algorithm is used to process the obtained multi-modal dataset. This process adopts a deep learning-based image fusion network, such as DenseFuse or FusionGAN, to intelligently fuse the image information of different spectra and angles. During the fusion process, the algorithm automatically learns and retains the key information in each modality while suppressing noise and redundant data. In this way, the system generates an enhanced welding interface image that combines the advantages of multi-modal data and highlights the key features of the welding interface. Based on the obtained enhanced welding interface image, the system then uses a deep learning image segmentation algorithm to accurately locate and extract the contour of the welding interface. This step adopts advanced semantic segmentation networks such as U-Net or Mask R-CNN to perform pixel-level classification and boundary recognition on the image. The network is trained with a large amount of labeled data and can accurately identify the fine structure of the welding interface, including interface boundaries and internal defects. By performing three-dimensional reconstruction on the segmentation results, the system generates a high-precision three-dimensional reconstruction model of the welding interface. From the generated three-dimensional reconstruction model, the system further extracts key features such as micro-topography, void distribution, and metal interconnect structure. This process involves complex image processing and feature extraction algorithms, such as morphological analysis, texture feature extraction, and connectivity analysis. Through these analyses, the system obtains a series of quantitative interface feature parameters, including interface roughness, void density, and continuity index of metal interconnects. These parameters provide an objective and quantitative basis for subsequent quality assessment. Based on the extracted quantitative interface feature parameters, the system conducts quality assessment of the welding interface. This step adopts a machine learning model, such as support vector machine (SVM) or random forest, to map the extracted feature parameters to predefined quality grades. The model is trained with a large amount of historical data to learn the complex relationship between different combinations of feature parameters and welding quality. The evaluation result not only gives the overall quality grade but also provides detailed information on specific defect types and locations. After obtaining the quality assessment result, the system uses a genetic algorithm to optimize the search for stacking process parameters. The genetic algorithm simulates the biological evolution process and continuously optimizes the parameter combination through operations such as crossover and mutation. The fitness function of the algorithm is designed to integrate multiple factors such as quality assessment results, production efficiency, and cost, aiming to find the optimal solution that balances various indicators.Through multi-generation iterative optimization, the system finally obtains an optimized set of stacking parameters, which includes key process parameters such as temperature curve, pressure distribution, and time control. Based on the optimized set of stacking parameters, the system further generates statistical characteristics and reliability evaluation results of the stacking process. This step involves large-scale Monte Carlo simulations that simulate the stacking process within different parameter variation ranges. By analyzing a large number of simulation results, the system obtains key statistical characteristics of the stacking process, such as the yield rate distribution and the probability of failure modes. At the same time, using methods of reliability engineering, such as Failure Mode and Effects Analysis (FMEA), the system evaluates the long-term reliability of the stacking process. Finally, based on a preset fuzzy PID adaptive control strategy, the system monitors and dynamically analyzes the statistical characteristics and reliability evaluation results during the stacking process. The fuzzy PID controller combines the precision of traditional PID control and the flexibility of fuzzy logic, and can dynamically adjust control parameters according to real-time monitoring data. The system continuously compares the differences between the parameters in the actual stacking process and the expected statistical characteristics, and automatically adjusts the process parameters according to the degree of difference. This adaptive control mechanism can effectively cope with various uncertainties and fluctuations during the stacking process, ensuring the consistency and reliability of the final product.

[0075] In this embodiment, through in-depth learning analysis of the design parameters of the memory-computation integrated chip, a chip layout scheme is generated, and the graph neural network is used to dynamically adjust the computing task allocation and data storage functions to obtain an optimized chip design scheme; based on the design scheme, in-depth learning modeling of micro-bumps is carried out, and a micro-bump array is designed and formed through an electroplating process; based on the chip design scheme, a through-silicon via distribution scheme of the silicon wafer is generated, and a through-silicon via structure is formed on the silicon wafer; the chip is flip-chip processed and multi-layer stacked with the silicon wafer having through-silicon vias to form a multi-layer heterogeneous integration structure. This method realizes the dynamic optimization of the chip computing tasks and storage locations by combining the micro-bump array and through-silicon vias after adjusting the computing task allocation and data storage functions, and improves the performance and integration efficiency of the chip.

[0076] The method for multi-layer heterogeneous integration of chips in the embodiments of the present invention has been described above. Next, the device for multi-layer heterogeneous integration of chips in the embodiments of the present invention will be described. Please refer to Figure 2 , an embodiment of the device for multi-layer heterogeneous integration of chips in the embodiments of the present invention includes:

[0077] A scheme design module 201, configured to perform in-depth learning analysis on the design parameters of the memory-computation integrated chip to obtain a chip layout scheme, and according to the chip layout scheme, use a graph neural network to dynamically adjust the computing task allocation function and data storage location function of the memory-computation integrated chip to obtain a memory-computation integrated chip design scheme;

[0078] The micro bump preparation module 202 is configured to perform deep learning modeling on the micro bumps on the memory - computing integrated chip according to the memory - computing integrated chip design scheme, obtain the micro bump design scheme, and perform electroplating treatment on the pads of the memory - computing integrated chip according to the micro bump design scheme to obtain a micro bump array;

[0079] The through - silicon via preparation module 203 is configured to generate a through - silicon via distribution scheme for the silicon wafer corresponding to the memory - computing integrated chip based on the memory - computing integrated chip design scheme, and form a through - silicon via structure on the silicon wafer according to the through - silicon via distribution scheme;

[0080] The flip - chip integration module 204 is configured to perform flip - chip processing on the memory - computing integrated chip with a micro bump array by using a machine vision system and a time - series prediction model, and perform multi - layer stacking with the silicon wafer having through - silicon vias to obtain a multi - layer heterogeneous integration structure.

[0081] In the embodiment of the present invention, the chip multi - layer heterogeneous integration device runs the above - mentioned chip multi - layer heterogeneous integration method. The chip multi - layer heterogeneous integration device generates a chip layout scheme by performing deep learning analysis on the design parameters of the memory - computing integrated chip, and uses a graph neural network to dynamically adjust the computing task allocation and data storage functions to obtain an optimized chip design scheme; performs deep learning modeling of micro bumps based on the design scheme, designs and forms a micro bump array through an electroplating process; generates a through - silicon via distribution scheme for the silicon wafer based on the chip design scheme, and forms a through - silicon via structure on the silicon wafer; performs flip - chip processing on the chip and performs multi - layer stacking with the silicon wafer having through - silicon vias to form a multi - layer heterogeneous integration structure. This method realizes the dynamic optimization of the chip computing task and storage location by combining the micro bump array and through - silicon vias after adjusting the computing task allocation and data storage functions, and improves the performance and integration efficiency of the chip.

[0082] Above Figure 2 The chip multi - layer heterogeneous integration device in the embodiment of the present invention is described in detail from the perspective of modular functional entities. Next, the chip multi - layer heterogeneous integration device in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0083] Figure 3It is a schematic structural diagram of a chip multi-layer heterogeneous integration device provided by an embodiment of the present invention. The chip multi-layer heterogeneous integration device 300 may vary greatly due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 (for example, one or more processors) and a memory 320, and one or more storage media 330 for storing application programs 333 or data 332 (for example, one or more mass storage device terminals). Among them, the memory 320 and the storage media 330 may be transient storage or persistent storage. The program stored in the storage media 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the chip multi-layer heterogeneous integration device 300. Further, the processor 310 may be configured to communicate with the storage media 330 and execute a series of instruction operations in the storage media 330 on the chip multi-layer heterogeneous integration device 300 to implement the steps of the above chip multi-layer heterogeneous integration method.

[0084] The chip multi-layer heterogeneous integration device 300 may further include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input / output interfaces 360, and / or one or more operating systems 331, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, and so on. Those skilled in the art can understand that Figure 3 The shown chip multi-layer heterogeneous integration device structure does not constitute a limitation on the chip multi-layer heterogeneous integration device provided by the present invention, and may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0085] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions run on a computer, the computer is caused to execute the steps of the chip multi-layer heterogeneous integration method.

[0086] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, or units can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0087] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0088] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of various embodiments of the present invention.

Claims

1. A method for multi-layer heterogeneous integration of chips, characterized in that The multi-layer heterogeneous integration method of the chip includes: Performing multi-objective optimization analysis and thermal distribution prediction modeling on the functional unit distribution, data flow pattern, and power consumption constraint of the memory-computation integrated chip to obtain a thermal optimization layout plan; according to the thermal optimization layout plan, using a recurrent neural network to dynamically predict the performance of the memory-computation integrated chip under different workloads to obtain a performance prediction model; based on the performance prediction model, using a graph neural network to perform in-depth learning analysis on the functional units and data flow of the memory-computation integrated chip to obtain a task allocation strategy; based on the task allocation strategy, using a reinforcement learning algorithm to model and optimize the storage hierarchy of the memory-computation integrated chip to obtain a storage optimization plan; integrating the task allocation strategy and the storage optimization plan, and using a multi-agent collaborative learning algorithm to perform collaborative optimization on the overall chip architecture to obtain a memory-computation integrated chip design plan; According to the memory-computation integrated chip design plan, performing in-depth learning modeling on the microbumps on the memory-computation integrated chip to obtain a microbump design plan, and performing electroplating treatment on the pads of the memory-computation integrated chip according to the microbump design plan to obtain a microbump array; Based on the memory-computation integrated chip design plan, generating a through-silicon via distribution plan for the silicon wafer corresponding to the memory-computation integrated chip, and forming a through-silicon via structure on the silicon wafer according to the through-silicon via distribution plan; Using a machine vision system and a time series prediction model to perform flip-chip processing on the memory-computation integrated chip with a microbump array, and performing multi-layer stacking with the silicon wafer having through-silicon vias to obtain a multi-layer heterogeneous integration structure.

2. The chip multi-layer heterogeneous integration method according to claim 1, wherein The performing in-depth learning modeling on the microbumps on the memory-computation integrated chip according to the memory-computation integrated chip design plan to obtain a microbump design plan, and performing electroplating treatment on the pads of the memory-computation integrated chip according to the microbump design plan to obtain a microbump array includes: Performing multi-dimensional analysis on the pad distribution, signal type, and current demand in the memory-computation integrated chip design plan to obtain a microbump distribution plan; according to the microbump distribution plan, performing parametric modeling on the geometric shape and size of the microbumps to obtain a microbump morphology model; Based on the microbump morphology model, performing finite element analysis on the stress distribution and thermal expansion characteristics of the microbumps to obtain microbump mechanical property data, and predicting the reliability of the microbumps under different working conditions according to the microbump mechanical property data to obtain a reliability evaluation model; Optimizing the microbump design using a deep reinforcement learning network according to the reliability evaluation model to obtain an optimized microbump design plan, and using a generative adversarial network to generate multiple sets of microbump electroplating process parameters according to the microbump design plan to obtain an electroplating process parameter set; Performing selective area electroplating treatment on the pads of the memory-computation integrated chip according to the electroplating process parameter set to obtain a microbump array.

3. The chip multi-layer heterogeneous integration method according to claim 1, characterized in that The generating a through-silicon via distribution plan for the silicon wafer corresponding to the memory-computation integrated chip based on the memory-computation integrated chip design plan, and forming a through-silicon via structure on the silicon wafer according to the through-silicon via distribution plan includes: Deep learning analysis is performed on the functional unit layout and signal transmission requirements in the in-memory computing integrated circuit design scheme to obtain an initial through-silicon via (TSV) distribution scheme, and a graph neural network is used to model the interconnect relationships between the TSVs in the initial TSV distribution scheme to obtain a TSV network model; Based on the TSV network model, electromagnetic simulation is performed on the electrical performance and crosstalk characteristics of the TSVs to obtain TSV electrical characteristic data, and a long short-term memory network is used to predict the performance of the TSVs under high-frequency signal transmission to obtain a performance prediction result; According to the performance prediction result, the initial TSV distribution scheme is globally optimized to obtain a TSV distribution scheme, and the silicon wafer is subjected to photolithography and development processes according to the TSV distribution scheme to obtain a TSV etching pattern; A deep reinforcement learning algorithm is used to dynamically optimize the plasma etching parameters to obtain an adaptive etching control strategy, and the silicon wafer is subjected to plasma etching, and the real-time parameters are adjusted using the adaptive etching control strategy during the etching process to obtain a TSV structure.

4. The chip multi-layer heterogeneous integration method according to claim 1, wherein, Using the machine vision system and the time series prediction model, the flip-chip processing of the in-memory computing integrated circuit with a micro-bump array is performed and multi-layer stacking is carried out with the silicon wafer having the TSVs, and the multi-layer heterogeneous integration structure obtained includes: The machine vision system is used to collect images and identify features on the surfaces of the in-memory computing integrated circuit and the silicon wafer to obtain position information, and the time series prediction model is used to predict the deformation during the flip-chip process according to the position information to obtain dynamic compensation parameters; Based on the dynamic compensation parameters, the in-memory computing integrated circuit is flipped and pre-aligned to obtain a preliminary flip-chip structure, and a deep reinforcement learning algorithm is used for fine adjustment to obtain a flip-chip-silicon wafer structure with high-precision alignment; The welding parameters of the flip-chip-silicon wafer structure are optimized to obtain the optimal flip-chip welding process parameters, and thermocompression welding is performed according to the optimal parameters to obtain a single-layer flip-chip integrated structure; The machine vision system is used to detect the single-layer flip-chip integrated structure, analyze the welding interface characteristics of the single-layer flip-chip integrated structure to obtain a quality evaluation result, and based on the quality evaluation result, the subsequent stacking parameters are optimized to obtain multi-layer stacking process parameters; According to the multi-layer stacking process parameters, multiple single-layer flip-chip integrated structures are stacked layer by layer, and the stacking parameters are monitored and dynamically adjusted using an acoustic sensor during the layer-by-layer stacking process to obtain a multi-layer heterogeneous integration structure.

5. The chip multi-layer heterogeneous integration method according to claim 4, wherein The machine vision system is used to collect images and identify features on the surfaces of the in-memory computing integrated circuit and the silicon wafer to obtain position information, and the time series prediction model is used to predict the deformation during the flip-chip process according to the position information to obtain dynamic compensation parameters, including: The machine vision system is used to perform multi-spectral image collection on the surfaces of the in-memory computing integrated circuit and the silicon wafer to obtain multi-dimensional image data, and the microscopic structural features of the multi-dimensional image data are extracted and analyzed to obtain high-precision three-dimensional surface profile information; Based on the high-precision three-dimensional surface profile information, identify and locate the key alignment marks on the in-memory computing integrated chip and the silicon wafer surface to obtain position information, and use a time series prediction model to perform time series analysis on the position information to obtain position change trend data; According to the position information, combine the thermodynamic model and finite element analysis to simulate and calculate the deformation caused by thermal expansion and mechanical stress during the flip-chip process to obtain a deformation prediction result, and generate corresponding compensation parameter sensitivity data according to the deformation prediction result; Generate corresponding dynamic compensation parameters using a multi-objective optimization algorithm according to the compensation parameter sensitivity data.

6. The chip multi-layer heterogeneous integration method according to claim 4, wherein Use the machine vision system to detect the single-layer flip-chip integrated structure, analyze the welding interface characteristics of the single-layer flip-chip integrated structure to obtain a quality evaluation result, and based on the quality evaluation result, optimize the subsequent stacking parameters to obtain multi-layer stacking process parameters including: Perform multi-angle and multi-spectral imaging on the single-layer flip-chip integrated structure to obtain a multi-modal data set, and use a multi-modal image fusion algorithm to process the multi-modal data set to extract the comprehensive characteristics of the welding interface to obtain an enhanced welding interface image; Based on the welding interface image, use a deep learning image segmentation algorithm to accurately locate and extract the contour of the welding interface to obtain a three-dimensional reconstruction model of the welding interface, and extract microscopic morphology, void distribution, and metal interconnect structure characteristics from the three-dimensional reconstruction model to obtain quantitative interface characteristic parameters; Perform quality evaluation of the welding interface according to the quantitative interface characteristic parameters to obtain a quality evaluation result, and use a genetic algorithm to optimize and search the stacking process parameters according to the quality evaluation result to obtain a stacking parameter set; Generate statistical characteristics and reliability evaluation results of the stacking process based on the stacking parameter set, and based on the adaptive control strategy of the preset fuzzy PID, perform real-time monitoring and dynamic analysis on the statistical characteristics and reliability evaluation results during the stacking process to obtain multi-layer stacking process parameters.

7. A chip multi-layer heterogeneous integration device, characterized in that, The chip multi-layer heterogeneous integration device includes: A scheme design module, which is used to perform multi-objective optimization analysis and thermal distribution prediction modeling on the functional unit distribution, data flow pattern, and power consumption constraint of the in-memory computing integrated chip to obtain a thermal optimization layout scheme; according to the thermal optimization layout scheme, use a recurrent neural network to dynamically predict the performance of the in-memory computing integrated chip under different workloads to obtain a performance prediction model; based on the performance prediction model, use a graph neural network to perform in-depth learning analysis on the functional units and data flow of the in-memory computing integrated chip to obtain a task allocation strategy; based on the task allocation strategy, use a reinforcement learning algorithm to model and optimize the storage hierarchy of the in-memory computing integrated chip to obtain a storage optimization scheme; comprehensively combine the task allocation strategy and the storage optimization scheme, and use a multi-agent collaborative learning algorithm to perform collaborative optimization on the overall chip architecture to obtain an in-memory computing integrated chip design scheme; The micro-bump preparation module is used to perform deep learning modeling on the micro-bumps on the memory-computation integrated chip according to the memory-computation integrated chip design scheme, obtain the micro-bump design scheme, and perform electroplating treatment on the pads of the memory-computation integrated chip according to the micro-bump design scheme to obtain a micro-bump array; The through-silicon via preparation module is used to generate a through-silicon via distribution scheme for the silicon wafer corresponding to the memory-computation integrated chip based on the memory-computation integrated chip design scheme, and form a through-silicon via structure on the silicon wafer according to the through-silicon via distribution scheme; The flip-chip integration module is used to perform flip-chip processing on the memory-computation integrated chip with a micro-bump array by using a machine vision system and a time series prediction model, and perform multi-layer stacking with the silicon wafer with through-silicon vias to obtain a multi-layer heterogeneous integration structure.

8. A chip multi-layer heterogeneous integration device, characterized in that, The chip multi-layer heterogeneous integration device includes: a memory and at least one processor, and instructions are stored in the memory; The at least one processor calls the instructions in the memory so that the chip multi-layer heterogeneous integration device executes the steps of the chip multi-layer heterogeneous integration method described in any one of claims 1-6.

9. A computer-readable storage medium, on which instructions are stored, characterized in that, When the instructions are executed by the processor, the steps of the chip multi-layer heterogeneous integration method described in any one of claims 1-6 are implemented.

Images