Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof. An exemplary method includes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and connected to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask to form a first opening exposing the first dielectric layer, and forming a second opening exposing the second dielectric layer over the first opening. The method includes forming a patterned hard mask layer, forming a first opening on the patterned hard mask layer, forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after forming the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC dimensions (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] As device dimensions continue to shrink, the performance of back-end-of-line (BEOL) interconnect structures is subject to higher demands. In some examples, high parasitic capacitance can result in lower device speeds (e.g., RC delays) when the distance between two adjacent conductive features is reduced to meet design requirements at smaller technology nodes. Low dielectric constant (low-k) materials have been incorporated into interconnect structures to reduce capacitance. While the purpose of low-k materials is to reduce capacitance, their poor thermal conductivity poses challenges to heat dissipation in front-end-of-line (FEOL) devices. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a first dielectric layer above a first conductive component; forming a conductive via extending through the first dielectric layer and connected to the first conductive component; forming a hard mask layer above the conductive via; patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening; forming a porous dielectric layer on the sacrificial layer; after forming the porous dielectric layer, selectively removing the sacrificial layer to form an air gap; forming a second dielectric layer above the porous dielectric layer; and replacing the portion of the patterned hard mask layer directly disposed above the conductive via with the second conductive component.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a first dielectric layer above a substrate; patterning the first dielectric layer to form a groove separating the first dielectric layer into a first part and a second part; forming an insulating liner extending along the side wall surfaces of the first part and the second part of the first dielectric layer; forming a covering structure between the first part and the second part of the first dielectric layer to seal the groove to form an air gap, wherein the covering structure includes a dielectric liner extending along the bottom and side wall surfaces of a dielectric filling layer, wherein the thermal conductivity of the dielectric filling layer is higher than the thermal conductivity of the first dielectric layer; after forming the covering structure, selectively removing the first part and the second part of the first dielectric layer to form a first opening and a second opening; and forming a first conductive component and a second conductive component in the first opening and the second opening, respectively.

[0006] Yet another embodiment of the present invention provides a semiconductor structure comprising: a conductive via extending through a first dielectric layer; a first conductive component located above and in direct contact with the conductive via; and a second conductive component located above the first dielectric layer and separated from the first conductive component by a dielectric structure, wherein a top surface of the dielectric structure is coplanar with a top surface of the first conductive component, and the dielectric structure comprises: a bottom pad extending between the first conductive component and the second conductive component and in direct contact with the first dielectric layer, a top pad extending between the first conductive component and the second conductive component and in direct contact with the bottom pad, a second dielectric layer located above the top pad, wherein the top pad extends along a bottom and sidewall surface of the second dielectric layer, and an air gap defined by the bottom pad and the top pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a partial cross-sectional view of an exemplary semiconductor structure according to one or more aspects of the present disclosure.

[0009] Figure 2 is a flow chart of a method for forming an interconnect layer of a semiconductor structure according to one or more aspects of the present disclosure.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 According to one or more aspects of the present disclosure, Figure 2 Partial cross-sectional views of the workpiece at different manufacturing stages.

[0011] Fig.15 According to one or more aspects of the present invention Fig.14 A partial top view of the workpiece shown.

[0012] Fig.16 is a partial cross-sectional view of a first alternative workpiece according to one or more aspects of the present disclosure.

[0013] Fig.17 , Fig.18 , Fig.19 and Fig. 20 According to one or more aspects of the present disclosure, Figure 2 Partial cross-sectional views of a second alternative workpiece at different stages of manufacture in the method.

[0014] Fig.21 is a flow chart of another method of forming an interconnect layer of a semiconductor structure according to one or more aspects of the present disclosure.

[0015] Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 and Fig.31 According to one or more aspects of the present disclosure, Fig.21 Partial cross-sectional views of a third alternative workpiece during the method at different stages of manufacture.

[0016] Fig.32 is a partial cross-sectional view of a fourth alternative workpiece according to one or more aspects of the present disclosure.

[0017] Fig.33 is a partial cross-sectional view of a fifth alternative workpiece according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0018] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0020] In addition, when a number or a range of numbers is described using the term "approximately," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the number, the number or range includes a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, and it is known to those of ordinary skill in the art that the manufacturing tolerance associated with deposited material layers is + / - 15%. The source / drain regions may be referred to individually or collectively as source or drain, depending on the context.

[0021] As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a larger role in meeting power, performance, and area requirements. BEOL interconnect structures can include low-k dielectric materials to maintain low parasitic capacitance. In general, low-k dielectric materials have lower thermal conductivity than high-k dielectric materials, metals, or semiconductor materials. The low thermal conductivity of low-k dielectric materials prevents them from effectively dissipating the heat generated by FEOL devices. In addition, it becomes increasingly challenging to package all conductive components on one side of the substrate. In order to reduce the packaging density, the wiring components can be partially moved to the back side of the substrate. Such wiring components can include back super power rails (SPRs) and / or back contacts. The introduction of SPRs further exacerbates heat accumulation due to the increased distance between the device and the heat sink. The industry is scrambling to find a solution to achieve high thermal conductivity while maintaining low parasitic capacitance.

[0022] The present disclosure provides a method for forming a dielectric structure disposed between two adjacent conductive components for heat dissipation and capacitance reduction. In an example process, a through hole is formed in a low-k dielectric layer, and a hard mask layer is formed above the low-k dielectric layer and patterned to form an opening. A sacrificial polymer layer is then deposited to fill the lower portion of the opening. A support layer is deposited on the sacrificial polymer layer, and a high-κ dielectric material layer may be formed on the support layer to fill the upper portion of the opening. After forming the support layer, a heat treatment is performed to selectively remove the sacrificial polymer layer, thereby forming an air gap between each sheet of the patterned hard mask layer. The patterned hard mask layer may be replaced with a metal line. A high-κ (kappa) dielectric material layer formed of a material with good thermal conductivity helps dissipate heat. The air gap between the conductive components helps maintain low capacitance.

[0023] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a partial cross-sectional view of an exemplary semiconductor structure according to one or more aspects of the present disclosure. Figure 2 and Fig.21 1 is a flowchart illustrating a method 100 and a method 100' for forming an interconnect layer of a semiconductor structure according to one or more aspects of the present disclosure. Methods 100 and 100' are merely examples and are not intended to limit the present disclosure to what is explicitly shown in method 100 or method 100'. Additional steps may be provided before, during, and after method 100 or method 100', and some of the steps described may be replaced, eliminated, or moved for other embodiments of method 100 or 100'. For simplicity, not all steps are described in detail. Figures 3 to 20 Describing method 100, Figures 3 to 20 1 is a partial top view or cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. The method 100 will be described below in conjunction with Figures 22 to 33 1 , these figures are partial cross-sectional views of a workpiece 200' at different manufacturing stages according to an embodiment of the method 100'. Since the workpiece 200 / 200' will be manufactured into a semiconductor structure after the manufacturing process, the workpiece 200 / 200' may be referred to as a semiconductor structure 200 / 200' as required by the context. In addition, throughout the present application and in different embodiments, unless otherwise specified, the same reference numerals represent the same components with similar structures and compositions. Depending on the context, the source / drain region may be referred to as a source or a drain individually or collectively.

[0024] Figure 1 6 is a partial schematic cross-sectional view of various layers (or layers) that may be fabricated over a semiconductor substrate (or wafer) 60 to form a portion of a semiconductor structure according to various aspects of the present disclosure. Figure 1 As shown, each layer includes a device layer DL and a front multilayer interconnect structure FMLI disposed above the device layer DL. In various embodiments, the structure may also include a back multilayer interconnect structure BMLI disposed below the device layer DL. The back multilayer interconnect structure BMLI may be similar to the front multilayer interconnect structure FMLI.

[0025] The device layer DL includes devices (eg, transistors, resistors, capacitors, and / or inductors) and / or device components (eg, doped wells, gate structures, and / or source / drain features). Figure 1 In the illustrated embodiment, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation feature 64, and a transistor T. In the depicted embodiment, the transistor T includes a floating channel layer 70 disposed between source / drain features 72 and a gate structure 68, wherein the gate structure 68 wraps around and / or surrounds the floating channel layer 70. Each gate structure 68 has a metal gate stack formed of a gate electrode 74 disposed over a gate dielectric layer 76 and a gate spacer 78 disposed along a sidewall of the metal gate stack.

[0026] The multi-layer interconnect structures FMLI and BMLI electrically connect various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements. Each of the multi-layer interconnect structures FMLI and BMLI may include one or more interconnect layers. In the depicted embodiment, the front multi-layer interconnect structure FMLI includes a contact interconnect layer (CO level), a zero via interconnect layer (V0 level), a metal 0 interconnect layer (M0 level), a via 1 interconnect layer (V1 level), a metal 1 interconnect layer (M1 level), a via 2 interconnect layer (V2 level), a metal 2 interconnect layer (M2 level), a via 3 interconnect layer (V3 level), and a metal 3 interconnect layer (M3 level). Each of the CO level, V0 level, M0 level, V1 level, M1 level, V2 level, M2 level, V3 level, and M3 level may be referred to as a metal level. The metal line formed at the M0 level may be referred to as an M0 metal line. Similarly, vias or metal lines formed at the V1 level, M1 level, V2 level, M2 level, V3 level, and M3 level may be referred to as V1 vias, M1 metal lines, V2 vias, M2 metal lines, V3 vias, and M3 metal lines, respectively. The present disclosure contemplates a multilayer interconnect structure FMLI having more or fewer interconnect layers and / or levels, for example, N interconnect layers (levels) of the front multilayer interconnect structure FMLI, where N is an integer from 1 to 10. Each layer of the front multilayer interconnect structure FMLI includes conductive components (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and an etch stop layer (ESL)). The dielectric layers of the front multilayer interconnect structure FMLI are collectively referred to as a dielectric structure 66. In some embodiments, conductive components at the same level (e.g., M0 level) of the multilayer interconnect structure FMLI are formed simultaneously. In some embodiments, conductive features at the same level of the multilayer interconnect structure FMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other.

[0027] exist Figure 1In the illustrated embodiment, the CO stage includes a source / drain contact MD disposed in the dielectric structure 66. The source / drain contact MD may be formed on and in direct contact with a silicide layer disposed directly on the source / source feature 72. The V0 stage includes a gate via VG disposed on the gate structure 68 and a source / drain contact via VD disposed on the source / drain contact MD, wherein the gate via VG connects the gate structure 68 to the M0 metal line, and the source / drain via V0 connects the source / source contact MD to the M0 metal line. In some embodiments, the V0 stage may further include a docking contact disposed in the dielectric structure 66. The V1 stage includes a V1 via disposed in the dielectric structure 66, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 stage includes an M1 metal line disposed in the dielectric structure 66. The V2 stage includes a V2 via disposed in the dielectric structure 66, wherein the V2 via connects the M1 metal line to the M2 metal line. The M2 level includes an M2 metal line disposed in dielectric structure 66. The V3 level includes a V3 via disposed in dielectric structure 66, wherein the V3 via connects the M2 metal line to the M3 metal line. For clarity, Figure 1 It is simplified for better understanding of the inventive concepts of the present disclosure.

[0028] refer to Figure 2 and Figure 3 , method 100 includes block 102, wherein a workpiece 200 is received. Workpiece 200 includes dielectric layer 202. Dielectric layer 202 may include a low dielectric constant (low-k) dielectric material having a dielectric constant less than that of silicon oxide, which is approximately 3.9. For example, dielectric layer 202 may include a porous organosilicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, oxidized carbon nitride silicon (SiOCN), carbon boron nitride, spin-on silicon-based polymer dielectrics, or combinations thereof. In some cases, dielectric layer 202 may be referred to as an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD).

[0029] The workpiece 200 also includes a conductive feature (e.g., a via) 204 extending through the dielectric layer 202. The conductive feature may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), or molybdenum (Mo), or a combination thereof. In various embodiments, the conductive feature 204 may be one of the vias (e.g., a gate via VG, a source / drain contact via VD, a V1 via, a V2 via) of the front-side multilayer interconnect structure FMLI. In one embodiment, the conductive feature 204 is a source / drain contact via VD.

[0030] The workpiece 200 also includes a dielectric structure 206 disposed on the dielectric layer 202. In one embodiment, the dielectric structure 206 is a single-layer structure and is formed by a dielectric material layer, which may include a low dielectric constant (low-k) dielectric material, the dielectric constant of the low-k dielectric material being less than the dielectric constant of silicon oxide, which is about 3.9. For example, the dielectric material layer may include a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, oxidized carbon nitride silicon (SiOCN), carbon boron nitride, spin-on silicon polymer dielectrics, or combinations thereof. In some other embodiments, the dielectric structure 206 may be a double-layer structure including a dielectric material layer formed above an etch stop layer (ESL). In some embodiments, the ESL includes aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof.

[0031] The workpiece 200 also includes a first conductive component 208 extending through the dielectric structure 206 and in direct contact with the conductive component 204. The first conductive component 208 includes a barrier layer 208a extending along the bottom and sidewall surfaces of the metal filling layer 208b. The barrier layer 208a may include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN) or tantalum nitride (TaN). The metal filling layer 208b may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W) or molybdenum (Mo) or a combination thereof. In the illustrated example, the workpiece 200 represents two adjacent interconnect layers (e.g., CO layer and M0 layer) of the front multilayer interconnect structure FMLI. In an embodiment, the first conductive feature 208 represents one of the M0 metal lines and the conductive feature 204 represents one of the V0 vias. In other embodiments, the first conductive feature 208 represents one of the M1 metal lines and the conductive feature 204 represents one of the V1 vias.

[0032] Still refer to Figure 2 and Figure 3 , the method 100 includes a box 104, wherein a capping layer 212 is selectively deposited over the first conductive component 208. The capping layer 212 may also be referred to as a metal capping layer 212 or a conductive capping layer 212, and is formed of a metal different from the metal forming the barrier layer 208a and the metal fill layer 208b. In an embodiment where the metal fill layer 208b is formed of copper, the capping layer 212 may include titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), cobalt (Co), ruthenium (Ru), or tungsten (W). In an embodiment, the capping layer 212 includes cobalt (Co). In some embodiments, at box 104, the capping layer 212 is selectively deposited on the top surface of the first conductive component 208 by metal organic chemical vapor deposition (MOCVD) using metal organic precursors having metal ions and coordinating ligands, respectively. As Figure 3 As shown, due to the selectivity of formation, the capping layer 212 is only deposited on the top surface of the metal filling layer 208b, and does not exist on the surface of the dielectric structure 206 and the surface of the barrier layer 208a. The capping layer 212 inhibits the electromigration or protrusion formation of the metal filling layer 208b. In addition to reducing electromigration, the capping layer 212 can also repair damage caused to the metal filling layer 208b during the planarization process. In some other embodiments, the capping layer 212 can be deposited on the top surfaces of the metal filling layer 208b and the barrier layer 208a, and does not exist on the surface of the dielectric structure 206.

[0033] refer to Figure 2and Figure 4 , the method 100 includes a block 106, in which a first etch stop layer (ESL) 214, a second ESL 216, and a low dielectric constant (or low-k) dielectric material layer 218 are formed over the dielectric structure 206. In some embodiments, the first and second ESLs may include aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof, and may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma enhanced CVD (PECVD). In an example process, the first ESL 214 is conformally disposed over the workpiece 200, including on the top and sidewall surfaces of the capping layer 212, and then the second ESL 216 is conformally disposed on the first ESL 214. After forming the second ESL 216, a low-k dielectric material layer 218 is formed. The dielectric constant of the low-k dielectric material layer 218 is less than the dielectric constant of silicon oxide, which is approximately 3.9. For example, the low-k dielectric material layer 218 may include a porous organic silicate film (e.g., SiCOH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, oxidized carbon nitride silicon (SiOCN), carbon boron nitride, spin-on silicon-based polymer dielectrics, or combinations thereof. In some other embodiments, instead of forming two ESLs 214 and 216, a single layer of ESL is disposed between the low-k dielectric material layer 218 and the dielectric structure 206.

[0034] refer to Figure 2 and Figure 5, the method 100 includes block 108, in which a via 220 is formed to extend through the low-k dielectric material layer 218 and the first and second ESLs 214 and 216 to connect to the capping layer 212. In an example process, the low-k dielectric material layer 218 and the first and second ESLs 214 and 216 are patterned to form a via opening (now filled by the via 220) that exposes the capping layer 212. The patterning of the low-k dielectric material layer 218 and the first and second ESLs 214 and 216 may include a photolithography process and an etching process, such as depositing a photoresist layer, photolithographically patterning the photoresist layer, etching the low-k dielectric material layer 218 and the first and second ESLs 214 and 216 using the patterned photoresist layer as an etching mask, and selectively removing the photoresist layer. The photoresist layer may include a hydrocarbon and may be deposited using spin coating. The etching of the low-k dielectric material layer 218 and the first ESL 214 and the second ESL 216 may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. After forming the through-hole opening, the photoresist layer may be removed by ashing or selective etching. A metal layer is then deposited over the workpiece 200, including in the through-hole opening. In some embodiments, the metal layer (and the through-hole 220 formed thereby) includes ruthenium (Ru), tungsten (W), molybdenum (Mo), combinations thereof, or other suitable conductive materials that are not prone to diffusion problems. The metal layer may be deposited using ALD, CVD, plasma enhanced ALD (PEALD), PECVD, electroplating, or electroless deposition. After depositing the metal layer, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess metal layers, thereby exposing the top surface of the low-k dielectric material layer 218. After the planarization process, a through-hole 220 is formed in the through-hole opening. In order to reduce parasitic resistance, the through-hole 220 is formed of metal and does not include a barrier layer similar to the barrier layer 208a. Forming the unobstructed via 220 advantageously reduces the parasitic resistance (eg, contact resistance) of the workpiece 200 .

[0035] refer to Figure 2 and Figure 6, the method 100 includes a block 110, in which a third ESL 222 and a hard mask 224 are formed over the low-k dielectric material layer 218. After forming the through hole 220, the third ESL 222 and the hard mask 224 are deposited over the workpiece 200. The third ESL 222 may be similar to one of the first ESL 214 and the second ESL 216. The hard mask 224 may be deposited on the third ESL 222 using ALD, CVD, PEALD, or PECVD. In the illustrated example, the hard mask 224 is a double-layer structure and includes a first layer 224a and a second layer 224b formed on the first layer 224a. The first layer 224a and the second layer 224b have different compositions and may be formed of aluminum oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, or other suitable materials or combinations thereof.

[0036] refer to Figure 2 and Figure 7 , method 100 includes frame 112, wherein hard mask 224 and third ESL 222 are patterned to form one or more openings (e.g., openings 226a and 226b). The patterning of hard mask 224 and third ESL 222 may include a photolithography process and an etching process. In the depicted embodiment, the operations in frame 112 include depositing a photoresist layer (not shown), photolithographically patterning the photoresist layer, etching hard mask 224 and third ESL 222 using the patterned photoresist layer as an etching mask to form openings, and selectively removing the photoresist after forming the openings. In the depicted example, the patterning of hard mask 224 and third ESL 222 forms openings 226a and 226b, and the patterned hard mask 244 includes three portions 224A, 224B, and 224C separated by two openings 226a, 226b. In the present embodiment, since the dielectric material layer 218 is a low-k dielectric material layer, the etchant used in the patterning process of the hard mask 224 and the third ESL 222 may also slightly etch the low-k dielectric layer 218. As a result, openings (e.g., openings 226a and 226b) extend into the low-k dielectric material layer 218. The openings 226a and 226b may be individually or collectively referred to as openings 226.

[0037] refer to Figure 2 and Figure 8, the method 100 includes block 114, in which a dielectric liner 228 is formed over the workpiece 200. In an embodiment, the dielectric liner 228 is conformally deposited over the workpiece 200, including in the two openings 226a and 226b, using ALD, CVD, plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), or other suitable methods. To facilitate describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The deposited thickness of the dielectric liner 228 may be about Peace between.

[0038] In an embodiment, the dielectric liner 228 is formed of a material having a dielectric constant in the range of 3.5 to 5 and a thermal conductivity (kappa) less than 5 W / mK. For example, the dielectric liner 228 includes silicon oxycarbonitride. In another alternative embodiment, the dielectric liner 228 is formed of a material having a thermal conductivity (kappa) greater than 5 W / mK. For example, the dielectric liner includes boron nitride having a thermal conductivity in the range of 5 to 400 W / mK. In the present disclosure, a dielectric material having a thermal conductivity less than 5 W / mK may be referred to as a low kappa dielectric material, and a dielectric material having a thermal conductivity not less than 5 W / mK may be referred to as a high kappa dielectric material.

[0039] Still refer to Figure 2 and Figure 8 , the method 100 includes a frame 116, wherein a sacrificial layer 230 is formed on the dielectric liner 228 to partially fill the opening 226. In an example process, a polymer layer is deposited over the workpiece 200, including in the opening 226. The polymer layer can be deposited by using CVD, PECVD, flowable CVD (FCVD), ALD, PEALD, or spin coating. The deposited polymer layer can be heated to increase its fluidity so as to have a smoother top surface. A curing process can then be performed to cure the polymer layer. In some cases, the curing process may include a baking process, an annealing process, a drying process, or an ultraviolet (UV) radiation process. The cured polymer layer is then planarized and selectively etched back to form a sacrificial layer 230 at the lower portion of the opening 226. The etch back of the polymer layer is used to define the height of the air gap 234.

[0040] Although the sacrificial layer 230 will be removed in a subsequent step, it is selected to withstand the planarization process and the deposition of the support layer 232 (described below) without structural damage. For these reasons, the sacrificial layer 230 needs to be easy to remove and remain stable around the deposition temperature of the support layer. Based on these criteria, the sacrificial layer 230 can include polyvinyl alcohol (PVA), polyacrylate, polycarbonate (PC), or other suitable polymers.

[0041] refer to Figure 2 and Fig. 9 , the method 100 includes block 118, in which a support layer 232 is formed over the workpiece 200. Fig. 9 In the illustrated embodiment, a low-k dielectric material is conformally deposited over the workpiece 200, including the sacrificial layer 230 and the dielectric liner 228, to form a support layer 232 having a porous structure and covering the sacrificial layer 230. In some embodiments, the support layer 232 has a porous structure. The deposition for forming the support layer 232 can be achieved by PECVD, PEALD, ALD, CVD, other suitable processes, or combinations thereof. In one embodiment, the support layer 232 includes silicon oxide.

[0042] Still refer to Figure 2 and Fig. 9 , the method 100 includes block 120, in which the sacrificial layer 230 is selectively removed to form an air gap 234 between the dielectric liner 228 and the support layer 232. In some embodiments, a thermal treatment (e.g., an annealing process, a baking process) and / or an ultraviolet process may be performed to decompose the sacrificial layer 230 into volatile compounds that may diffuse through the porous structure of the support layer 232. The air gap 234 is formed by removing the sacrificial layer 230. Fig. 9 As shown, the air gap is defined by the dielectric liner 228 and the sustaining layer 232. In the example shown, an air gap 234 is formed between portions 224A and 224B of the patterned hard mask 224, and another air gap 234 is provided between portions 224B and 224C of the patterned hard mask 224. Because the dielectric constant of air is close to 1, the air gap 234 reduces the effective dielectric constant of the dielectric structure in the second conductive features (e.g., second conductive structures 242a to 242c).

[0043] refer to Figure 2 and Fig.10, method 100 includes box 122, in which a high thermal conductivity (high kappa) dielectric material layer 236 is formed over support layer 232 using ALD, CVD, plasma enhanced CVD (PECVD), or microwave PECVD. In some embodiments, high kappa dielectric material layer 236 may include diamond, diamond-like carbon, or aluminum nitride (AlN). The thermal conductivity of diamond may be in the range between about 100 W / mK and 2000 W / mK. The thermal conductivity of aluminum nitride may be in the range of about 5 W / mK to 300 W / mK. In some embodiments, high kappa dielectric material layer 236 may include silicon nitride having a thermal conductivity greater than 5 W / mK. In some embodiments, high kappa dielectric material layer 236 includes diamond or diamond-like carbon. For embodiments in which high kappa dielectric material layer 236 has a porous structure, sacrificial layer 230 may be selectively removed after forming high kappa dielectric material layer 236.

[0044] refer to Figure 2 and Fig.11 , the method 100 includes a block 124, in which the workpiece 200 is planarized to expose the patterned hard mask 224. After forming the high-kappa dielectric material layer 236, a planarization process is performed on the workpiece 200. In one embodiment, the planarization process stops after exposing the top surface of the first layer 224a of the hard mask 224. After the planarization process is completed, the topmost surface of the support layer 232, the topmost surface of the dielectric liner 228, and the top surface of the high-kappa dielectric material layer 236 are coplanar. The support layer 232 extends along the bottom and sidewall surfaces of the high-kappa dielectric material layer 236 and is in direct contact with the dielectric liner 228.

[0045] refer to Figure 2 and Fig.12 , the method 100 includes a frame 126, wherein the patterned hard mask 224 and the third ESL 222 are selectively removed to form openings 238a to 238c. After performing a planarization process to expose the top surface of the first layer 224a of the hard mask 224, an etching process is performed to selectively etch the exposed first layer 224a of the hard mask 224 and the third ESL 222 thereunder, without substantially etching the dielectric liner 228. In the illustrated example, the etching process removes portions 224A, 224B, and 224C and the third ESL 222 thereunder, thereby forming openings 238a, 238b, and 238c, respectively. The number of openings is only an example and is not intended to be limiting. Openings 238a and 238c expose the top surface of the low-k dielectric material layer 218, and opening 238b exposes the top surface of the through hole 220.

[0046] refer to Figure 2 and Fig.13 , Fig.14 , Fig.15 , the method 100 includes block 128, wherein second conductive features 242a to 242c are formed in the openings 238a to 238c, respectively. Fig.13 , a conductive barrier layer 240a is conformally formed over the workpiece 200, including in the openings 238a to 238c. The barrier layer 240a may include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN) or tantalum nitride (TaN), and may be formed by ALD, CVD, PEALD, PECVD or other suitable processes. Then, a metal fill layer 240b is deposited over the conductive barrier layer 240a and in the openings 238a to 238c. The metal fill layer 240b may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W) or molybdenum (Mo), or a combination thereof, and may be formed by ALD, CVD, PEALD, PECVD, chemical plating or other suitable processes.

[0047] refer to Fig.14 After forming the metal filling layer 208b, a planarization process is performed to remove excess portions of the metal filling layer 240b and the conductive barrier layer 240a to form second conductive components 242a, 242b, and 242c in the openings 238a to 238c, respectively. The top surfaces of the second conductive components 242a, 242b, and 242c are planar and coplanar with the top surface of the high-kappa dielectric material layer 236. The second conductive component 242b is disposed above the through hole 220 and in direct contact with the through hole 220. In this embodiment, the metal filling layer 240b of the second conductive component 242b is physically isolated from the through hole by the conductive barrier layer 240a. The second conductive structure 242b is separated from the adjacent second conductive components 242a and 242c by a dielectric structure 246, which is composed of a dielectric liner 228, a support layer 232, an air gap 234 defined by the dielectric liner 228 and the support layer 232, and a high-kappa dielectric material layer 236 wrapped by the support layer 232. The formation of the air gap 234 reduces the effective dielectric constant of the dielectric structure between two adjacent second conductive components (e.g., 242a and 242b), thereby advantageously reducing parasitic capacitance. The implementation of the high-kappa dielectric material layer 236 will advantageously improve heat dissipation, thereby improving reliability. Fig.15 Depicted Fig.14 A top view of a portion of the workpiece shown. More specifically, Fig.15A second conductive feature 242b, a via 220, and a first conductive feature 208 are shown. In the illustrated example, the first conductive feature 208 extends longitudinally along the X direction, and the second conductive feature 242b extends longitudinally along the Y direction that is substantially perpendicular to the X direction. In some embodiments, the second conductive features 242a-242c may be M2 metal lines, the first conductive feature 208 may be one of the M1 metal lines, and the via 220 may be one of the V1 vias.

[0048] After forming the second conductive features 242a to 242c, further processes may be performed. For example, operations 104 to 128 may be repeated to form an interconnect layer over the second conductive features 242a to 242c. Such further processes may include forming a backside multilayer interconnect structure BMLI under the device layer DL.

[0049] In the above-described embodiment, the air gap 234 and the dielectric liner 228 extend into the low-k dielectric material layer 218, and the bottommost surface of the dielectric liner 228 is substantially planar. In some other embodiments, depending on the composition of the low-k dielectric material layer 218, the composition of the third ESL 222, and the etchant used in the patterning process of the hard mask 224 in the frame 112, the opening 226 can have a different profile, and therefore, the dielectric liner 228 can have a different profile. Fig.16 Another embodiment is shown in which the dielectric liner 228 has a Fig.14 Different outlines shown.

[0050] In the above embodiment, the metal filling layer 240b of the second conductive component 242b is physically separated from the via 220 by the conductive barrier layer 240a. In an alternative embodiment, the metal filling layer 240b of the second conductive component 242b may directly contact the via 220 to further reduce parasitic resistance. Figures 17 to 20 Depicted are partial cross-sectional views of a workpiece during various manufacturing steps of forming second conductive features 242 a - 242 c according to this alternative embodiment, wherein the metal-fill layer 240 b of the second conductive structure 242 b is in direct contact with the via 220 .

[0051] refer to Fig.17 and Fig.12 , in forming the openings 238a to 238c (such as Fig.12After the barrier layer 250 is selectively formed on the metal surface, but not on the dielectric surface, the barrier layer 250 is formed. In one embodiment, the barrier layer 250 is selectively deposited on the exposed top surface of the through hole 220, and there is no barrier layer 250 on the top surface of the low-k dielectric material layer 218. The barrier layer 250 can be formed by applying an inhibitor using chemical vapor deposition (CVD), spin coating, or spray coating techniques. The molecules of the inhibitor can include silicon, carbon-based polymers (e.g., benzotriazole (BTA), carbon layers, graphene, graphite), or self-aligned molecules (e.g., octadecylphosphonic acid, thiol).

[0052] Reference Fig.18 After forming the barrier layer 250, a conductive barrier layer 240a is deposited on the workpiece 200. Fig.13 The formation and composition of the conductive barrier layer 240a are described above, and therefore, repeated descriptions are omitted for simplicity. The barrier layer 250 prevents the conductive barrier layer 240a from being directly disposed thereon. That is, after the deposition of the conductive barrier layer 240a is completed, as shown in FIG. Fig.18 As shown, the opening 238b still exposes the top surface of the barrier layer 250. It is worth noting that since both ends of the barrier layer 250 are disposed adjacent to the dielectric liner 228, the portion of the conductive barrier layer 240a extending along the sidewall surface of the dielectric liner 228 is in direct contact with the barrier layer 250.

[0053] Reference Fig.19 After forming the conductive barrier layer 240a, the barrier layer 250 is selectively removed. The barrier layer 250 may be selectively removed by heat, plasma treatment, or wet chemical methods. Removing the barrier layer 250 exposes the entire top surface of the through hole 220.

[0054] refer to Fig. 20 , and then depositing a metal filling layer 240b over the workpiece 200, including in the openings 238a to 238c. A planarization process is performed to remove excess portions of the conductive barrier layer 240a and the metal filling layer 240b, thereby defining the final structure of the second conductive components 242a, 242b, and 242c. Fig. 20 In the cross-sectional view shown, the metal filling layer 240b of the second conductive component 242b is in direct contact with the through hole 220. A portion of the metal filling layer 240b of the second conductive component 242b is directly disposed under the conductive barrier layer 240a. The metal filling layer 240b of the second conductive components 242a and 242c is isolated from the low-k dielectric material layer 218 by the conductive barrier layer 240a. Since no barrier layer is directly disposed between the through hole 220 and the metal filling layer 240b, the parasitic resistance of the workpiece 200 can be advantageously reduced.

[0055] In reference Figures 2 to 20In the above described embodiment, the method 100 includes forming a high kappa dielectric material layer 236 on the air gap 234 to improve heat dissipation. Fig.21 In the alternative method 100 ′ shown, a high-kappa material layer may be disposed below the air gap 234 to improve heat dissipation. For example, a high-kappa material layer may be deposited in place of the low-k dielectric material layer 218 .

[0056] refer to Fig.21 and 22 The method 100' includes a block 102, wherein a workpiece 200 (eg, Figure 3 ), and block 104, wherein a capping layer 212 (such as Figure 3 For ease of description, when describing the alternative method 100', Figure 3 The workpiece 200 depicted in FIG. 2 is referred to as workpiece 200 ′.

[0057] Still refer to Fig.21 and Fig. 22 , the method 100' includes a block 106', wherein a first etch stop layer (ESL) 214, a second ESL 216, and a high kappa dielectric material layer 218' are formed on the dielectric structure 206. The formation and composition of the first ESL 214 and the second ESL 216 have been described above with reference to block 106 of the method 100, and therefore repeated descriptions are omitted for the sake of brevity. Then, a high kappa dielectric material layer 218' is formed on the second ESL 216 using ALD, PEALD, CVD, plasma enhanced CVD (PECVD), or microwave PECVD. In some embodiments, the high kappa dielectric material layer 218' may include diamond, diamond-like carbon, or aluminum nitride (AlN). The thermal conductivity of diamond may be in the range of about 100 W / mK to 2000 W / mK. The thermal conductivity of aluminum nitride may be between about 5 W / mK and 300 W / mK. In some embodiments, the high kappa dielectric material layer 218 ′ may include silicon nitride having a thermal conductivity greater than 5 W / mK.

[0058] refer to Fig.21 and Fig.23 , the method 100' includes a block 108', in which a via 220' is formed to extend through the high kappa dielectric material layer 218' and the first ESL 214 and the second ESL 216 to connect to the capping layer 212. The via 220' is substantially similar to the via 220, and the operations of the block 108' are similar to the operations in the block 108. Therefore, for the sake of brevity, a detailed description of the operations at the block 108' is omitted.

[0059] refer to Fig.21 and Fig.24, the method 100' includes block 110', where a third ESL 222 and a hard mask 224 are formed over the high kappa dielectric material layer 218'. The operations at block 110' are similar to the operations in block 110. Therefore, for the sake of brevity, a detailed description of the operations at block 110' is omitted.

[0060] refer to Fig.21 and Fig.25 , method 100 includes box 112', in which the hard mask 224 and the third ESL 222 are patterned to form one or more openings (e.g., openings 226a' and 226b'). The operation of box 112' is similar to the operation in box 112. Therefore, for the sake of brevity, a detailed description of the operation at box 112' is omitted. However, in the present embodiment, the etchant used in the patterning process of the hard mask 224 and the third ESL 222 does not substantially damage the high kappa dielectric material layer 218'. That is, after the hard mask 224 and the third ESL 222 are patterned, the openings 226a' and 226b' do not extend into the high kappa dielectric material layer 218'. Openings 226a' and 226b' may be referred to individually or collectively as openings 226'.

[0061] refer to Fig.21 and Fig.26 , the method 100' includes a block 114, wherein a dielectric liner 228 is formed. Figure 8 The operation at block 114 is described, so a repeated description is omitted for the sake of brevity.

[0062] Still refer to Fig.21 and Fig.26 , the method 100' includes block 116, wherein a sacrificial layer 230 is formed on the dielectric liner 228 to partially fill the opening 226'. Figure 8 The operation at block 116 is described, so a repeated description is omitted for the sake of brevity.

[0063] refer to Fig.21 and Fig. 27 The method 100' includes a block 118 in which a support layer 232 is formed over the workpiece 200'. Fig. 9 The operation at block 118 is described, and thus, a repeated description is omitted for the sake of brevity.

[0064] Still refer to Fig.21 and Fig. 27 , the method 100 ′ includes block 120, wherein the sacrificial layer 230 is selectively removed to form an air gap 234 between the dielectric liner 228 and the support layer 232. Fig. 9 The operation at block 120 is described, and thus a repeated description is omitted for the sake of brevity.

[0065] refer to Fig.21 and Fig.28 , the method 100' includes a block 122', in which a low-k dielectric material layer 236' is formed over the support layer 232 using ALD, CVD, plasma enhanced CVD (PECVD), or microwave PECVD. The dielectric constant of the low-k dielectric material layer 236' is less than the dielectric constant of silicon oxide, which is about 3.9. For example, the low-k dielectric material layer 236' may include a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, oxidized carbon nitride silicon (SiOCN), carbon boron nitride, spin-on silicon polymer dielectrics, or a combination thereof. In some embodiments, the sacrificial layer 230 may be selectively removed after the low-k dielectric material layer 236' is formed. In another alternative embodiment, rather than forming a low-k dielectric material layer 236 ′ over the support layer 232 , a high-kappa dielectric material film 236 may be formed over the support layer 32 to further increase heat dissipation.

[0066] refer to Fig.21 and Fig.29 , the method 100' includes a block 124, in which the workpiece 200' is planarized to expose the patterned hard mask 224. Fig.11 The operation at block 124 is described, so a repeated description is omitted for the sake of brevity.

[0067] refer to Fig.21 and Fig.30 , the method 100 ′ includes block 126 , wherein the patterned hard mask layer 224 and the third ESL 222 are selectively removed to form openings 238 a to 238 c . Fig.12 The operation at block 126 is described, so a repeated description is omitted for the sake of brevity.

[0068] refer to Fig.21 and Fig.31 , the method 100 includes a block 128, wherein second conductive features 242a to 242c are formed in the openings 238a to 238c, respectively. Figures 13 to 15 The operation of block 128 is described, and repeated description is omitted for brevity. In some other alternative embodiments, such as Fig.32 As shown, the second conductive components 242a to 242c can refer to Figures 17 to 20 The description is formed in this way, so the repeated description is omitted for the sake of brevity. Fig.32In the partial cross-sectional view shown, the second conductive components 242a and 242c are in direct contact with the high-kappa dielectric material layer 218', and the metal filling layer 240b of the second conductive component 242b is in direct contact with the via 220'.

[0069] In the above embodiment, the first conductive component 208 can be referred to as a metal line extending along the X direction. Fig.33 As shown, the first conductive feature 208 may be referred to as a via. For example, the first conductive feature 208 may be one of the vias located in the CO layer.

[0070] Although not limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. For example, the present invention provides a dielectric structure disposed between two adjacent conductive components and a method for forming the same. The dielectric structure includes a layer of high kappa dielectric material to facilitate heat dissipation. The dielectric structure also includes an air gap to reduce the effective dielectric constant of the dielectric structure and the parasitic capacitance of the semiconductor structure.

[0071] The present disclosure provides many different embodiments. Semiconductor structures and methods for manufacturing the same are disclosed herein. In one exemplary aspect, the present disclosure relates to a method. The method includes forming a first dielectric layer over a first conductive component, forming a conductive via extending through the first dielectric layer and connected to the first conductive component, forming a hard mask layer over the conductive via, patterning the hard mask to form a first opening exposing the first dielectric layer, forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer over the sacrificial layer, after forming the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask directly disposed over the conductive via with the second conductive component.

[0072] In some embodiments, the method may further include conformally depositing a dielectric liner before forming the sacrificial layer, wherein the air gap may be between the dielectric liner and the porous dielectric layer. In some embodiments, the first dielectric layer may include a low dielectric constant material layer. In some embodiments, the first opening may penetrate into the first dielectric layer. In some embodiments, the second dielectric layer may include a high thermal conductivity dielectric material layer. In some embodiments, the conductive via may be formed by Ru, Mo, or W. In some embodiments, the formation of the sacrificial layer may include depositing a polymer layer, a planarizing polymer layer, and etching back the polymer layer above the first dielectric layer. In some embodiments, the method may further include forming an etch stop layer between the first dielectric layer and the hard mask layer, wherein the patterning of the hard mask further patterns the etch stop layer, and wherein replacing the patterned hard mask portion with a second conductive component may include performing a planarization process to expose the patterned hard mask layer, selectively removing a portion of the patterned hard mask layer and a portion of the etch stop layer thereunder to form a second opening, and forming a second conductive component in the second opening. In some embodiments, the second conductive component may include a barrier layer extending along the sidewalls and bottom surface of the metal fill layer. In some embodiments, the first dielectric layer may include a high thermal conductivity dielectric material layer, and the second dielectric layer may include a low dielectric constant material layer.

[0073] In another exemplary aspect, the present disclosure relates to a method. The method includes forming a first dielectric layer over a substrate, patterning the first dielectric layer to form a trench separating the first dielectric layer into a first portion and a second portion, forming an insulating liner extending along sidewall surfaces of the first and second portions of the first dielectric layer, forming a capping structure between the first and second portions of the first dielectric layer to seal the trench to form an air gap, wherein the capping structure may include a dielectric liner extending along a bottom and sidewall surfaces of a dielectric filling layer, wherein the dielectric filling layer has a higher thermal conductivity than the first dielectric layer, after forming the capping structure, selectively removing the first and second portions of the first dielectric layer to form a first opening and a second opening, and forming a first conductive component and a second conductive component in the first opening and the second opening, respectively.

[0074] In some embodiments, the formation of the capping structure may include forming a polymer layer on the insulating liner to partially fill the trench, conformally depositing a first dielectric material layer over the polymer layer and the insulating liner, depositing a second dielectric material on the first dielectric material layer, selectively removing the polymer layer after depositing the first dielectric material layer to form an air gap, and performing a planarization process to remove portions of the patterned first dielectric layer, the first dielectric material layer, and the second dielectric material layer to form the capping structure. In some embodiments, the dielectric filling layer may include diamond or aluminum nitride. In some embodiments, selectively removing the polymer layer may include performing a heat treatment. In some embodiments, the method may further include forming a conductive via embedded in the second dielectric layer and below the first dielectric layer, wherein the second opening exposes the conductive via and the first opening exposes the second dielectric layer. In some embodiments, the formation of the first conductive component and the second conductive component may include, after forming the first opening and the second opening, selectively forming a barrier layer on the conductive via, depositing a conductive barrier layer in the first opening and the second opening without forming the conductive component on the barrier layer, selectively removing the barrier layer after depositing the conductive barrier layer, forming a metal layer on the conductive barrier layer, and removing portions of the metal layer and the conductive barrier layer on the capping structure. In some embodiments, the dielectric liner may include diamond or aluminum nitride.

[0075] In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a conductive via extending through a first dielectric layer, a first conductive component over and in direct contact with the conductive via, and a second conductive component over the first dielectric layer and separated from the first conductive component by a dielectric structure, wherein a top surface of the dielectric structure is coplanar with a top surface of the first conductive component, and wherein the dielectric structure includes a bottom liner extending between the first and second conductive structures and in direct contact with the first dielectric layer, a top liner extending between and in direct contact with the first and second conductive components, a second dielectric layer over the top liner, wherein the top liner extends along a bottom surface and sidewall surfaces of the second dielectric layer, and an air gap defined by the bottom liner and the top liner.

[0076] In some embodiments, the second dielectric layer may include diamond or aluminum nitride (AlN), and the first dielectric layer may include a low-k dielectric material. In some embodiments, the semiconductor structure may further include a third conductive component embedded in the third dielectric layer and disposed below the first dielectric layer, and a metal cover disposed on the third conductive component and in direct contact with the third conductive component and the first conductive component, and the bottom pad may extend into the third dielectric layer.

[0077] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first dielectric layer over the first conductive feature; forming a conductive via extending through the first dielectric layer and connected to the first conductive feature; forming a hard mask layer over the conductive via; patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening; forming a porous dielectric layer on the sacrificial layer; After forming the porous dielectric layer, selectively removing the sacrificial layer to form an air gap; forming a second dielectric layer over the porous dielectric layer; as well as A portion of the patterned hard mask layer disposed directly over the conductive via is replaced with a second conductive feature.

2. The method according to claim 1, further comprising: A dielectric liner is conformally deposited before forming the sacrificial layer, wherein the air gap is located between the dielectric liner and the porous dielectric layer.

3. The method according to claim 1, wherein: The first dielectric layer includes a low dielectric constant material layer.

4. The method according to claim 3, wherein: The first opening penetrates into the first dielectric layer.

5. A method for forming a semiconductor structure, comprising: forming a first dielectric layer over the substrate; patterning the first dielectric layer to form a trench separating the first dielectric layer into a first portion and a second portion; forming an insulating liner extending along sidewall surfaces of the first portion and the second portion of the first dielectric layer; forming a capping structure between the first portion and the second portion of the first dielectric layer to seal the trench to form an air gap, wherein the capping structure comprises a dielectric liner extending along a bottom and sidewall surface of a dielectric filling layer, wherein the dielectric filling layer has a higher thermal conductivity than the first dielectric layer; After forming the capping structure, selectively removing the first portion and the second portion of the first dielectric layer to form a first opening and a second opening; and A first conductive feature and a second conductive feature are formed in the first opening and the second opening, respectively.

6. The method according to claim 5, wherein: Forming the covering structure comprises: forming a polymer layer over the insulating liner to partially fill the trench; conformally depositing a first layer of dielectric material over the polymer layer and the insulating liner; depositing a second dielectric material layer over the first dielectric material layer; selectively removing the polymer layer after depositing the first dielectric material layer to form an air gap; and A planarization process is performed to remove portions of the patterned first dielectric layer, portions of the first dielectric material layer, and portions of the second dielectric material layer to form the capping structure.

7. The method according to claim 6, wherein: The dielectric filling layer includes diamond or aluminum nitride.

8. A semiconductor structure comprising: a conductive via extending through the first dielectric layer; A first conductive component, located above the conductive through hole and in direct contact with the conductive through hole; as well as a second conductive component located above the first dielectric layer and separated from the first conductive component by a dielectric structure, Wherein, the top surface of the dielectric structure is coplanar with the top surface of the first conductive component, and the dielectric structure comprises: a bottom pad extending between the first conductive component and the second conductive component and in direct contact with the first dielectric layer, a top pad extending between the first conductive component and the second conductive component and in direct contact with the bottom pad, a second dielectric layer overlying the top liner, wherein the top liner extends along a bottom and sidewall surface of the second dielectric layer, and An air gap is defined by the bottom gasket and the top gasket.

9. The semiconductor structure according to claim 8, wherein: The second dielectric layer includes diamond or aluminum nitride (AlN), and the first dielectric layer includes a low-k dielectric material.

10. The semiconductor structure according to claim 8, further comprising: a third conductive component embedded in the third dielectric layer and disposed below the first dielectric layer; as well as a metal cover, disposed on the third conductive component and in direct contact with the second conductive component and the first conductive component, Wherein, the bottom liner extends into the third dielectric layer.

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