Stacked chip lead bonding packaging structure and preparation method

Abstract

The invention discloses a stacked chip lead bonding packaging structure and a preparation method. The preparation method comprises the following steps: preparing a temporary bonding adhesive film layer on the surface of a glass slide; preparing a metal anti-reflection layer on the surface of the temporary bonding adhesive film layer; preparing a rewiring layer on the metal anti-reflection layer; mounting and stacking a chip group on the surface of the rewiring layer; performing plastic packaging; removing the glass slide, and exposing the temporary bonding adhesive film layer; removing the temporary bonding glue layer to expose the metal anti-reflection layer; removing the metal anti-reflection layer to expose the metal bonding pad; solder balls are arranged on the metal bonding pads; and grinding and cutting to obtain the packaging body. According to the invention, the rewiring layer is used for replacing an organic substrate, a plurality of chips are mounted on the rewiring layer, interconnection among the chips is carried out through lead bonding, and signals are connected to the rewiring layer through lead bonding, so that the organic substrate is omitted, the risk of material breakage caused by imbalance of supply and demand is avoided, and the packaging cost is reduced; the method is suitable for industrial popularization.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a stacked chip wire bonding packaging structure and a preparation method thereof. Background Art

[0002] The stacked chip wire bonding packaging structure has a broad application market in storage and other fields. In this packaging structure, the stacked chips are usually mounted on an organic substrate, and the chips are interconnected by wire bonding, and the signals are transmitted to the organic substrate by wire bonding. In this packaging structure, the thickness of the substrate is usually several hundred microns, which is not conducive to the thinness of the packaging structure. In addition, the production capacity of the packaging substrate is very scarce, and the risk of material shortage of the packaging substrate is high. The imbalance between supply and demand leads to high prices of organic substrates, which significantly increases the packaging cost.

[0003] Therefore, the present invention discloses a stacked chip wire bonding packaging structure and a preparation method thereof. Summary of the invention

[0004] In order to solve the technical problems existing in the prior art, the object of the present invention is to provide a stacked chip wire bonding packaging structure and a preparation method thereof.

[0005] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0006] A method for preparing a stacked chip wire bonding packaging structure comprises the following steps:

[0007] Step 1: Prepare a temporary bonding film layer on the surface of the glass slide;

[0008] Step 2: preparing a metal anti-reflection layer on the surface of the temporary bonding film layer;

[0009] Step 3: Prepare a redistribution layer on the metal anti-reflection layer;

[0010] Step 4: Surface mount the stacked chipset on the redistribution layer;

[0011] Step 5: Use plastic packaging material to perform wafer-level plastic packaging to wrap the entire stacked chipset;

[0012] Step 6: Remove the glass slide to expose the temporary bonding film layer;

[0013] Step 7: Remove the temporary bonding layer to expose the metal anti-reflection layer;

[0014] Step 8: Remove the metal anti-reflection layer to expose the metal pads on the redistribution layer;

[0015] Step 9: Set solder balls on metal pads;

[0016] Step 10: Get the final package by grinding and cutting.

[0017] Furthermore, in Step 2, the metal anti-reflection layer is made of metal aluminum or titanium copper, and has a thickness of 0.1-3 microns.

[0018] Furthermore, in Step 3, the redistribution layer comprises a plurality of passivation layers and metal circuit layers which are alternately arranged in sequence, the bottom of the redistribution layer forms a metal pad for connecting to the solder ball, and the top of the redistribution layer forms a pad I for subsequent wire bonding.

[0019] Furthermore, in Step 4, the stacked chipset includes a plurality of chips arranged in sequence from bottom to top, with all the chips facing upward, and the mounting of two adjacent chips is staggered in sequence, so that the pad II for wire bonding is fully exposed, and the chips and the redistribution layer are electrically interconnected.

[0020] Furthermore, in Step 4, the stacked chip group includes several groups of vertically stacked branch units, each group of vertically stacked branch units includes several chips arranged in sequence from bottom to top, all chips are facing up, the mounting of two adjacent chips is staggered in sequence, the pad II used for wire bonding is completely exposed, and the chips and the chip and the redistribution layer are electrically interconnected.

[0021] Furthermore, adjacent chips are physically connected via a die bonding layer, and electrical interconnection between chips and signal conduction between chips and a redistribution layer are achieved via wire bonding.

[0022] Furthermore, in Step 6, the glass carrier is removed by using a laser debonding process to expose the temporary bonding film layer.

[0023] Furthermore, in Step 7, the temporary bonding adhesive layer is removed by using a chemical wet cleaning method or a plasma dry cleaning method to expose the metal anti-reflection layer.

[0024] Furthermore, in Step 8, the metal anti-reflection layer is removed by wet etching to expose the metal pad.

[0025] The present invention also discloses a stacked chip wire bonding packaging structure, comprising a plastic package and a stacked chip group wrapped therein, wherein the stacked chip group is mounted on a redistribution layer, wherein the redistribution layer comprises a plurality of passivation layers and metal circuit layers which are alternately arranged in sequence, a metal pad is arranged at the bottom of the redistribution layer, a solder ball is arranged on the metal pad, a solder pad I is arranged at the top of the redistribution layer, all chips of the stacked chip group face up, two adjacent chips are mounted staggered in sequence, and solder pad II used for wire bonding is completely exposed, adjacent chips are physically connected through a die bonding layer, and electrical interconnection between chips and signal conduction between chips and the redistribution layer are achieved through wire bonding.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention discloses a stacked chip wire-bonded packaging structure and a preparation method thereof, wherein a redistribution layer is used to replace an organic substrate, a plurality of chips are mounted on the redistribution layer, wire bonding is used to interconnect the chips, and signals are connected to the redistribution layer through wire bonding, thereby omitting an organic substrate having a thickness of several hundred microns and using a redistribution layer having a thickness of only several tens of microns, thereby significantly reducing the total packaging thickness of the stacked chip wire-bonded packaging structure, avoiding the risk of material shortage due to an imbalance between supply and demand, and significantly reducing the packaging cost. The present invention adopts wafer-form processing to replace substrate-form processing, thereby increasing output and being more suitable for industrial promotion and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of step 1 of the present invention;

[0029] Figure 2 It is a structural schematic diagram of step 2 of the present invention;

[0030] Figure 3 It is a structural schematic diagram of step three of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure of step 4 of embodiment 1 of the present invention;

[0032] Figure 5 This is a schematic diagram of the structure of step 5 of embodiment 1 of the present invention;

[0033] Figure 6 This is a schematic diagram of the structure of step six of embodiment 1 of the present invention;

[0034] Figure 7 This is a schematic diagram of the structure of step seven of embodiment 1 of the present invention;

[0035] Figure 8 This is a schematic diagram of the structure of step eight of embodiment 1 of the present invention;

[0036] Figure 9-10 They are respectively structural schematic diagrams of step nine of embodiment 1 of the present invention;

[0037] Fig.11 This is a structural diagram of step nine of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0039] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0040] like Figure 1-11 As shown, the present invention discloses a method for preparing a stacked chip wire bonding packaging structure, comprising the following steps:

[0041] Step 1: Figure 1 As shown, a temporary bonding film layer 2 is coated on the surface of a glass slide 1. The glass slide 1 is usually a circular slide. The temporary bonding film layer 2 is usually a laser-sensitive material that will decompose after laser irradiation;

[0042] Step 2: Figure 2 As shown, a metal anti-reflection layer 3 is sputtered on the surface of the temporary bonding film layer 2. The metal anti-reflection layer 3 is usually made of metal aluminum or titanium copper, with a thickness of 0.1-3 microns. The function of the metal anti-reflection layer 3 is to block the laser in the subsequent laser debonding process to prevent the laser from damaging the redistribution layer;

[0043] Step 3: Figure 3 As shown, the redistribution layer is prepared by metal sputtering, photolithography and electroplating processes, and the redistribution layer includes multiple passivation layers 4 and multiple metal circuit layers 5 arranged alternately in sequence. The passivation layer 4 is usually a polyimide material that can be photolithographically processed, and the metal circuit layer 5 is usually a copper circuit. A metal pad 51 that is subsequently connected to a solder ball is formed at the bottom of the redistribution layer, and a pad I 52 for subsequent wire bonding is formed at the top of the redistribution layer;

[0044] Step 4: Surface mount the stacked chipset on the redistribution layer;

[0045] Step 5: After the chip stacking and wire bonding process is completed, a plastic packaging material is used to perform wafer-level plastic packaging to form a plastic packaging body 15, and the stacked chip set is completely wrapped by the plastic packaging body 15 to protect the chip;

[0046] Step 6: Using a laser debonding process, the glass carrier 1 is removed to expose the temporary bonding film layer 2;

[0047] Step 7: Use liquid wet cleaning or plasma dry cleaning to remove the temporary bonding adhesive layer 2 to expose the metal anti-reflection layer 3. In this step, the cleaning liquid is usually provided by the temporary bonding adhesive supplier. The main process parameters of liquid cleaning are the flow rate, pressure and time of the liquid, which can be flexibly selected according to actual needs. Plasma dry cleaning does not require the purchase of liquid or cleaning fluid. It only requires plasma cleaning equipment. The key process parameters are power, gas type and operation time. Oxygen is usually selected. The operation time is usually 30-600 seconds. The operating power varies greatly depending on the equipment.

[0048] Step 8: Use wet etching to remove the metal anti-reflection layer 3 to expose the metal pad 51. The key process parameters of wet etching are temperature and time. The temperature is usually room temperature, and the time is determined according to the thickness of the metal anti-reflection layer 3. Usually, over-etching of 50%-100% is required.

[0049] Step 9: Setting a solder ball 16 at the position of the metal pad 51 by a ball planting process or a solder paste printing process. The composition of the solder ball 16 is usually doped with a small amount of tin-copper-silver alloy;

[0050] Step 10: Finally, a single package is obtained through grinding, marking and cutting processes.

[0051] In the present invention, the stacked chipset may adopt one of the following structures:

[0052] The first is that the bottom of the stacked chipset is the first chip 6, and upwards are the second chip 7, the third chip 8, the fourth chip 9, the fifth chip 10, the sixth chip 11, the seventh chip 12, the eighth chip 13, and the eighth chip 14. ... By analogy, there is no limit to the number of chips contained in the stacked chipset, and this is just an example. The number of stacked chipsets can be one group, two groups, or more groups, without limitation. The mounting of two adjacent chips is staggered in sequence, with the aim of ensuring that all chips face up and that the pads II 62 used for wire bonding are fully exposed. Adjacent chips are physically connected through a bonding layer 61 to ensure that the chips are firm and not easily damaged. Electrical interconnection between chips is achieved through wire bonding, and signal conduction between chips and redistribution layers is also achieved through wire bonding. The metal wire 14 used in wire bonding is usually made of aluminum wire, gold wire, copper wire, silver wire, etc.

[0053] The second type is that the bottom of the stacked chipset is the first chip 6, and upwards are the second chip 7, the third chip 8, the fourth chip 9, the fifth chip 10, the sixth chip 11, the seventh chip 12, the eighth chip 13, and the eighth chip 14. The mounting of two adjacent chips is staggered in sequence, so as to realize that all chips face up and the pads II 62 used for wire bonding are fully exposed. The adjacent chips are physically connected through the adhesive layer 61 to ensure that the chips are firm and not easily damaged. The electrical interconnection between chips is achieved by wire bonding, and the signal conduction between the chip and the redistribution layer is also achieved by wire bonding. The metal wire 14 used in wire bonding is usually an aluminum wire;

[0054] The present invention does not specifically limit the stacking method, the number of chips, the wire bonding method, etc. In addition to the above two structures, those skilled in the art can also flexibly change them according to actual needs.

[0055] The present invention also discloses a stacked chip wire bonding packaging structure, comprising a plastic package 15 and a stacked chip group wrapped therein, the stacked chip group is mounted on a redistribution layer, the redistribution layer comprises a plurality of passivation layers 4 and metal circuit layers 5 which are alternately arranged in sequence, a metal pad 51 is arranged at the bottom of the redistribution layer, a solder ball 16 is arranged on the metal pad 51, a solder pad I 52 is arranged at the top of the redistribution layer, all chips of the stacked chip group face up, the mounting of two adjacent chips is staggered in sequence, the solder pad II 62 used for wire bonding is completely exposed, adjacent chips are physically connected through a die bonding layer 61, electrical interconnection between chips and signal conduction between chips and the redistribution layer are achieved through wire bonding, and solder pad I 52 is connected to solder pad II 62 by wire bonding.

[0056] Example 1

[0057] like Figure 1-10 As shown, a method for preparing a stacked chip wire bonding packaging structure comprises the following steps:

[0058] Step 1: Figure 1 As shown, a temporary bonding film layer 2 is coated on the surface of a glass slide 1. The glass slide 1 is usually a circular slide. The temporary bonding film layer 2 is usually a laser-sensitive material that will decompose after laser irradiation;

[0059] Step 2: Figure 2 As shown, a metal anti-reflection layer 3 is sputtered on the surface of the temporary bonding film layer 2. The metal anti-reflection layer 3 is usually metal aluminum with a thickness of 2 microns. The function of the metal anti-reflection layer 3 is to block the laser in the subsequent laser debonding process to prevent the laser from damaging the redistribution layer;

[0060] Step 3: Figure 3 As shown, the redistribution layer is prepared by metal sputtering, photolithography and electroplating processes. The redistribution layer includes four passivation layers 4 and multiple metal circuit layers 5 arranged alternately in sequence. The passivation layer 4 is usually a polyimide material that can be photolithographically processed, and the metal circuit layer 5 is usually a copper circuit. A metal pad 51 that is subsequently connected to a solder ball is formed at the bottom of the redistribution layer, and a pad I 52 for subsequent wire bonding is formed at the top of the redistribution layer;

[0061] Step 4: Figure 4 As shown, a surface mounted stacked chipset is mounted on a redistribution layer;

[0062] Specifically, the bottom of the stacked chipset is the first chip 6, and upwards are the second chip 7, the third chip 8, the fourth chip 9, the fifth chip 10, the sixth chip 11, the seventh chip 12, the eighth chip 13, and the eighth chip 14. The mounting of two adjacent chips is staggered in sequence, so as to realize that all chips face up and the pads II 62 used for wire bonding are fully exposed. The adjacent chips are physically connected through the adhesive layer 61 to ensure that the chips are firm and not easily damaged. Electrical interconnection between chips is achieved through wire bonding, and signal conduction between chips and redistribution layers is also achieved through wire bonding. The metal wire 14 used in wire bonding is usually an aluminum wire;

[0063] Step 5: Figure 5 As shown, after the chip stacking and wire bonding process is completed, a plastic packaging material is used for wafer-level plastic packaging to form a plastic packaging body 15, and the stacked chip group is completely wrapped by the plastic packaging body 15 to protect the chip;

[0064] Step 6: Figure 6 As shown, the glass carrier 1 is removed by laser debonding process to expose the temporary bonding film layer 2;

[0065] Step 7: Figure 7 As shown, plasma dry cleaning is used, usually oxygen is selected, and the operation time is usually 50 seconds to remove the temporary bonding glue layer 2 and expose the metal anti-reflection layer 3;

[0066] Step8: Figure 8 As shown, the metal anti-reflection layer 3 is removed by wet etching to expose the metal pad 51;

[0067] Step9: Figure 9-10 As shown, a solder ball 16 is arranged at the position of the metal pad 51 through a ball planting process, and the composition of the solder ball 16 is usually doped with a small amount of tin-copper-silver alloy;

[0068] Step 10: Finally, a single package is obtained through grinding, marking and cutting processes.

[0069] A stacked chip wire bonding packaging structure comprises a plastic package 15 and a stacked chip group wrapped therein, wherein the stacked chip group is mounted on a redistribution layer, wherein the redistribution layer comprises four passivation layers 4 and metal circuit layers 5 which are alternately arranged in sequence, wherein a metal pad 51 is arranged at the bottom of the redistribution layer, wherein a solder ball 16 is arranged on the metal pad 51, wherein a solder pad I 52 is arranged at the top of the redistribution layer, wherein all chips of the stacked chip group face upward, and the mounting of two adjacent chips is staggered in sequence, wherein a solder pad II 62 for wire bonding is completely exposed, adjacent chips are physically connected via a die bonding layer 61, and electrical interconnection between chips and signal conduction between chips and the redistribution layer are achieved via wire bonding, wherein solder pad I 52 is connected to solder pad II 62 via wire bonding.

[0070] Example 2

[0071] like Figure 1-3 and Fig.11 As shown, a method for preparing a stacked chip wire bonding packaging structure comprises the following steps:

[0072] Step 1: Figure 1 As shown, a temporary bonding film layer 2 is coated on the surface of a glass slide 1. The glass slide 1 is usually a circular slide. The temporary bonding film layer 2 is usually a laser-sensitive material that will decompose after laser irradiation;

[0073] Step 2: Figure 2 As shown, a metal anti-reflection layer 3 is sputtered on the surface of the temporary bonding film layer 2. The metal anti-reflection layer 3 is usually metal aluminum. The function of the metal anti-reflection layer 3 is to block the laser in the subsequent laser debonding process to prevent the laser from damaging the redistribution layer;

[0074] Step 3: Figure 3 As shown, the redistribution layer is prepared by metal sputtering, photolithography and electroplating processes. The redistribution layer includes four passivation layers 4 and multiple metal circuit layers 5 arranged alternately in sequence. The passivation layer 4 is usually a polyimide material that can be photolithographically processed, and the metal circuit layer 5 is usually a copper circuit. A metal pad 51 that is subsequently connected to a solder ball is formed at the bottom of the redistribution layer, and a pad I 52 for subsequent wire bonding is formed at the top of the redistribution layer;

[0075] Step 4: Surface mount the stacked chipset on the redistribution layer;

[0076] Specifically, the stacked chipset includes two groups of vertically stacked branch units, each group of vertically stacked branch units includes a number of chips arranged in sequence from bottom to top, and the number of chips is not limited. The mounting of two adjacent chips is staggered in sequence, with the purpose of realizing that all chips face up and the pads II 62 used for wire bonding are fully exposed. Adjacent chips are physically connected through the adhesive layer 61 to ensure that the chips are firm and not easily damaged. Electrical interconnection between chips is achieved through wire bonding, and signal conduction between chips and redistribution layers is also achieved by wire bonding. The metal wire 14 used in wire bonding is usually a gold wire;

[0077] Step 5: After the chip stacking and wire bonding process is completed, a plastic packaging material is used to perform wafer-level plastic packaging to form a plastic packaging body 15, and the stacked chip set is completely wrapped by the plastic packaging body 15 to protect the chip;

[0078] Step 6: Using a laser debonding process, the glass carrier 1 is removed to expose the temporary bonding film layer 2;

[0079] Step 7: Remove the temporary bonding adhesive layer 2 by using a chemical wet cleaning method or a plasma dry cleaning method to expose the metal anti-reflection layer 3;

[0080] Step 8: Using a wet etching method, remove the metal anti-reflection layer 3 to expose the metal pad 51;

[0081] Step9: Fig.11 As shown, a solder ball 16 is arranged at the position of the metal pad 51 by a ball planting process or a solder paste printing process, and the composition of the solder ball 16 is usually doped with a small amount of tin-copper-silver alloy;

[0082] Step 10: Finally, a single package is obtained through grinding, marking and cutting processes.

[0083] A stacked chip wire bonding packaging structure comprises a plastic package 15 and a stacked chip group wrapped therein, wherein the stacked chip group is mounted on a redistribution layer, wherein the redistribution layer comprises four passivation layers 4 and metal circuit layers 5 which are alternately arranged in sequence, wherein a metal pad 51 is arranged at the bottom of the redistribution layer, wherein a solder ball 16 is arranged on the metal pad 51, wherein a solder pad I 52 is arranged at the top of the redistribution layer, wherein all chips of the stacked chip group face upward, and the mounting of two adjacent chips is staggered in sequence, wherein a solder pad II 62 for wire bonding is completely exposed, adjacent chips are physically connected via a die bonding layer 61, and electrical interconnection between chips and signal conduction between chips and the redistribution layer are achieved via wire bonding, wherein solder pad I 52 is connected to solder pad II 62 via wire bonding.

[0084] The rest is the same as in Example 1.

[0085] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0086] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for preparing a stacked chip wire bonding packaging structure, characterized in that: The following steps are involved: Step 1: Prepare a temporary bonding film layer on the surface of the glass slide; Step 2: preparing a metal anti-reflection layer on the surface of the temporary bonding film layer; Step 3: Prepare a redistribution layer on the metal anti-reflection layer; Step 4: Surface mount the stacked chipset on the redistribution layer; Step 5: Use plastic packaging material to perform wafer-level plastic packaging to wrap the entire stacked chipset; Step 6: Remove the glass slide to expose the temporary bonding film layer; Step 7: Remove the temporary bonding layer to expose the metal anti-reflection layer; Step 8: Remove the metal anti-reflection layer to expose the metal pads on the redistribution layer; Step 9: Set solder balls on metal pads; Step 10: Get the final package by grinding and cutting.

2. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 2, the metal anti-reflection layer is made of metal aluminum or titanium copper, and has a thickness of 0.1-3 microns.

3. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 3, the redistribution layer includes multiple layers of passivation layers and metal circuit layers that are alternately arranged in sequence. The bottom of the redistribution layer forms a metal pad for connecting to the solder ball, and the top of the redistribution layer forms a pad I for subsequent wire bonding.

4. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 4, the stacked chipset includes a plurality of chips arranged in sequence from bottom to top, with all the chips facing up, and the mounting of two adjacent chips is staggered in sequence, so that the pad II for wire bonding is fully exposed, and the chips and the redistribution layer are electrically interconnected.

5. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 4, the stacked chip group includes several groups of vertically stacked branch units, each group of vertically stacked branch units includes several chips arranged in sequence from bottom to top, all chips are facing upward, the mounting of two adjacent chips is staggered in sequence, the pad II used for wire bonding is completely exposed, and the chips and the redistribution layer are electrically interconnected.

6. The method for preparing a stacked chip wire bonding packaging structure according to claim 4 or 5, characterized in that: Adjacent chips are physically connected through the die bonding layer, and the electrical interconnection between chips and the signal conduction between the chip and the redistribution layer are achieved through wire bonding.

7. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 6, the glass carrier is removed using a laser debonding process to expose the temporary bonding film layer.

8. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 7, the temporary bonding layer is removed by using a solution wet cleaning method or a plasma dry cleaning method to expose the metal anti-reflection layer.

9. The method for preparing a stacked chip wire bonding packaging structure according to claim 1, characterized in that: In Step 8, the metal anti-reflective layer is removed by wet etching to expose the metal pad.

10. A stacked chip wire bonding packaging structure, characterized in that: It comprises a plastic package and a stacked chipset wrapped therein, wherein the stacked chipset is mounted on a redistribution layer, wherein the redistribution layer comprises a plurality of passivation layers and metal circuit layers which are alternately arranged in sequence, wherein a metal pad is arranged at the bottom of the redistribution layer, wherein a solder ball is arranged on the metal pad, and a solder pad I is arranged at the top of the redistribution layer, wherein all chips of the stacked chipset face upward, and the mounting of two adjacent chips is staggered in sequence, so that the solder pad II used for wire bonding is completely exposed, and adjacent chips are physically connected through a die bonding layer, and electrical interconnection between chips and signal conduction between chips and the redistribution layer are realized through wire bonding.

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