Semiconductor structure with micro-channel and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure with a micro-channel and a manufacturing method thereof. The structure includes: a semiconductor substrate in which a first slot and a second slot are arranged; the barrier layer is located on the first surface of the semiconductor substrate and fills the first groove, and the barrier layer at least partially covers the top surface of the second groove and is provided with a top opening; the sealing layer at least partially covers the top opening; the chip module is arranged on the sealing layer; the micro-channel inlet and the micro-channel outlet are located at the two ends of the top opening respectively, and the micro-channel inlet and the micro-channel outlet are communicated with the micro-channel body to form a micro-channel. According to the semiconductor structure with the micro-channel provided by the invention, the silicon oxide isolation strip is constructed on the side edge of the micro-channel body in advance, so that the boundary and the structure of the micro-channel body are controllable; and the chip module is pasted on the sealing layer of the notch, so that accurate and efficient heat dissipation of a specific position of the chip module can be realized.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a semiconductor structure with a microchannel and a manufacturing method thereof. Background Art

[0002] Applications such as artificial intelligence and high-performance computing have increasing demands for bandwidth, storage, high-power heat dissipation, large power supplies, and capacitor decoupling. Currently, 2.5D packaging based on adapters is often used to integrate high-performance chips and HBM (High Bandwidth Memory). However, as the number of integrated HBMs increases and chip performance gradually improves, the integration of high-performance chips and HBM will be limited by the area of ​​the adapter, D2D (Die to Die) high-speed interconnection, power supply, and heat dissipation capacity. Among them, high-performance chips often use DRAM stacked directly on top of high-power AS ICs, so the demand for bottom heat dissipation increases, and conventional heat dissipation covers, heat sinks, and air cooling methods are difficult to meet the high heat dissipation capacity and heat dissipation efficiency requirements of high-performance chips.

[0003] The microchannel structure has a good heat dissipation effect. The microchannel structure is suitable for passing the coolant, which absorbs the heat generated by the chip and transmits it to the outside, thereby achieving the purpose of heat dissipation of the device.

[0004] The existing back-side microchannel process has low heat dissipation efficiency for the chip attached to the first surface. The existing first-surface microchannel is sealed by a patch method, which has poor sealing and is prone to leakage, making it difficult to achieve heat dissipation at a precise fixed position.

[0005] In the preparation process of microfluidic channels, the single dry grooving process is difficult to seal due to the large groove opening; while the wet grooving process can achieve a small groove opening, but the width and boundary of the groove cannot be determined; this seriously restricts the development of the first surface microfluidic channel process. Summary of the invention

[0006] In view of some or all of the problems in the prior art, the present invention provides a semiconductor structure with a microchannel, the structure comprising:

[0007] A semiconductor substrate, in which a first groove and a second groove are arranged, the first groove surrounds the second groove, and the second groove includes a microfluidic channel body;

[0008] A barrier layer, the barrier layer is located on the first surface of the semiconductor substrate, the barrier layer fills the first groove, the barrier layer at least partially covers the top surface of the second groove and leaves a top opening, and the width of the microfluidic channel body is greater than the width of the top opening;

[0009] a sealing layer, the sealing layer at least partially covering the top opening;

[0010] A chip module, wherein the chip module is arranged on the sealing layer;

[0011] A microfluidic channel inlet and a microfluidic channel outlet are respectively located at two ends of the top opening, and the microfluidic channel inlet and the microfluidic channel outlet are connected with the microfluidic channel body to form a microfluidic channel.

[0012] Furthermore, the semiconductor substrate is a silicon substrate.

[0013] Furthermore, the material of the barrier layer is silicon dioxide, and the thickness of the barrier layer is 2 μm-10 μm.

[0014] Furthermore, the material of the sealing layer includes one or more of copper, nickel or gold.

[0015] Furthermore, the chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0016] Furthermore, the width of the top opening is 7 μm-15 μm; and the width of the microchannel body is 30 μm-150 μm.

[0017] The present invention also provides a method for manufacturing a semiconductor structure having a microchannel, the method comprising the following steps:

[0018] Applying photoresist on the first surface of the semiconductor substrate and exposing it to light;

[0019] Etching the semiconductor substrate to form a first groove;

[0020] Forming a barrier layer on the first surface of the semiconductor substrate;

[0021] Applying photoresist on the first surface of the barrier layer and exposing it to light;

[0022] dry etching the barrier layer and the semiconductor substrate to form a second groove;

[0023] In the second groove, wet-etching the semiconductor substrate to form a micro-channel body between adjacent barrier layers;

[0024] forming a sealing layer on the top opening of the second groove;

[0025] A chip module is arranged on the sealing layer to form a semiconductor structure with a micro-channel.

[0026] Furthermore, the barrier layer is manufactured by using an oxidation process or a plasma enhanced chemical vapor deposition process.

[0027] Further, wet etching the semiconductor substrate includes:

[0028] The etching liquid is sprayed toward the side of the semiconductor substrate having the second groove, and part of the etching liquid enters the semiconductor substrate through the second groove to perform wet etching.

[0029] Furthermore, a sealing layer is formed on the top opening of the second slot by using an electroplating process; and a seed layer is sputtered on the top opening to achieve lateral growth of the sealing layer on the side wall of the top opening.

[0030] The technical solution provided by the present invention has the following beneficial effects:

[0031] 1. The semiconductor structure with microchannels provided by the present invention uses a method of dry etching to form a narrow notch and wet etching to expand the internal cavity, thereby realizing a microchannel structure with a narrow notch and a wide groove body.

[0032] 2. The semiconductor structure with microchannels provided by the present invention constructs a silicon oxide isolation zone in advance on the side of the microchannel body, so that the boundary and structure of the microchannel body can be controlled.

[0033] 3. The semiconductor structure with microchannels provided by the present invention can be sealed by electroplating the sealing layer through the narrow groove design on the top, which has a better sealing effect and is convenient for designing the microchannel inlet and microchannel outlet.

[0034] 4. The semiconductor structure with microchannels provided by the present invention adopts the method of manufacturing the microchannels on the front side of the semiconductor substrate. Compared with gluing, the microchannels are more tightly sealed.

[0035] 5. The semiconductor structure with microchannels provided by the present invention can achieve accurate and efficient heat dissipation at a specific position of the chip module by attaching the chip module to the sealing layer of the notch. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0037] Figure 1 A cross-sectional schematic diagram of a semiconductor structure with a microfluidic channel according to an embodiment of the present invention is shown;

[0038] Figure 2 A schematic top view of a semiconductor structure with a microfluidic channel according to an embodiment of the present invention is shown;

[0039] Figure 3A schematic diagram showing a process of a method for manufacturing a semiconductor structure with a microfluidic channel according to an embodiment of the present invention; and

[0040] Figure 4a-4h A schematic cross-sectional view of a process for forming a semiconductor structure with a micro-channel according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0042] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0043] In this specification, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." only indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0044] In this specification, unless otherwise specified, "first surface" and "second surface" are only used to describe the surfaces of the same component. In addition, "first", "second" and "third" are only used to distinguish and do not include size differences.

[0045] In this specification, unless otherwise specified, the quantifiers "a", "an" do not exclude the presence of a plurality of elements, and the quantifiers "plurality" and "multiple" refer to one or more than one elements.

[0046] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0047] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0048] Figure 1 FIG. 4 is a cross-sectional schematic diagram of a semiconductor structure with a microfluidic channel according to an embodiment of the present invention. Figure 1 As shown, the semiconductor structure with a microfluidic channel includes a semiconductor substrate 101, a barrier layer 104, a sealing layer 108, and a chip module 109. A first groove and a second groove are arranged in the semiconductor substrate 101, the first groove surrounds the second groove, and the second groove includes a microfluidic channel body 107. The barrier layer 104 is located on the first surface of the semiconductor substrate 101, the barrier layer 104 is filled with the first groove, the barrier layer 104 at least partially covers the top surface of the second groove and leaves a top opening, and the width of the microfluidic channel body 107 is greater than the width of the top opening.

[0049] Figure 2 FIG. 1 is a schematic top view of a semiconductor structure with a microfluidic channel according to an embodiment of the present invention. Figure 2 As shown, the sealing layer 108 at least partially covers the top opening, and leaves space at both ends of the top opening. A plurality of chip modules 109 are arranged on the sealing layer 108. The microfluidic inlet 110 and the microfluidic outlet 111 are respectively located at both ends of the top opening, and the microfluidic inlet 110 and the microfluidic outlet 111 are connected with the microfluidic body 107 to form a microfluidic channel. The coolant is suitable for entering the microfluidic body 107 from the microfluidic inlet 110 and flowing out from the microfluidic outlet 111.

[0050] In one embodiment of the present invention, the semiconductor substrate 101 may be a silicon substrate.

[0051] In one embodiment of the present invention, the material of the barrier layer 104 may include silicon dioxide, and the thickness of the barrier layer 104 is 2 μm-10 μm.

[0052] In one embodiment of the present invention, the material of the sealing layer 108 may include one or more of copper, nickel, or gold.

[0053] In one embodiment of the present invention, the chip module 109 may include multiple identical chips, or multiple chips of the same type, or multiple chips of different types. In one embodiment of the present invention, the chip may be a logic chip such as a CPU, DSP, GPU, FPGA, or a storage chip such as a DRAM, Flash, HBM, or other types of chips such as SoC or sensors (such as MEMS sensors, etc.).

[0054] In one embodiment of the present invention, the width of the top opening may be 7 μm-15 μm; the width of the microchannel body 107 may be 30 μm-150 μm.

[0055] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure with a microfluidic channel according to an embodiment of the present invention is shown. Figure 4a-4h The schematic cross-sectional view of the process of forming a semiconductor structure with a microchannel according to an embodiment of the present invention is shown. Figure 3 and Figure 4a-4h A method for manufacturing a semiconductor structure with a microfluidic channel according to the present invention is described.

[0056] First, a photoresist 102 is coated on the first surface of the semiconductor substrate 101 and exposed. Figure 4a In one embodiment of the present invention, the semiconductor substrate 101 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or a gallium arsenide substrate.

[0057] Next, the semiconductor substrate 101 is etched to form a first groove 103. Figure 4b In one embodiment of the present invention, the width of the first groove 103 is 4 μm-20 μm, and the depth of the first groove 103 is 20 μm-100 μm.

[0058] Next, a barrier layer 104 is formed on the first surface of the semiconductor substrate 101, such as Figure 4c In one embodiment of the present invention, the barrier layer 104 is made by oxidation process or plasma enhanced chemical vapor deposition process. In one embodiment of the present invention, the material of the barrier layer 104 may include one or more of silicon dioxide, silicon nitride, gallium nitride, gallium arsenide, or aluminum nitride, and the thickness of the barrier layer 104 is 2 μm-10 μm.

[0059] Next, a photoresist 105 is coated on the first surface of the barrier layer 104 and exposed. Figure 4d shown.

[0060] Next, the barrier layer 104 and the semiconductor substrate 101 are dry-etched to form a second groove 106. Figure 4e In one embodiment of the present invention, the width of the second groove 106 is 7 μm-15 μm, and the depth of the second groove 106 is 15 μm-75 μm.

[0061] Next, the semiconductor substrate 101 is wet-etched in the second groove 106 to form a microchannel body 107 between adjacent barrier layers 104. Figure 4fAs shown. In one embodiment of the present invention, the process of wet etching the semiconductor substrate 101 is: spraying the etching liquid to the side of the semiconductor substrate 101 having the second groove 106, and part of the etching liquid enters the semiconductor substrate 101 through the second groove 106 for wet etching. In one embodiment of the present invention, the etching liquid is an alkali solution, and the alkali solution includes an aqueous solution of tetramethylammonium hydroxide, the mass percentage concentration of tetramethylammonium hydroxide is 5%-10%, and the temperature is 80℃-85℃; the wet etching time is 8000s-15000s.

[0062] Next, a sealing layer 108 is formed on the top opening of the second groove, such as Figure 4g As shown. In one embodiment of the present invention, the material of the sealing layer 108 may include one or more of copper, nickel or gold. In one embodiment of the present invention, the sealing layer is made on the top opening of the second slot by using an electroplating process; the specific process is to sputter a seed layer on the top opening to achieve lateral growth of the sealing layer on the side wall of the top opening. Because the top opening of the second slot is narrow, the electroplating sealing of the sealing layer can be achieved.

[0063] Finally, a chip module 109 is arranged on the sealing layer 108 to form a semiconductor structure with a microchannel, such as Figure 4h As shown. In one embodiment of the present invention, the chip module 109 may include multiple identical chips, or multiple chips of the same type, or multiple chips of different types. In one embodiment of the present invention, the chip may be a logic chip such as a CPU, DSP, GPU, FPGA, etc., or a storage chip such as a DRAM, Flash, HBM, etc., or other types of chips such as SoC or sensors (such as MEMS sensors, etc.).

[0064] The semiconductor structure with microfluidic channels provided by the present invention uses a method of dry etching to form a narrow notch and wet etching to expand the internal cavity, thereby realizing a structure of a microfluidic channel with a narrow notch and a wide notch body; a silicon oxide isolation zone is constructed in advance on the side of the microfluidic channel body to realize controllable boundaries and structures of the microfluidic channel body; an electroplated sealing layer is used for sealing to obtain a sealed front microfluidic channel with a better sealing effect, which is convenient for designing a microfluidic channel inlet and a microfluidic channel outlet; the microfluidic channel is made on the front side of the semiconductor substrate, and the microfluidic channel is more tightly sealed compared to gluing; the chip module is attached to the sealing layer of the notch, so that accurate and efficient heat dissipation of a specific position of the chip module can be achieved.

[0065] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A semiconductor structure having a microfluidic channel, characterized in that: include: A semiconductor substrate, in which a first groove and a second groove are arranged, the first groove surrounds the second groove, and the second groove includes a microfluidic channel body; A barrier layer, the barrier layer is located on the first surface of the semiconductor substrate, the barrier layer fills the first groove, the barrier layer at least partially covers the top surface of the second groove and leaves a top opening, and the width of the microfluidic channel body is greater than the width of the top opening; a sealing layer, the sealing layer at least partially covering the top opening; A chip module, wherein the chip module is arranged on the sealing layer; A microfluidic channel inlet and a microfluidic channel outlet are respectively located at two ends of the top opening, and the microfluidic channel inlet and the microfluidic channel outlet are connected with the microfluidic channel body to form a microfluidic channel.

2. The semiconductor structure with microchannel according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate.

3. The semiconductor structure with microchannel according to claim 1, characterized in that: The material of the barrier layer is silicon dioxide, and the thickness of the barrier layer is 2 μm-10 μm.

4. The semiconductor structure with microchannel according to claim 1, characterized in that: The material of the sealing layer includes one or more of copper, nickel or gold.

5. The semiconductor structure with microchannel according to claim 1, characterized in that: The chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

6. The semiconductor structure with microfluidic channels according to claim 1, characterized in that: The width of the top opening is 7 μm-15 μm; the width of the microchannel body is 30 μm-150 μm.

7. A method for manufacturing a semiconductor structure having a microfluidic channel according to any one of claims 1 to 6, characterized in that: The steps include: Applying photoresist on the first surface of the semiconductor substrate and exposing it to light; Etching the semiconductor substrate to form a first groove; Forming a barrier layer on the first surface of the semiconductor substrate; Applying photoresist on the first surface of the barrier layer and exposing it to light; dry etching the barrier layer and the semiconductor substrate to form a second groove; In the second groove, wet-etching the semiconductor substrate to form a micro-channel body between adjacent barrier layers; forming a sealing layer on the top opening of the second groove; A chip module is arranged on the sealing layer to form a semiconductor structure with a micro-channel.

8. The method for manufacturing a semiconductor structure with a microfluidic channel according to claim 7, characterized in that: The barrier layer is formed by oxidation process or plasma enhanced chemical vapor deposition process.

9. The method for manufacturing a semiconductor structure with a microfluidic channel according to claim 7, characterized in that: Wet etching the semiconductor substrate includes: The etching liquid is sprayed toward the side of the semiconductor substrate having the second groove, and part of the etching liquid enters the semiconductor substrate through the second groove to perform wet etching.

10. The method for manufacturing a semiconductor structure with a microfluidic channel according to claim 7, characterized in that: A sealing layer is formed on the top opening of the second groove by using an electroplating process; and a seed layer is sputtered on the top opening to achieve lateral growth of the sealing layer on the side wall of the top opening.

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