Semiconductor device

Abstract

The invention provides a semiconductor device capable of suppressing formation of a gap in a contact portion of the semiconductor device. A semiconductor device (100) is provided with: a semiconductor substrate in which a plurality of trenches (8) are formed; an interlayer insulating film (4) formed on the semiconductor substrate; a contact hole (50) formed in the interlayer insulating film (4); and an electrode (6) connected to a semiconductor mesa portion (51), which is a portion between the trenches (8) of the semiconductor substrate, through the contact hole (50). The side wall of the contact hole (50) has a step shape having at least one step. The bottom portion of the contact hole (50) is located on the semiconductor mesa portion (51), and the upper end portion of the contact hole (50) is located at a position outside the semiconductor mesa portion (51).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] For example, Patent Document 1 listed below discloses a technique for forming contact holes by self-alignment as a method for reducing the size of a semiconductor device.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2007-207784

[0004] As semiconductor devices become increasingly miniaturized, contact holes are becoming smaller in size, potentially creating voids in contact plugs (hereinafter referred to as "contact portions") within the contact holes. Patent Document 1 fails to consider the formation of contact holes in semiconductor devices with advanced miniaturization, and thus fails to adequately prevent the formation of voids in the contact portions. Summary of the Invention

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of suppressing the formation of voids in contact portions of a semiconductor device.

[0006] The semiconductor device disclosed herein comprises: a semiconductor substrate having a plurality of trenches formed therein; an interlayer insulating film formed on the semiconductor substrate; a contact hole formed in the interlayer insulating film; and an electrode formed on the interlayer insulating film and connected to a portion of the semiconductor substrate between the trenches, i.e., a semiconductor mesa portion, through the contact hole. The sidewall of the contact hole is stepped with at least one step, the bottom of the contact hole is located on the semiconductor mesa portion, and the upper end of the contact hole is located outside the semiconductor mesa portion.

[0007] According to the present disclosure, it is possible to suppress the formation of voids in the contact portion of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a top view of a chip of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a top view of a chip of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a plan view of the IGBT region of the semiconductor device according to the first embodiment.

[0011] Figure 4 This is a cross-sectional view of the IGBT region of the semiconductor device according to the first embodiment.

[0012] Figure 5 This is a cross-sectional view of the IGBT region of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a top view of the diode region of the semiconductor device according to the first embodiment.

[0014] Figure 7 This is a cross-sectional view of the diode region of the semiconductor device according to the first embodiment.

[0015] Figure 8 This is a cross-sectional view of the diode region of the semiconductor device according to the first embodiment.

[0016] Figure 9 This is a cross-sectional view of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment.

[0017] Figure 10 This is a cross-sectional view of a termination region of the semiconductor device according to the first embodiment.

[0018] Figure 11 This is a cross-sectional view of a termination region of the semiconductor device according to the first embodiment.

[0019] Figure 12 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Figure 13 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Figure 14 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Figure 15 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Figure 16 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Figure 17 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0025] Figure 18 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0026] Figure 19 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0027] Figure 20 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0028] Figure 21These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0029] Figure 22 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Figure 23 These are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Figure 24 This is a diagram showing the structure of a contact portion of the semiconductor device according to the first embodiment.

[0032] Figure 25 It is a process diagram showing the step of forming a contact hole.

[0033] Figure 26 1 is a process diagram showing the step of forming a contact hole.

[0034] Figure 27 1 is a process diagram showing the step of forming a contact hole.

[0035] Figure 28 1 is a process diagram showing the step of forming a contact hole.

[0036] Figure 29 It is a diagram showing an example of the shape of a frame-shaped insulating film remaining on the step of the contact hole.

[0037] Figure 30 It is a diagram showing an example of the shape of a frame-shaped insulating film remaining on the step of the contact hole.

[0038] Figure 31 It is a diagram showing an example of the shape of a frame-shaped insulating film remaining on the step of the contact hole.

[0039] Figure 32 This is a diagram showing a modified example of the contact portion of the semiconductor device according to the first embodiment.

[0040] Figure 33 This is a diagram showing the structure of a contact portion of a semiconductor device according to a second embodiment.

[0041] Figure 34 A diagram showing a modified example of the contact portion of the semiconductor device according to the second embodiment.

[0042] Figure 35 A diagram showing a modified example of the contact portion of the semiconductor device according to the second embodiment.

[0043] Figure 36 A diagram showing a modified example of the contact portion of the semiconductor device according to the second embodiment.

[0044] Figure 37It is a diagram showing an example of arrangement of contact portions of a semiconductor device.

[0045] Description of reference numerals: 1...n _ 1...n-type drift layer; 2...n-type carrier storage layer; 3...n-type buffer layer; 4...interlayer insulating film; 5...barrier metal; 6...emitter electrode; 6a...terminal electrode; 7...collector; 8...trench; 9...oxide film; 10...IGBT region; 11...active trench gate; 11a...gate trench electrode; 11b...gate trench insulating film; 12...dummy trench gate; 12a...dummy trench electrode; 12b...dummy trench insulating film; 13...n + Type emitter layer; 14...p + p-type contact layer; 15...p-type base layer; 16...p-type collector layer; 16a...p-type terminal collector layer; 20...diode region; 21...diode trench gate; 21a...diode trench electrode; 21b...diode trench insulating film; 24...p-type + Type contact layer; 25...p-type anode layer; 26...n + type cathode layer; 30...terminal region; 31...p-type terminal well layer; 32...n + 33...semi-insulating film; 34...terminal protection film; 40...pad region; 41...control pad; 41a...current sensing pad; 41b...Kelvin emitter pad; 41c...gate pad; 41d, 41e...temperature sensing diode pads; 50...contact hole; 51...semiconductor mesa portion; 52...insulating film; 53...underlying conductive film; 54...p-type high-concentration layer; 60...gate wiring; 61...emitter contact hole; 62...dummy trench contact hole; 63...active trench contact hole; 100, 101...semiconductor device. DETAILED DESCRIPTION

[0046] In the following description, n and p represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is set to n type and the second conductivity type is set to p type. However, the first conductivity type may be set to p type and the second conductivity type may be set to n type. - Indicates that the impurity concentration is lower than n, n + Indicates that the impurity concentration is higher than n. Similarly, p - Indicates that the impurity concentration is lower than p, p + Indicates that the impurity concentration is higher than that of p.

[0047] The level of impurity concentration in each region is defined by its peak concentration. That is, a region with high (or low) impurity concentration refers to a region with high (or low) impurity peak concentration.

[0048] <Implementation Method 1>

[0049] The following describes the structure of a semiconductor device according to Embodiment 1. The semiconductor device includes a semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT), an SBD (Schottky Barrier Diode), or a PN diode. Here, the semiconductor element is assumed to be an RC-IGBT.

[0050] Semiconductor devices can be made of either silicon (Si) or wide-bandgap semiconductors such as silicon carbide (SiC). Compared to silicon-based semiconductor devices, those made of wide-bandgap semiconductors offer superior operation at high voltages, high currents, and high temperatures. Wide-bandgap semiconductors include not only silicon carbide but also gallium nitride (GaN)-based materials and diamond.

[0051] Figure 1 1 is a top view showing a semiconductor device as an RC-IGBT. Figure 2 It is a plan view showing a semiconductor device of another structure, an RC-IGBT. Figure 1 The semiconductor device 100 shown has a structure in which the IGBT region 10 and the diode region 20 are arranged in a stripe shape, which may also be simply referred to as a “stripe type”. Figure 2 The semiconductor device 101 shown has a structure in which a plurality of diode regions 20 are arranged in the vertical and horizontal directions, and an IGBT region 10 is provided around the diode regions 20 , which may also be simply referred to as an “island type”.

[0052] (1) Striped overall plane structure

[0053] exist Figure 1 In the embodiment, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in stripes in a direction perpendicular to the extending direction of the IGBT region 10 and the diode region 20. Figure 1In the figure, three IGBT regions 10 are shown, two diode regions are shown, and all diode regions 20 are sandwiched by the IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited thereto. The number of IGBT regions 10 may be more than three or less than three, and the number of diode regions 20 may be more than two or less than two. Figure 1 The locations of the IGBT regions 10 and the diode regions 20 may be interchanged, or all the IGBT regions 10 may be sandwiched between the diode regions 20. Alternatively, the IGBT regions 10 and the diode regions 20 may be provided adjacent to each other one by one.

[0054] like Figure 1 As shown, a pad area 40 is provided adjacent to the lower side of the paper of the IGBT area 10. The pad area 40 is an area where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT area 10 and the diode area 20 are collectively referred to as a unit area. A terminal area 30 is provided around the area where the unit area and the pad area 40 are combined in order to maintain the withstand voltage of the semiconductor device 100. The terminal area 30 can be appropriately selected to provide a known withstand voltage maintenance structure. For example, the withstand voltage maintenance structure can also be provided on the surface side of the semiconductor device 100, that is, the first main surface side, by providing an FLR (Field Limiting Ring) that surrounds the area where the unit area and the pad area 40 are combined by a p-type terminal well layer of a p-type semiconductor, or a VLD (Variation of The number of annular p-type termination well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Furthermore, the p-type termination well layer can be provided over substantially the entire pad region 40, and an IGBT cell or a diode cell can be provided in the pad region 40.

[0055] The control pad 41 may be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sensing diode pads 41d and 41e. The current sensing pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 100. When current flows through the cell region of the semiconductor device 100, the control pad is electrically connected to the IGBT cells or diode cells in a portion of the cell region so that a current of a fraction to tens of thousands of the current flowing through the entire cell region flows.

[0056] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via the p-type base layer. + The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in semiconductor device 100. The temperature of semiconductor device 100 is measured by measuring the voltage between the anode and cathode of a temperature sensing diode (not shown) provided in the cell region.

[0057] (2) Island-type overall plane structure

[0058] Figure 2 In FIG. 1 , semiconductor device 101 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. Multiple diode regions 20 are arranged vertically and horizontally within the semiconductor device, and are surrounded by the IGBT region 10. In other words, multiple diode regions 20 are arranged in an island shape within the IGBT region 10. Figure 2 In the figure, the diode region 20 is shown as a structure arranged in a matrix with 4 columns in the left-right direction of the paper and 2 rows in the upper limit direction of the paper, but the number and configuration of the diode regions 20 are not limited to this. It can be a structure in which one or more diode regions 20 are dispersed in the IGBT region 10 and each diode region 20 is surrounded by the IGBT region 10.

[0059] like Figure 2As shown, a pad region 40 is provided adjacent to the lower side of the IGBT region 10 in the drawing. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 101 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as the cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the withstand voltage of the semiconductor device 101. A known withstand voltage maintenance structure can be appropriately selected for the termination region 30. For example, the withstand voltage maintenance structure can be formed by providing an FLR (Field Limiting Ring) on ​​the first principal surface, which is the surface side of the semiconductor device 101, where a p-type termination well layer of a p-type semiconductor surrounds the combined region of the cell region and the pad region 40, or a VLD (Variation of Lateral Doping) on ​​the first principal surface, which is the surface side of the semiconductor device 101, where a p-type termination well layer having a concentration gradient surrounds the combined region of the cell region and the pad region 40. The number of ring-shaped p-type termination well layers used in the FLR and the concentration profile used in the VLD can be appropriately selected based on the withstand voltage design of the semiconductor device 101. Alternatively, a p-type termination well layer may be provided over substantially the entire pad region 40 , or an IGBT cell or a diode cell may be provided in the pad region 40 .

[0060] The control pad 41 may be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sensing diode pads 41d and 41e. The current sensing pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 101. When current flows through the cell region of the semiconductor device 101, the control pad is electrically connected to the IGBT cells or diode cells in a portion of the cell region so that a current of a fraction to tens of thousands of the current flowing through the entire cell region flows.

[0061] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off control of the semiconductor device 101 is applied. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via the p-type base layer. + The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0062] (3) Example of the structure of the IGBT region 10

[0063] Figure 3 This is a partially enlarged top view showing the structure of the IGBT region of a semiconductor device as an RC-IGBT. Figure 4 as well as Figure 5 It is a cross-sectional view showing the structure of an IGBT region of a semiconductor device as an RC-IGBT. Figure 3 It will Figure 1 The semiconductor device 100 or Figure 2 FIG. 8 is an enlarged view of a region surrounded by a dotted line 82 in the semiconductor device 101 . Figure 4 yes Figure 3 The cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dotted line AA is shown. Figure 5 yes Figure 3 The semiconductor device 100 or the semiconductor device 101 is shown as a cross-sectional view taken along the dashed line BB.

[0064] like Figure 3 As shown, active trench gates 11 and dummy trench gates 12 are provided in a stripe pattern in the IGBT region 10. In the semiconductor device 100, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 serves as the longitudinal direction of the active trench gates 11 and dummy trench gates 12. Meanwhile, in the semiconductor device 101, although the longitudinal direction and the transverse direction are not specifically distinguished in the IGBT region 10, the longitudinal direction of the active trench gates 11 and dummy trench gates 12 may be defined as the horizontal direction on the paper, or the vertical direction on the paper may be defined as the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0065] The active trench gate 11 is configured such that a gate trench electrode 11a is provided within a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided within a trench formed in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0066] n + The type emitter layer 13 is provided on both sides of the active trench gate 11 in the width direction in contact with the gate trench insulating film 11b. + The emitter layer 13 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm3 ~1.0E+20 / cm 3 .n + The type emitter layer 13 is connected to the p-type emitter layer 13 along the extending direction of the active trench gate 11. + Type contact layers 14 are arranged alternately. + The p-type contact layer 14 is also provided between two adjacent dummy trench gates 12. + The contact layer 14 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0067] like Figure 3 As shown, in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101, three dummy trench gates 12 are arranged next to three active trench gates 11, and three active trench gates 11 are arranged next to three dummy trench gates 12. The IGBT region 10 has a structure in which groups of active trench gates 11 and groups of dummy trench gates 12 are alternately arranged in this manner. Figure 3 In the embodiment, the number of active trench gates 11 included in one group of active trench gates 11 is set to 3, but may be 1 or more. Furthermore, the number of dummy trench gates 12 included in one group of dummy trench gates 12 may be 1 or more, or may be 0. In other words, all trenches provided in the IGBT region 10 may be active trench gates 11.

[0068] Figure 4 The semiconductor device 100 or the semiconductor device 101 Figure 3 The cross-sectional view taken along the dotted line AA in FIG. 1 is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 has an n-type semiconductor substrate. - Type drift layer 1. n - The drift layer 1 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 .exist Figure 4 In the semiconductor substrate, the + type emitter layer 13 and p + The range from the p-type contact layer 14 to the p-type collector layer 16. Figure 4 In the + type emitter layer 13 and p +The upper end of the p-type contact layer 14 on the paper is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. The semiconductor device 100 has n in the IGBT region 10 as the cell region and between the first main surface and the second main surface opposite to the first main surface. - Type drift layer 1.

[0069] like Figure 4 As shown, in the IGBT region 10, at n - The first main surface side of the n-type drift layer 1 is provided with an n-type impurity concentration ratio n - The n-type carrier storage layer 2 has a high n-type drift layer 1. The n-type carrier storage layer 2 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In addition, the semiconductor device 100 or the semiconductor device 101 may be configured such that the n-type carrier storage layer 2 is not provided. Figure 4 The region of the n-type carrier storage layer 2 shown is also provided with n - By providing the n-type carrier storage layer 2, the conduction loss when the current flows in the IGBT region 10 can be reduced. - The drift layer 1 is collectively referred to as the drift layer.

[0070] The n-type carrier storage layer 2 is formed by - The semiconductor substrate of the drift layer 1 is ion-implanted with n-type impurities and then the n-type impurities implanted by annealing are formed as n-type impurities. - The type drift layer 1 is formed by diffusion in the semiconductor substrate.

[0071] A p-type base layer 15 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, an n-type base layer is provided in contact with the gate trench insulating film 11b of the active trench gate 11. + Type emitter layer 13, and p + Type contact layer 14. + type emitter layer 13 and p +The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. + In the case of the p-type contact layer 14 and the p-type base layer 15, they can also be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as a p-type base layer.

[0072] In addition, the semiconductor device 100 or the semiconductor device 101 is - The second main surface side of the n-type drift layer 1 is provided with an n-type impurity concentration ratio n - The n-type buffer layer 3 is formed to suppress the breakdown of the depletion layer extending from the p-type base layer 15 to the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be implanted with phosphorus (P) or protons (H + ) can also be formed by injecting phosphorus (P) and protons (H + The concentration of n-type impurities in the n-type buffer layer 3 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0073] Alternatively, the semiconductor device 100 or the semiconductor device 101 may be configured such that the n-type buffer layer 3 is not provided. Figure 4 The region of the n-type buffer layer 3 shown is also provided with n - n-type drift layer 1. n-type buffer layer 3 and n-type - The drift layer 1 is collectively referred to as the drift layer.

[0074] The semiconductor device 100 or the semiconductor device 101 includes a p-type collector layer 16 provided on the second main surface side of the n-type buffer layer 3. - A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 P-type collector layer 16 forms the second main surface of the semiconductor substrate. P-type collector layer 16 is provided not only in IGBT region 10 but also in termination region 30. The portion of p-type collector layer 16 provided in termination region 30 constitutes p-type termination collector layer 16a. Alternatively, a portion of p-type collector layer 16 may extend from IGBT region 10 toward diode region 20.

[0075] like Figure 4As shown, the semiconductor device 100 or the semiconductor device 101 has a structure that penetrates the p-type base layer 15 from the first main surface of the semiconductor substrate and reaches the n-type base layer 15. - The active trench gate 11 is formed by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. - The dummy trench electrode 12a is provided in the trench via the dummy trench insulating film 12b, thereby forming the dummy trench gate 12. The dummy trench electrode 12a is separated from the n-type drift layer 1 via the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type emitter layer 13. When a gate driving voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0076] like Figure 4 As shown, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the area of ​​the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed with titanium and silicon (Si). Figure 4 As shown, the barrier metal 5 and n + Type emitter layer 13, p + The contact layer 14 and the dummy trench electrode 12a are in ohmic contact with the n + Type emitter layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or can be an electrode composed of a multilayer metal film formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The plating formed by chemical plating or electroplating can also be, for example, a nickel (Ni) plating. In addition, when there are tiny areas such as between adjacent interlayer insulating films 4 and areas where good embedding cannot be achieved in the emitter electrode 6, tungsten with better embedding properties than the emitter electrode 6 can be arranged in a tiny area and the emitter electrode 6 can be provided on the tungsten. In addition, instead of providing the barrier metal 5, an n + Type emitter layer 13, p + The emitter electrode 6 is provided on the n-type contact layer 14 and the dummy trench electrode 12a. +A barrier metal 5 is provided on an n-type semiconductor layer such as an n-type emitter layer 13. The barrier metal 5 and the emitter electrode 6 may also be collectively referred to as an emitter electrode. Figure 4 , the diagram shows that the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in other cross sections.

[0077] The interlayer insulating film 4 will be described in detail in “(8) Cross-sectional shape of contact portion” to be described later.

[0078] Collector electrode 7 is provided on the second principal surface of p-type collector layer 16. Like emitter electrode 6, collector electrode 7 can also be composed of an aluminum alloy, or an aluminum alloy and a plated film. Furthermore, collector electrode 7 can have a different structure from emitter electrode 6. Collector electrode 7 is in ohmic contact with p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0079] Figure 5 The semiconductor device 100 or the semiconductor device 101 Figure 3 The cross-sectional view at the dotted line BB in FIG is a cross-sectional view of the IGBT region 10. Figure 4 The difference of the cross-sectional view at the dotted line AA is that Figure 5 The n-type transistor provided on the first main surface side of the semiconductor substrate and in contact with the active trench gate 11 is not visible in the cross section taken along the dotted line BB. + type emitter layer 13. In other words, Figure 3 As shown, n + The p-type emitter layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 is collectively referred to as a p-type base layer.

[0080] (4) Example of the structure of the diode region 20

[0081] Figure 6 This is a partially enlarged top view showing the structure of the diode region of a semiconductor device as an RC-IGBT. Figure 7 as well as Figure 8 It is a cross-sectional view showing the structure of a diode region of a semiconductor device as an RC-IGBT. Figure 6 It will Figure 1 The diagram shows an enlarged view of a region surrounded by a dotted line 83 in the semiconductor device 100 or the semiconductor device 101 . Figure 7 yes Figure 6 A cross-sectional view of the semiconductor device 100 is shown along a dotted line CC. Figure 8 yes Figure 6 FIG. 1 is a cross-sectional view of the semiconductor device 100 taken along the dashed line DD.

[0082] The diode trench gate 21 extends from one end side of the diode region 20 serving as the unit region toward the other end side thereof along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is formed by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type semiconductor device 100 via the diode trench insulating film 21b. - A p-type drift layer 1 is provided between two adjacent diode trench gates 21. + Type contact layer 24 and p-type anode layer 25. + The contact layer 24 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 .p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0083] Figure 7 The semiconductor device 100 or the semiconductor device 101 Figure 6 The cross-sectional view taken along the dotted line CC in FIG. 1 is a cross-sectional view of the diode region 20. The semiconductor device 100 or the semiconductor device 101 also has an n-type semiconductor substrate in the diode region 20 similarly to the IGBT region 10. - Type drift layer 1. The n-type diode region 20 - n type drift layer 1 and IGBT region 10 - The type drift layer 1 is continuously and integrally formed and is formed by the same semiconductor substrate. Figure 7 In the semiconductor substrate, the + Type contact layer 24 to n + The range up to the cathode layer 26. Figure 7 In the + The upper end of the paper surface of the type contact layer 24 is called the first main surface of the semiconductor substrate. +The lower edge of cathode layer 26 is referred to as the second principal surface of the semiconductor substrate. The first principal surface of diode region 20 is flush with the first principal surface of IGBT region 10 , and the second principal surface of diode region 20 is flush with the second principal surface of IGBT region 10 .

[0084] like Figure 7 As shown, in the diode region 20, similar to the IGBT region 10, - An n-type carrier storage layer 2 is provided on the first main surface side of the n-type drift layer 1. - An n-type buffer layer 3 is provided on the second main surface side of the type drift layer 1. The n-type carrier storage layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier storage layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessary to provide the n-type carrier storage layer 2 in the IGBT region 10 and the diode region 20. Even if the n-type carrier storage layer 2 is provided in the IGBT region 10, the n-type carrier storage layer 2 may not be provided in the diode region 20. In addition, the n-type carrier storage layer 2 and the n-type buffer layer 3 provided in the diode region 20 may be provided in the same manner as the IGBT region 10. - The n-type drift layer 1 , the n-type carrier accumulation layer 2 , and the n-type buffer layer 3 are collectively referred to as a drift layer.

[0085] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is provided on the n-type carrier storage layer 2. - The p-type drift layer 1 is formed between the p-type anode layer 25 and the first main surface. Alternatively, the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously so that the p-type impurity concentration is the same as that of the p-type base layer 15 in the IGBT region 10. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be lower than that of the p-type base layer 15 in the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery losses during diode operation.

[0086] On the first main surface side of the p-type anode layer 25, a p + Type contact layer 24. p + The concentration of the p-type impurity in the p-type contact layer 24 is proportional to the concentration of the p-type impurity in the IGBT region 10. + The p-type impurities in the p-type contact layer 14 may have the same concentration or different concentrations. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25. + In the case of the p-type contact layer 24 and the p-type anode layer 25, they can also be referred to individually, or the p+ The p-type contact layer 24 and the p-type anode layer 25 are collectively referred to as a p-type anode layer.

[0087] The diode region 20 is provided on the second main surface side of the n-type buffer layer 3. + Type cathode layer 26. n + The cathode layer 26 is provided on the n - Between the drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 .like Figure 2 As shown, n + The cathode layer 26 is provided on a part or the whole of the diode region 20. + The type cathode layer 26 constitutes the second main surface of the semiconductor substrate. In addition, although not shown in the figure, it is also possible to form an n-type cathode layer 26 as described above. + The region of the cathode layer 26 is further selectively injected with p-type impurities to form an n-type cathode layer. + A p-type cathode layer is provided as a p-type semiconductor in a part of the region of the p-type cathode layer 26 .

[0088] like Figure 7 As shown, in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, a p-type anode layer 25 is formed from the first main surface of the semiconductor substrate to reach the n-type anode layer 25. - The diode trench gate 21 is formed by providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - type drift layer 1 is opposite.

[0089] like Figure 7 As shown, the diode trench electrode 21a and p + A barrier metal 5 is provided on the type contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and the p + The contact layer 24 is in ohmic contact with the diode trench electrode and the p + The barrier metal 5 may also be of the same structure as the barrier metal 5 of the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. Alternatively, as in the case of the IGBT region 10, the barrier metal 5 may not be provided, and the diode trench electrode 21a and the p + The type contact layer 24 is in ohmic contact with the emitter electrode 6. Figure 7 , the diagram shows that the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in other cross sections.

[0090] In n + The collector electrode 7 is provided on the second main surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. + The cathode layer 26 is in ohmic contact with n + The cathode layer 26 is electrically connected to the cathode layer.

[0091] Figure 8 The semiconductor device 100 or the semiconductor device 101 Figure 6 The cross-sectional view at the dotted line DD in FIG is a cross-sectional view of the diode region 20. Figure 7 The difference of the cross-sectional view at the dotted line CC is that no p-type anode layer 25 is provided between the p-type anode layer 25 and the barrier metal 5. + The p-type contact layer 24 and the p-type anode layer 25 constitute the first main surface of the semiconductor substrate. Figure 7 The p shown + The p-type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25 .

[0092] (5) Boundary region between the IGBT region 10 and the diode region 20

[0093] Figure 9 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device which is an RC-IGBT. Figure 9 yes Figure 1 A cross-sectional view of the semiconductor device 100 or the semiconductor device 101 is shown along the dashed line GG.

[0094] like Figure 9 As shown, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is extended from the boundary between the IGBT region 10 and the diode region 20 by a distance U1 toward the diode region 20. In this way, by extending the p-type collector layer 16 toward the diode region 20, the n-type collector layer 16 of the diode region 20 can be increased. +The distance between the cathode layer 26 and the active trench gate 11 is increased, and even when a gate driving voltage is applied to the gate trench electrode 11a during the operation of the recirculating diode, the current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n-type cathode layer 26 can be suppressed. + The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101 as an RC-IGBT, the distance U1 may be zero or smaller than 100 μm.

[0095] (6) Example of the structure of the terminal region 30

[0096] Figure 10 as well as Figure 11 It is a cross-sectional view showing the structure of a terminal region of a semiconductor device as an RC-IGBT. Figure 10 yes Figure 1 or Figure 2 , which is a cross-sectional view taken along the dotted line EE in FIG. 1 , and is a cross-sectional view from the IGBT region 10 to the terminal region 30. Figure 11 yes Figure 1 FF is a cross-sectional view taken along the dotted line FF in FIG. 1 , and is a cross-sectional view from the diode region 20 to the terminal region 30 .

[0097] like Figure 10 as well as Figure 11 As shown, the termination region 30 of the semiconductor device 100 has n between the first main surface and the second main surface of the semiconductor substrate. - The first main surface and the second main surface of the terminal region 30 are the same as the first main surface and the second main surface of the IGBT region 10 and the diode region 20. - The drift layer 1 is n-type and is connected to the IGBT region 10 and the diode region 20. - The drift layer 1 has the same structure as the type drift layer 1 and is continuously formed as a whole.

[0098] In n - The first main surface side of the n type drift layer 1, that is, the first main surface of the semiconductor substrate and the n type drift layer 1 - A p-type termination well layer 31 is provided between the p-type drift layers 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm 3 ~1.0E+19 / cm 3The p-type terminal well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type terminal well layer 31 is provided in a plurality of rings, and the number of the p-type terminal well layers 31 provided is appropriately selected according to the withstand voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, an n-type terminal well layer 31 is provided on the outer edge side of the p-type terminal well layer 31. + Type channel limiting layer 32, n + The p-type channel limiting layer 32 surrounds the p-type termination well layer 31 .

[0099] In n - A p-type terminal collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is formed continuously and integrally with the p-type collector layer 16 provided in the cell region. Therefore, the layer including the p-type terminal collector layer 16a can also be referred to as the p-type collector layer 16. Figure 1 As in the semiconductor device 100 shown in FIG. 1 , the diode region 20 may also be adjacent to the terminal region 30, as shown in FIG. Figure 11 As shown, the end portion of the p-type terminal collector layer 16a on the diode region 20 side is extended toward the diode region 20 by a distance U2. + The distance between the p-type cathode layer 26 and the p-type termination well layer 31 is increased, and the p-type termination well layer 31 can be prevented from operating as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0100] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. Collector electrode 7 is integrally formed continuously from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30. Meanwhile, an emitter electrode 6 is provided on the first main surface of the semiconductor substrate in the termination region 30, continuing from the cell region and a termination electrode 6a is provided, separated from emitter electrode 6.

[0101] The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 6a is electrically connected to the p-type terminal well layer 31 and the n-type terminal well layer 32. + The channel limiting layer 32 is electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30. Furthermore, a termination protection film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protection film 34 may be formed of, for example, polyimide.

[0102] (7) Example of a method for manufacturing an RC-IGBT

[0103] Figures 12 to 23 It is a diagram showing a method for manufacturing a semiconductor device as an RC-IGBT. Figures 12 to 19 1 is a diagram showing a process for forming the surface side of the semiconductor device 100 or the semiconductor device 101. Figures 20 to 23 1 and 2 are diagrams showing a process of forming the back side of the semiconductor device 100 or the semiconductor device 101 .

[0104] First, if Figure 12 As shown, prepare to form n - The semiconductor substrate may be a so-called FZ wafer produced by the FZ (Floating Zone) method, a so-called MCZ wafer produced by the MCZ (Magnetic Field Applied CZochralski) method, or an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the withstand voltage of the semiconductor device to be produced. For example, for a semiconductor device with a withstand voltage of 1200V, the concentration of n-type impurities constituting the semiconductor substrate may be appropriately selected. - The concentration of the n-type impurity is adjusted so that the resistivity of the n-type drift layer 1 becomes about 40 to 120 Ω·cm. Figure 12 As shown, in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes n - type drift layer 1, but by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them in the semiconductor substrate by heat treatment, a p-type or n-type semiconductor layer is formed to manufacture the semiconductor device 100 or the semiconductor device 101.

[0105] like Figure 12 As shown, it constitutes n - The semiconductor substrate of the p-type drift layer 1 includes regions that serve as the IGBT region 10 and the diode region 20. Furthermore, although not shown, a region that serves as the termination region 30 is provided around the regions that serve as the IGBT region 10 and the diode region 20. The following description focuses on the method for manufacturing the structures of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or 101. However, the termination region 30 of the semiconductor device 100 or 101 can also be fabricated using known manufacturing methods. For example, when the termination region 30 includes an FLR having a p-type termination well layer 31 as a withstand voltage retention structure, the termination region 30 can be formed by implanting p-type impurity ions before fabricating the IGBT region 10 and the diode region 20 of the semiconductor device 100 or 101. Alternatively, the termination region 30 can be formed by implanting p-type impurity ions simultaneously with the implantation of p-type impurities into the IGBT region 10 or the diode region 20 of the semiconductor device 100 or 101.

[0106] Next, if Figure 13 As shown, n-type impurities such as phosphorus (P) are implanted from the first main surface of the semiconductor substrate to form the n-type carrier storage layer 2. Furthermore, p-type impurities such as boron (B) are implanted from the first main surface of the semiconductor substrate to form the p-type base layer 15 and the p-type anode layer 25. The n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions using a heat treatment. Since the n-type and p-type impurities are ion implanted after masking the first main surface of the semiconductor substrate, they are selectively formed on the first main surface of the semiconductor substrate. The n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to the p-type terminal well layer 31 in the terminal region 30. In addition, mask processing refers to a process of forming a mask on a semiconductor substrate in order to apply a resist on the semiconductor substrate, form openings in predetermined areas of the resist using photolithography technology, and perform ion implantation or etching on predetermined areas of the semiconductor substrate through the openings.

[0107] The p-type base layer 15 and the p-type anode layer 25 can also be formed by simultaneously ion-implanting p-type impurities. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, resulting in the same structure. Alternatively, the p-type base layer 15 and the p-type anode layer 25 can be formed by separately ion-implanting p-type impurities using a mask, thereby varying the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25.

[0108] Alternatively, the p-type termination well layer 31 formed in other cross-sections can be formed by ion implanting p-type impurities simultaneously with the p-type anode layer 25. In this case, the p-type termination well layer 31 and the p-type anode layer 25 can have the same depth and p-type impurity concentration, resulting in the same structure. Alternatively, the p-type termination well layer 31 and the p-type anode layer 25 can be formed by ion implanting p-type impurities simultaneously, allowing the p-type impurity concentrations in the p-type termination well layer 31 and the p-type anode layer 25 to differ. In this case, one or both masks can be mesh-shaped, and the aperture ratio can be adjusted.

[0109] Alternatively, the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted with p-type impurities using a mask process to differentiate the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25. Alternatively, the p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed by simultaneously ion-implanting p-type impurities.

[0110] Next, if Figure 14As shown, n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by mask processing to form n-type impurities. + The n-type impurities injected may be, for example, arsenic (As) or phosphorus (P). In addition, by masking, p-type impurities are selectively injected into the first main surface side of the p-type base layer 15 of the IGBT region 10 to form a p-type emitter layer 13. + The p-type contact layer 14 is formed by selectively implanting p-type impurities into the first main surface side of the p-type anode layer 25 of the diode region 20. + type contact layer 24. The implanted p-type impurity may be, for example, boron (B) or aluminum (Al).

[0111] Next, if Figure 15 As shown, a gate electrode is formed from the first main surface side of the semiconductor substrate through the p-type base layer 15 and the p-type anode layer 25 to reach the n-type base layer 15. - The trench 8 of the type drift layer 1. In the IGBT region 10, the n + The sidewalls of the trench 8 of the type emitter layer 13 constitute n + The trench 8 can also be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming an opening in the oxide film at the portion where the trench 8 is to be formed by masking, and etching the semiconductor substrate using the oxide film with the opening as a mask. Figure 15 In the embodiment, the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pitch of the trenches 8 can be appropriately changed according to the mask pattern of the masking process when viewed from above.

[0112] Next, if Figure 16 As shown, the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and on the first main surface of the semiconductor substrate. Of the oxide film 9 formed on the inner wall of the trench 8, the oxide film 9 formed in the trench 8 in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Furthermore, the oxide film 9 formed in the trench 8 in the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later step.

[0113] Next, if Figure 17 As shown, polysilicon doped with n-type or p-type impurities is deposited in the trench 8 having the oxide film 9 formed on the inner wall thereof by CVD (chemical vapor deposition) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0114] Next, if Figure 18 As shown, after forming the interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 can also be, for example, SiO2. Then, a contact hole is formed in the interlayer insulating film 4 deposited by masking. The contact hole is formed at n + On the emitter layer 13, p + Type contact layer 14, p + type contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0115] Next, if Figure 19 As shown, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and on an interlayer insulating film 4 having a single layer or a multilayer structure including an insulating film, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 can also be omitted by forming titanium nitride by PVD (physical vapor deposition) or CVD.

[0116] The emitter electrode 6 can also be formed, for example, by depositing an aluminum-silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be further formed on the formed aluminum-silicon alloy by chemical plating or electroplating to form the emitter electrode 6. If the emitter electrode 6 is formed by plating, a thicker metal film can be easily formed as the emitter electrode 6, so that the heat capacity of the emitter electrode 6 can be increased and the heat resistance can be improved. In addition, after the emitter electrode 6 composed of the aluminum-silicon alloy is formed by PVD, in the case of further forming a nickel alloy by plating, the plating process for forming the nickel alloy can also be carried out after the second main surface side of the semiconductor substrate is processed.

[0117] Next, if Figure 20 As shown, the second main surface of the semiconductor substrate is polished to thin the semiconductor substrate to a predetermined thickness. The thickness of the semiconductor substrate after polishing may be, for example, 80 μm to 200 μm.

[0118] Next, if Figure 21 As shown, n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0119] The n-type buffer layer 3 may be formed by, for example, implanting phosphorus (P) ions. Alternatively, protons (H + ). Alternatively, it can be formed by injecting both protons and phosphorus. Protons can be injected from the second main surface of the semiconductor substrate to a deeper position at a relatively low acceleration energy. Furthermore, the depth of proton injection can be easily changed by varying the acceleration energy. Therefore, when forming the n-type buffer layer 3 using protons, if multiple injections are performed while varying the acceleration energy, an n-type buffer layer 3 having a wider width in the thickness direction of the semiconductor substrate can be formed compared to an n-type buffer layer formed using phosphorus.

[0120] Furthermore, compared to protons, phosphorus can increase the activation rate of n-type impurities. Therefore, even in a semiconductor substrate thinned by forming the n-type buffer layer 3 with phosphorus, depletion layer breakdown can be more reliably suppressed. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. In this case, the protons are implanted deeper than the phosphorus from the second main surface.

[0121] The p-type collector layer 16 can also be formed by implanting boron (B), for example. The p-type collector layer 16 is also formed in the termination region 30 , and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, laser irradiation and laser annealing are performed on the second main surface to activate the implanted boron, forming the p-type collector layer 16. At this time, the phosphorus used to implant the n-type buffer layer 3 from the second main surface of the semiconductor substrate into a relatively shallow position is also activated. On the other hand, protons are activated at relatively low annealing temperatures, such as 350°C to 500°C. Therefore, after proton implantation, care must be taken to prevent the entire semiconductor substrate from reaching temperatures exceeding 350°C to 500°C in all steps other than the proton activation step. Because laser annealing can only raise the temperature near the second main surface of the semiconductor substrate, it can be used to activate both n-type and p-type impurities even after proton implantation.

[0122] Next, if Figure 22 As shown, n is formed in the diode region 20. + Type cathode layer 26. n + The cathode layer 26 can also be formed by injecting phosphorus (P), for example. Figure 22 As shown, the p-type collector layer 16 and the n + Phosphorus is selectively implanted from the second main surface side using a mask process so that the boundary between the n-type cathode layers 26 is located at a position away from the boundary between the IGBT region 10 and the diode region 20 by a distance U1 toward the diode region 20. +The amount of n-type impurities implanted into the cathode layer 26 is greater than the amount of p-type impurities implanted into the p-type collector layer 16 . Figure 22 In FIG. 1 , the p-type collector layer 16 and the n-type collector layer 16 are shown. + The depth of the cathode layer 26 from the second main surface is the same, but n + The depth of the n-type cathode layer 26 may be greater than the depth of the p-type collector layer 16. + The region of the cathode layer 26 needs to be implanted with n-type impurities in the region where p-type impurities are implanted to form an n-type semiconductor. + The concentration of the p-type impurity implanted in the entire region of the cathode layer 26 is higher than the concentration of the n-type impurity.

[0123] Next, if Figure 23 As shown, a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20, and the terminal region 30 of the second main surface. Alternatively, the collector electrode 7 may be formed over the entire second main surface of an n-type wafer serving as the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum-silicon alloy (Ai-Si alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or by stacking multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by forming a further metal film by chemical plating or electroplating on the metal film formed by PVD.

[0124] The semiconductor device 100 or 101 is manufactured through the above-described steps. Since a plurality of semiconductor devices 100 or 101 are manufactured in a matrix on a single n-type wafer, the semiconductor device 100 or 101 is cut into individual semiconductor devices 100 or 101 by laser dicing or blade dicing, thereby completing the semiconductor device 100 or 101.

[0125] (8) Contact structure

[0126] Figure 24 1 is a diagram showing the structure of a contact portion formed in the semiconductor device 100 or the semiconductor device 101. As an example of a contact portion, the following shows a case where the emitter electrode 6 is connected to the n + A contact portion of the emitter layer 13 (emitter contact portion). Figure 24 In FIG, an active trench gate 11 is shown as a trench formed in a semiconductor substrate, but sometimes the trench is a dummy trench gate 12 depending on the position of the contact portion. Figure 24 In the figure, the contact part and n + The example of connecting the type emitter layer 13, but sometimes the contact part is different from the p-type emitter layer 13, + The type contact layer 14 is connected.

[0127] like Figure 24 Thus, contact hole 50, constituting a contact portion, is formed in interlayer insulating film 4 formed between emitter electrode 6 (a conductive film) and the semiconductor substrate. The sidewalls of contact hole 50 are stepped. The bottom of contact hole 50 is located on semiconductor mesa portion 51, which is located between active trench gates 11 of the semiconductor substrate. However, the top end of contact hole 50 (the edge of contact hole 50) is located outside semiconductor mesa portion 51, i.e., on active trench gate 11. Therefore, in a plan view, the bottom of contact hole 50 overlaps with semiconductor mesa portion 51, and the edge of contact hole 50 overlaps with active trench gate 11.

[0128] Since the sidewalls of the contact hole 50 are stepped in this manner, the substantial aspect ratio of the contact hole 50 is relaxed. Therefore, when a contact portion (conductive film of the emitter electrode 6 ) is formed in the contact hole 50 , formation of a void in the contact portion is prevented.

[0129] The ratio (H1 / W1) of the height H1 from the bottom of the contact hole 50 to the lowest step of the sidewall to the width W1 of the bottom of the contact hole 50 is 6 or less, preferably 3 or less, and more preferably 2 or less. In other words, H1 is 6 times or less, preferably 3 times or less, and more preferably 2 times or less of W1. The lower this ratio, the better the embeddedness of the conductive film in the contact hole 50.

[0130] Here, the method of forming the contact hole 50 is described. Figure 25 After the interlayer insulating film 4 is formed on the semiconductor substrate in this manner, the interlayer insulating film 4 in the region where the contact hole 50 is to be formed is selectively etched by the first etching. This first etching is a half etching that removes only the upper portion of the interlayer insulating film 4. Figure 26 In this way, a recess is formed on the upper surface of the interlayer insulating film 4 in the region where the contact hole 50 is to be formed.

[0131] Next, if Figure 27 In this manner, an insulating film 52, such as an oxide film or a nitride film, is formed on the interlayer insulating film 4. The insulating film 52 is also formed in the recess formed in the upper surface of the interlayer insulating film 4 by the first etching. A semi-insulating film or a conductive film may be used instead of the insulating film 52.

[0132] Next, the insulating film 52 and the interlayer insulating film 4 in the region where the contact hole 50 is formed are selectively etched by the second etching. The insulating film 52 in the center of the recess of the interlayer insulating film 4 is thinner than the insulating film 52 in the peripheral portion thereof. Therefore, in the second etching, the interlayer insulating film 4 in the center of the recess is etched by self-alignment. Figure 28 In this way, the center of the depression of the interlayer insulating film 4 reaches the semiconductor substrate, forming a contact hole 50. Thereafter, an emitter electrode 6 is formed on the interlayer insulating film 4, thereby obtaining Figure 24 The contact portion of the structure shown.

[0133] In addition, if Figure 28 As shown, in the process of forming the contact hole 50 by self-alignment, an insulating film 52 remains as a frame-shaped component on the outer peripheral portion of the depression of the interlayer insulating film 4, that is, on the step of the side wall of the contact hole 50. The frame-shaped insulating film 52 can be removed or left as it is. In the case where the frame-shaped insulating film 52 remains, it is preferred that the upper end of the insulating film 52 is lower than the upper surface of the interlayer insulating film 4 or the width of the opening of the frame-shaped insulating film 52 is larger than the width (W1) of the bottom of the contact hole 50, or both. In addition, the cross-sectional shape of the frame-shaped insulating film 52 can also be an arc shape with bulging sides ( Figure 29 ), or a triangular shape with a plane with inclined sides ( Figure 30 ), or a concave shape with concave sides ( Figure 31 When the frame-shaped insulating film 52 remains, the embedding property of the conductive film in the contact hole 50 is improved.

[0134] Furthermore, the edge of the step of the sidewall of the contact hole 50 may be chamfered to form an arc shape during the second etching or by a different etching process. This further improves the embedding property of the conductive film in the contact hole 50 .

[0135] The conductive film constituting the emitter electrode 6 is preferably made of Al or a metal with a lower resistance than Al. As described above, a barrier metal 5 may be formed on the lower surface of the emitter electrode 6. For example, when Cu is used as the material for the conductive film of the emitter electrode 6, diffusion of the conductive film material into the interlayer insulating film 4 or the semiconductor substrate can be prevented.

[0136] In addition, if Figure 32 As shown, the emitter electrode 6 may also have a two-layer structure including a lower conductive film 53. The lower conductive film 53 is preferably formed of Ti, W, Mo, or the like, which has good embedding properties. Alternatively, the lower conductive film 53 may have a plug shape embedded in the contact hole 50. By forming the lower conductive film 53 into a plug shape, stress relaxation can be expected.

[0137] The interlayer insulating film 4 may also have a multilayer structure in which two or more conductive films are stacked. For example, if the etching selectivity is different for each layer of the multilayer structure, the shape of the contact hole 50 can be controlled.

[0138] The sidewall of the contact hole 50 may also have two or more steps. If the number of steps is increased, the embedding property of the conductive film relative to the contact hole 50 is improved. The contact hole 50 having two or more steps can be repeatedly used. Figures 26 to 28 It is formed by the described process.

[0139] <Implementation Method 2>

[0140] In the second embodiment, another structure of a contact portion formed in the semiconductor device 100 or the semiconductor device 101 is described.

[0141] Figure 33 This figure shows the structure of a contact portion in Embodiment 2. As in Embodiment 1, a contact hole 50 constituting the contact portion is formed in an interlayer insulating film 4 formed between an emitter electrode 6 (a conductive film) and a semiconductor substrate. The sidewalls of the contact hole 50 are stepped.

[0142] In the second embodiment, the contact hole 50 extends into the portion of the semiconductor substrate between the active trench gates 11, that is, into the semiconductor mesa portion 51 (inside the p-type base layer 15). Therefore, the bottom of the contact hole 50 is located lower than the upper surface of the semiconductor substrate (i.e., the first main surface). Figure 33 In the example, the contact hole 50 passes through n + type emitter layer 13 and reaches n + The p-type base layer 15 is formed below the p-type emitter layer 13. This improves the hole attraction efficiency and the latch-up resistance.

[0143] The upper end portion (edge ​​of the opening) of the contact hole 50 is located outside the semiconductor mesa portion 51, that is, on the active trench gate 11. Therefore, in a plan view, the bottom portion of the contact hole 50 overlaps with the semiconductor mesa portion 51, and the edge of the contact hole 50 overlaps with the active trench gate 11.

[0144] The ratio (H2 / W2) of the height H2 from the bottom of the contact hole 50 to the lowest step of the sidewall to the width W2 of the bottom of the contact hole 50 is 6 or less, preferably 3 or less, and more preferably 2 or less. In other words, H2 is 6 times or less, preferably 3 times or less, and more preferably 2 times or less of W2.

[0145] The contact hole 50 of the second embodiment can also be formed by using Figures 25 to 28 However, the second etching needs to be performed until the contact hole 50 enters the interior of the semiconductor substrate.

[0146] The frame-shaped insulating film 52 formed in the process of forming the contact hole 50 by self-alignment may be removed or left as it is. In the case where the frame-shaped insulating film 52 remains, it is preferred that the upper end of the insulating film 52 is lower than the upper surface of the interlayer insulating film 4 or the width of the opening of the frame-shaped insulating film 52 is larger than the width (W2) of the bottom of the contact hole 50, or both. In addition, the cross-sectional shape of the frame-shaped insulating film 52 may be an arc shape with a bulging side surface ( Figure 29 ), or a triangular shape with inclined flat sides ( Figure 30 ), or a concave shape with concave sides ( Figure 31 ).

[0147] The conductive film constituting the emitter electrode 6 is preferably Al or a metal having a lower resistance than Al. As described above, a barrier metal 5 may be formed on the lower surface of the emitter electrode 6. Figure 34 As shown, the emitter electrode 6 may have a two-layer structure including a lower conductive film 53. The lower conductive film 53 is preferably formed of Ti, W, Mo, etc. Alternatively, the lower conductive film 53 may be in the shape of a plug embedded in the contact hole 50.

[0148] The interlayer insulating film 4 may also be a multilayer structure in which two or more conductive films are stacked. The sidewall of the contact hole 50 may also have two or more steps. The contact hole 50 having two or more steps can be repeatedly used. Figures 26 to 28 It is formed by the described process.

[0149] like Figure 35 As shown, a p-type high concentration layer 54 that is in contact with the bottom of the contact hole 50 and has a high local impurity concentration may be formed in the p-type base layer 15 of the semiconductor mesa portion 51. By providing the p-type high concentration layer 54, the hole attraction efficiency is further improved. Figure 36 As shown, the p-type high-concentration layer 54 may be formed so as to surround the contact hole 50 .

[0150] Figure 37 The figure shows an example of the arrangement of the contact portion in the semiconductor device 100 or the semiconductor device 101. As a contact hole formed in the interlayer insulating film 4 of the semiconductor device 100 or the semiconductor device 101, in addition to the existence of n + In addition to the emitter contact hole 61 connecting to the emitter layer 13, there are also dummy trench contact holes 62 connecting the emitter electrode 6 and the dummy trench electrode 12a, and active trench contact holes 63 connecting the gate wiring 60 and the gate trench electrode 11a of the active trench gate 11.

[0151] like Figure 37 As shown, the emitter contact hole 61 is formed in the n-type region below the emitter electrode 6. + On the emitter layer 13, the dummy trench contact hole 62 is formed on the dummy trench gate 12 below the emitter electrode 6, and the active trench contact hole 63 is formed on the active trench gate 11 below the gate wiring 60. When the contact hole 50 of the first or second embodiment is applied to the emitter contact hole 61, the upper end of the emitter contact hole 61 extends from the semiconductor mesa portion 51 and is located on the active trench gate 11 or the dummy trench gate 12. Therefore, in this case, Figure 37In this manner, the position of the emitter contact hole 61 and the position of the dummy trench contact hole 62 are arranged so as not to overlap in the direction perpendicular to the extending direction of the active trench gate 11 .

[0152] In addition, the various embodiments can be freely combined, or the various embodiments can be appropriately modified or omitted.

[0153] <Note>

[0154] Hereinafter, each aspect of the present disclosure will be collectively described as a supplementary note.

[0155] (Note 1)

[0156] A semiconductor device comprises: a semiconductor substrate having a plurality of trenches formed therein; an interlayer insulating film formed on the semiconductor substrate; a contact hole formed in the interlayer insulating film; and an electrode formed on the interlayer insulating film and connected to a portion of the semiconductor substrate between the trenches, i.e., a semiconductor mesa portion, through the contact hole, wherein the sidewall of the contact hole is stepped with at least one step, the bottom of the contact hole is located on the semiconductor mesa portion, and the upper end of the contact hole is located outside the semiconductor mesa portion.

[0157] (Note 2)

[0158] In the semiconductor device according to Supplementary Note 1, the bottom portion of the contact hole enters the semiconductor mesa portion.

[0159] (Note 3)

[0160] In the semiconductor device according to Supplementary Note 2, a high-concentration layer having a high impurity concentration is locally formed on the semiconductor mesa portion so as to be in contact with the bottom portion of the contact hole.

[0161] (Note 4)

[0162] In the semiconductor device according to Supplementary Note 3, the high-concentration layer is formed so as to surround the contact hole.

[0163] (Note 5)

[0164] In the semiconductor device according to any one of Supplementary Notes 1 to 4, a height from the bottom of the contact hole to the lowest step of the sidewall is 6 times or less of a width of the bottom of the contact hole.

[0165] (Note 6)

[0166] In the semiconductor device according to any one of Supplementary Notes 1 to 5, the electrode includes Al or a metal having a lower electrical resistance than Al.

[0167] (Note 7)

[0168] In the semiconductor device according to any one of Supplementary Notes 1 to 6, the electrode has a barrier metal on a lower surface.

[0169] (Note 8)

[0170] In the semiconductor device according to any one of Supplementary Notes 1 to 7, the electrode has a multilayer structure including an underlying conductive film, and the underlying conductive film includes any one of Ti, W, and Mo.

[0171] (Note 9)

[0172] In the semiconductor device according to Supplementary Note 8, the lower conductive film has a plug shape embedded in the contact hole.

[0173] (Note 10)

[0174] In the semiconductor device according to any one of Supplementary Notes 1 to 9, the interlayer insulating film has a multilayer structure in which two or more conductive films are stacked.

[0175] (Note 11)

[0176] In the semiconductor device according to any one of Supplementary Notes 1 to 10, the sidewall of the contact hole has a stepped shape having two or more steps.

[0177] (Note 12)

[0178] In the semiconductor device according to any one of Supplementary Notes 1 to 11, a frame-shaped member is formed on the step of the sidewall of the contact hole, and an upper end of the frame-shaped member is lower than an upper surface of the interlayer insulating film.

[0179] (Note 13)

[0180] In the semiconductor device according to any one of Supplementary Notes 1 to 12, a frame-shaped member is formed on the step of the sidewall of the contact hole, and a width of an opening of the frame-shaped member is larger than a width of the bottom of the contact hole.

[0181] (Note 14)

[0182] In the semiconductor device according to Supplementary Note 12 or Supplementary Note 13, the frame-shaped member is an oxide film, a nitride film, a semi-insulating film, or a conductive film.

[0183] (Note 15)

[0184] In the semiconductor device according to any one of Supplementary Notes 12 to 14, the cross-sectional shape of the frame-shaped member is an arc shape having bulging side surfaces, a triangle shape having inclined flat side surfaces, or a concave shape having concave side surfaces.

[0185] (Note 16)

[0186] In the semiconductor device according to any one of Supplementary Notes 1 to 15, an edge of the step of the sidewall of the contact hole is chamfered.

[0187] (Note 17)

[0188] In the semiconductor device described in any one of Notes 1 to 16, there is also a trench contact hole formed in the interlayer insulating film and connected to the trench electrode in the trench, and the position of the contact hole and the position of the trench contact hole do not overlap in a direction orthogonal to the extension direction of the trench.

[0189] (Note 18)

[0190] In the semiconductor device according to any one of Supplementary Notes 1 to 17, the semiconductor substrate is formed of a wide bandgap semiconductor.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having a plurality of grooves formed therein; an interlayer insulating film formed on the semiconductor substrate; a contact hole formed in the interlayer insulating film; as well as an electrode formed on the interlayer insulating film and connected to a semiconductor mesa portion between the trenches of the semiconductor substrate through the contact hole, The sidewall of the contact hole is stepped with at least one step. The bottom of the contact hole is located on the semiconductor mesa portion, and the upper end of the contact hole is located outside the semiconductor mesa portion.

2. The semiconductor device according to claim 1, wherein: The bottom of the contact hole enters into the semiconductor mesa portion.

3. The semiconductor device according to claim 2, wherein: A high-concentration layer having a high impurity concentration is locally formed on the semiconductor mesa portion so as to be in contact with the bottom portion of the contact hole.

4. The semiconductor device according to claim 3, wherein: The high concentration layer is formed to surround the contact hole.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that A height from the bottom of the contact hole to the lowest step of the side wall is 6 times or less of a width of the bottom of the contact hole.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The electrode includes Al or a metal having a lower electrical resistance than Al.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The electrode has a barrier metal on a lower surface.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The electrode has a multilayer structure having a lower conductive film, and the lower conductive film includes any one of Ti, W, and Mo.

9. The semiconductor device according to claim 8, wherein: The lower conductive film is in a plug shape embedded in the contact hole.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The interlayer insulating film has a multilayer structure in which two or more conductive films are stacked.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The sidewall of the contact hole is stepped with two or more steps.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: A frame-shaped component is formed on the step of the side wall of the contact hole, An upper end of the frame-shaped member is lower than an upper surface of the interlayer insulating film.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that: A frame-shaped component is formed on the step of the side wall of the contact hole, The width of the opening of the frame-shaped component is greater than the width of the bottom of the contact hole.

14. The semiconductor device according to claim 12, wherein: The frame-shaped component is an oxide film, a nitride film, a semi-insulating film or a conductive film.

15. The semiconductor device according to claim 13, wherein: The frame-shaped component is an oxide film, a nitride film, a semi-insulating film or a conductive film.

16. The semiconductor device according to claim 12, wherein: The cross-sectional shape of the frame-shaped member is an arc shape having a bulging side surface, a triangular shape having an inclined flat side surface, or a concave shape having a concave side surface.

17. The semiconductor device according to claim 13, wherein: The cross-sectional shape of the frame-shaped member is an arc shape having a bulging side surface, a triangular shape having an inclined flat side surface, or a concave shape having a concave side surface.

18. The semiconductor device according to any one of claims 1 to 17, wherein: An edge of the step of the sidewall of the contact hole is chamfered.

19. The semiconductor device according to any one of claims 1 to 18, characterized in that A trench contact hole is also provided, which is formed in the interlayer insulating film and connected to the trench electrode in the trench. The position of the contact hole and the position of the trench contact hole do not overlap in a direction orthogonal to an extending direction of the trench.

20. The semiconductor device according to any one of claims 1 to 19, wherein: The semiconductor substrate is formed of a wide bandgap semiconductor.

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