Semiconductor structure

Abstract

The invention discloses a semiconductor structure. The semiconductor structure comprises a plurality of element structures which are arranged in a stacked mode. The plurality of element structures includes a plurality of substrates and a plurality of substrate perforations. A plurality of substrate perforations are in the plurality of substrates. The plurality of substrate perforations includes a plurality of first substrate perforations. Each element structure includes a corresponding substrate and a corresponding first substrate via. Each first substrate through hole penetrates through the corresponding substrate. The number of substrate perforations in the last element structure is less than the number of substrate perforations in the other element structure. The first substrate through hole in the last element structure and the first substrate through hole in the other element structure are aligned with each other and electrically connected with each other.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a semiconductor structure comprising a plurality of substrate through holes. Background Art

[0002] Currently, in order to shorten the signal transmission path and reduce the area of ​​the semiconductor structure, a semiconductor structure composed of multiple component structures (such as wafer structures or chip structures) has been developed. However, how to improve the heat dissipation capacity of the semiconductor structure and further shorten the signal transmission path is a goal of continuous efforts. Summary of the invention

[0003] The invention provides a semiconductor structure which has better heat dissipation capability and shorter signal transmission path.

[0004] The present invention provides a semiconductor structure, including a plurality of element structures stacked. The plurality of element structures include a plurality of substrates and a plurality of through-substrate vias (TSVs). The plurality of substrate through-vias are located in the plurality of substrates. The plurality of substrate through-vias include a plurality of first substrate through-vias. Each element structure includes a corresponding substrate and a corresponding first substrate through-via. Each first substrate through-via penetrates the corresponding substrate. The number of substrate through-vias in the last element structure is less than the number of substrate through-vias in another element structure. The first substrate through-via in the last element structure and the first substrate through-via in another element structure are aligned with each other and electrically connected to each other.

[0005] According to an embodiment of the present invention, in the semiconductor structure, the number of substrate through-holes in the last device structure may be less than the number of substrate through-holes in each device structure of the remaining device structures. The first substrate through-hole in the last device structure and the first substrate through-holes in the remaining device structures may be aligned with each other and may be electrically connected to each other.

[0006] According to an embodiment of the present invention, in the semiconductor structure, the plurality of substrate through-holes may further include a plurality of second substrate through-holes. The plurality of second substrate through-holes are located in the plurality of substrates. Each second substrate through-hole may penetrate the corresponding substrate. The plurality of second substrate through-holes in the plurality of element structures may be aligned with each other. The plurality of second substrate through-holes aligned with each other may not be electrically connected to each other.

[0007] According to an embodiment of the present invention, in the semiconductor structure, the plurality of first substrate through-holes may be separated from each other, and the plurality of second substrate through-holes may be separated from each other.

[0008] According to an embodiment of the present invention, in the semiconductor structure, the plurality of second through-substrate vias and the plurality of first through-substrate vias may be separated from each other.

[0009] According to an embodiment of the present invention, in the semiconductor structure, one of the two adjacent device structures may be hybrid bonded to the other of the two adjacent device structures.

[0010] According to an embodiment of the present invention, in the semiconductor structure, the plurality of device structures may further include a plurality of dielectric layers and a plurality of bonding pads. The plurality of dielectric layers are located on the plurality of substrates. The plurality of bonding pads are located in the plurality of dielectric layers.

[0011] According to an embodiment of the present invention, in the semiconductor structure, two adjacent dielectric layers in two adjacent device structures may be bonded to each other.

[0012] According to an embodiment of the present invention, in the semiconductor structure, two adjacent bonding pads in two adjacent device structures may be bonded to each other.

[0013] According to an embodiment of the present invention, in the semiconductor structure, the plurality of bonding pads and the plurality of first substrate through holes may be aligned with each other.

[0014] According to an embodiment of the present invention, in the semiconductor structure, a plurality of bonding pads aligned with each other and a plurality of first substrate through vias may be electrically connected to each other.

[0015] According to an embodiment of the present invention, in the semiconductor structure, the plurality of device structures may further include a plurality of vias. The plurality of vias are located in the plurality of dielectric layers. Each via is located between a corresponding bonding pad and a corresponding first substrate through hole.

[0016] According to an embodiment of the present invention, in the semiconductor structure, the width of the plurality of through holes may be equal to the width of the plurality of first substrate through holes.

[0017] According to an embodiment of the present invention, in the semiconductor structure, the width of the plurality of through holes may be smaller than the width of the plurality of first substrate through holes.

[0018] According to an embodiment of the present invention, in the semiconductor structure, the plurality of bonding pads, the plurality of through holes, and the plurality of first substrate through holes may be aligned with each other.

[0019] According to an embodiment of the present invention, in the semiconductor structure, a plurality of bonding pads, a plurality of through holes, and a plurality of first substrate through holes that are aligned with each other can be electrically connected to each other.

[0020] According to an embodiment of the present invention, in the semiconductor structure, each device structure may be a wafer structure or a chip structure.

[0021] According to an embodiment of the present invention, in the semiconductor structure, the last device structure may be a logic device structure, and the remaining device structures may be memory device structures.

[0022] According to an embodiment of the present invention, in the semiconductor structure, the plurality of device structures may include a first device structure, a second device structure and an internal connection structure. The second device structure is located on the first device structure. The internal connection structure includes a first portion, a second portion and a third portion. The first portion is located in the first device structure. The second portion and the third portion are located in the second device structure and are separated from each other. The second portion and the third portion may be connected to the first portion. The second portion and the third portion may be electrically connected to each other through the first portion.

[0023] According to an embodiment of the present invention, in the semiconductor structure, the interconnect structure may include a redistribution layer (RDL), a second substrate through hole, a conductive line, a via, a bonding pad or a combination thereof.

[0024] Based on the above, in the semiconductor structure proposed by the present invention, each component structure includes a corresponding substrate and a corresponding first substrate through-hole. Each first substrate through-hole passes through the corresponding substrate. The number of substrate through-holes in the last component structure is less than the number of substrate through-holes in another component structure. The first substrate through-hole in the last component structure and the first substrate through-hole in another component structure are aligned with each other and electrically connected to each other. Therefore, a good heat conduction path can be provided by the first substrate through-holes that are aligned with each other and electrically connected to each other, thereby improving the heat dissipation capacity of the semiconductor structure. In addition, a good signal transmission path can be provided and the signal transmission path can be shortened by the first substrate through-holes that are aligned with each other and electrically connected to each other.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 are cross-sectional views of semiconductor structures according to some embodiments of the present invention;

[0027] Figure 2 are cross-sectional views of semiconductor structures according to other embodiments of the present invention;

[0028] Figure 3 are cross-sectional views of semiconductor structures according to other embodiments of the present invention;

[0029] Figure 4 for Figure 1 An enlarged schematic diagram of region R in FIG.

[0030] Figure 5For other embodiments of the present invention Figure 1 An enlarged schematic diagram of region R in FIG.

[0031] Explanation of symbols

[0032] 10: Semiconductor structure

[0033] 100,100A,100B,100C,100D:Component structure

[0034] 102: Base

[0035] 104,104A,104B,104C: Base perforation

[0036] 106,116: Dielectric layer

[0037] 108: Bonding pad

[0038] 110,128:Through hole

[0039] 112A, 112B, 120, 122: Internal connection structure

[0040] 114:Metal layer

[0041] 118: Connecting terminal

[0042] 124: Rewiring layer

[0043] 126: Wire

[0044] P1: Part 1

[0045] P2: Part 2

[0046] P3: Part 3

[0047] P4: Part 4

[0048] P5: Part 5

[0049] R: Region

[0050] R1: Zone 1

[0051] R2: Second Zone

[0052] S1: Front

[0053] S2: Back DETAILED DESCRIPTION

[0054] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0055] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 2 are cross-sectional views of semiconductor structures according to some other embodiments of the present invention. Figure 3 are cross-sectional views of semiconductor structures according to some other embodiments of the present invention.

[0056] Please refer to Figure 1 , the semiconductor structure 10 includes a plurality of device structures 100 stacked. In addition, the number of device structures 100 is not limited to the number shown in the figure. As long as the number of device structures 100 is multiple, it belongs to the scope covered by the present invention. For example, the plurality of device structures 100 may include a device structure 100A, a device structure 100B, a device structure 100C, and a device structure 100D. The device structure 100B is located on the device structure 100A. The device structure 100C is located on the device structure 100B. The device structure 100D is located on the device structure 100C.

[0057] In some embodiments, each element structure 100 may be a wafer (chip) structure or a chip structure. In some embodiments, each element structure 100 may be a logic element structure or a memory element structure (e.g., a dynamic random access memory (DRAM) structure). That is, each element structure 100 may be a wafer structure including a logic element, a wafer structure including a memory element (e.g., a DRAM element), a chip structure including a logic element, or a chip structure including a memory element (e.g., a DRAM element). In this embodiment, the last element structure 100A may be a logic element structure, and the remaining element structures 100 (e.g., element structures 100B to 100D) may be memory element structures (e.g., DRAM structures).

[0058] The plurality of device structures 100 include a plurality of substrates 102 and a plurality of substrate through-holes 104. In some embodiments, the substrate 102 may be a semiconductor substrate, such as a silicon substrate. The plurality of substrate through-holes 104 are located in the plurality of substrates 102. The number of substrate through-holes 104 in the last device structure 100 (e.g., device structure 100A) is less than the number of substrate through-holes 104 in another device structure 100 (e.g., device structure 100B). In some embodiments, the number of substrate through-holes 104 in the last device structure 100 (e.g., device structure 100A) may be less than the number of substrate through-holes 104 in each device structure 100 of the remaining device structures 100 (e.g., device structures 100B to 100D). In some embodiments, the material of the substrate through-holes 104 is, for example, copper, tantalum, tantalum nitride, or a combination thereof. In some embodiments, a dielectric layer (not shown) may be provided between the substrate through-holes 104 and the substrate 102.

[0059] The plurality of substrate through-holes 104 include a plurality of substrate through-holes 104A. Each device structure 100 includes a corresponding substrate 102 and a corresponding substrate through-hole 104A. Each substrate through-hole 104A penetrates the corresponding substrate 102. In some embodiments, the substrate through-hole 104A may be a substrate through-hole in the device region. In some embodiments, the plurality of substrate through-holes 104A may be separated from each other.

[0060] The substrate through hole 104A in the last device structure 100 (e.g., device structure 100A) is aligned with and electrically connected to the substrate through hole 104A in another device structure 100 (e.g., device structure 100B), thereby providing a good heat conduction path, thereby improving the heat dissipation capability of the semiconductor structure 10, and providing a good signal transmission path and shortening the signal transmission path.

[0061] In some embodiments, the substrate through-hole 104A in the last device structure 100 (e.g., device structure 100A) and the plurality of substrate through-holes 104A in the remaining device structures 100 (e.g., device structures 100B to 100D) may be aligned with each other and may be electrically connected to each other. Thus, the heat dissipation capability of the semiconductor structure 10 may be further improved, and a good signal transmission path may be further provided and the signal transmission path may be further shortened.

[0062] In some embodiments, the plurality of substrate through-holes 104 may further include a plurality of substrate through-holes 104B. The plurality of substrate through-holes 104B are located in the plurality of substrates 102. Each substrate through-hole 104B may penetrate the corresponding substrate 102. In some embodiments, the substrate through-hole 104B may be a substrate through-hole in an input / output (I / O) region. In some embodiments, the plurality of substrate through-holes 104B may be separated from each other. In some embodiments, the plurality of substrate through-holes 104B and the plurality of substrate through-holes 104A may be separated from each other. The plurality of substrate through-holes 104B in the plurality of element structures 100 may be aligned with each other. In some embodiments, the plurality of substrate through-holes 104B aligned with each other may not be electrically connected to each other. In some embodiments, the plurality of substrate through-holes 104B aligned with each other may be electrically connected to each other.

[0063] In some embodiments, one of two adjacent device structures 100 may be hybrid-bonded to the other of two adjacent device structures 100. In some embodiments, the plurality of device structures 100 may further include a plurality of dielectric layers 106 and a plurality of bonding pads 108. The plurality of dielectric layers 106 are located on the plurality of substrates 102. In some embodiments, two adjacent dielectric layers 106 of two adjacent device structures 100 may be bonded to each other. In some embodiments, a portion of the substrate through-holes 104 may also be located in the dielectric layer 106. In some embodiments, the dielectric layer 106 may be a multi-layer structure. In some embodiments, the material of the dielectric layer 106 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0064] A plurality of dielectric layers 106 may be respectively disposed on the front side S1 and the back side S2 of the substrate 102. The dielectric layer 106 on the front side S1 may include front end of line (FEOL) elements (e.g., logic elements or memory elements) (not shown) and interconnect structures (not shown) and back end of line (BEOL) interconnect structures (not shown), and their description is omitted here. In this embodiment, as shown in FIG. Figure 1 As shown, the front side S1 of the substrate 102 in the device structure 100B may face the front side S1 of the substrate 102 in the device structure 100A, the front side S1 of the substrate 102 in the device structure 100C may face the back side S2 of the substrate 102 in the device structure 100B, and the front side S1 of the substrate 102 in the device structure 100D may face the back side S2 of the substrate 102 in the device structure 100C, but the present invention is not limited thereto. In other embodiments, such as Figure 2As shown, the back side S2 of the substrate 102 in the element structure 100B may face the front side S1 of the substrate 102 in the element structure 100A, the back side S2 of the substrate 102 in the element structure 100C may face the front side S1 of the substrate 102 in the element structure 100B, and the back side S2 of the substrate 102 in the element structure 100D may face the front side S1 of the substrate 102 in the element structure 100C.

[0065] A plurality of bonding pads 108 are located in the plurality of dielectric layers 106. In some embodiments, two adjacent bonding pads 108 in two adjacent element structures 100 may be bonded to each other. In some embodiments, the material of the bonding pads 108 is, for example, a conductive material such as copper. In some embodiments, the plurality of bonding pads 108 and the plurality of substrate through-holes 104A may be aligned with each other. In some embodiments, the plurality of bonding pads 108 and the plurality of substrate through-holes 104A aligned with each other may be electrically connected to each other. In some embodiments, the plurality of bonding pads 108 and the plurality of substrate through-holes 104B may be aligned with each other. In some embodiments, the bonding pads 108 and the substrate through-holes 104B adjacent to each other may be electrically connected to each other.

[0066] In some embodiments, the plurality of device structures 100 may further include a plurality of through holes 110. The plurality of through holes 110 are located in the plurality of dielectric layers 106. In some embodiments, the through holes 110 may be used as through dielectric vias (TDVs). In some embodiments, the through holes 110 may be located in the dielectric layer 106 on the front side S1. Each through hole 110 is located between a corresponding bonding pad 108 and a corresponding substrate through hole 104A. In some embodiments, the plurality of bonding pads 108, the plurality of through holes 110, and the plurality of substrate through holes 104A may be aligned with each other. In some embodiments, the plurality of bonding pads 108, the plurality of through holes 110, and the plurality of substrate through holes 104A aligned with each other may be electrically connected to each other. In some embodiments, the material of the through hole 110 is, for example, copper, tantalum, tantalum nitride, or a combination thereof.

[0067] In some embodiments, the device structure 100 may further include an internal connection structure 112A and an internal connection structure 112B. Figure 1As shown, the through hole 110 can be directly connected to the bonding pad 108, and the through hole 110 can be electrically connected to the substrate through hole 104A through the internal connection structure 112A, but the present invention is not limited thereto. In other embodiments, the through hole 110 can be electrically connected to the bonding pad 108 through other internal connection structures (not shown). In the present embodiment, the internal connection structure 112A can be a single-layer structure, but the present invention is not limited thereto. In other embodiments, the internal connection structure 112A can be a multi-layer structure. In addition, the substrate through hole 104B can be electrically connected to the internal connection structure 112B. In some embodiments, the material of the internal connection structure 112A and the material of the internal connection structure 112B are, for example, copper, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride or a combination thereof.

[0068] In some embodiments, Figure 1 As shown, the width of the plurality of through holes 110 may be equal to the width of the plurality of substrate through holes 104A, thereby helping to further improve the heat dissipation capability of the semiconductor structure 10. In other embodiments, such as Figure 3 As shown, the width of the plurality of through holes 110 may be smaller than the width of the plurality of through substrate holes 104A.

[0069] In some embodiments, the last device structure 100 (e.g., device structure 100A) further includes a metal layer 114. The metal layer 114 may be located in the dielectric layer 106. The metal layer 114 may be connected to the substrate through-hole 104 (e.g., substrate through-hole 104A). In some embodiments, the metal layer 114 may be used as a heat sink. In some embodiments, the metal layer 114 may be used as a redistribution layer. In some embodiments, the material of the metal layer 114 is a conductive material such as copper.

[0070] In some embodiments, the semiconductor structure 10 may further include a dielectric layer 116, a plurality of connection terminals 118, and a plurality of interconnect structures 120. The dielectric layer 116 is located on the dielectric layer 106 of another endmost device structure 100 (e.g., device structure 100D). In some embodiments, the dielectric layer 116 may be a multi-layer structure. In some embodiments, the material of the dielectric layer 116 may be silicon oxide, silicon nitride, or a combination thereof.

[0071] Each connection terminal 118 can be electrically connected to a corresponding substrate through-hole 104. In some embodiments, the connection terminal 118 can be a bump (e.g., a solder ball), but the present invention is not limited thereto. The interconnect structure 120 is located in and on the dielectric layer 116. In some embodiments, the interconnect structure 120 can include an under-bump metallurgy (UBM), a wire, a through hole, or a combination thereof. In some embodiments, the connection terminal 118 can be electrically connected to the substrate through-hole 104 through the interconnect structure 120 and the bonding pad 108.

[0072] Figure 4 for Figure 1 An enlarged schematic diagram of region R in FIG. Figure 5 According to some other embodiments of the present invention Figure 1 Schematic diagram of the enlarged area R in FIG. Figure 1 in, omit Figure 4 and Figure 5 In addition, Figure 1 , Figure 4 and Figure 5 The components are not drawn to the same scale.

[0073] Please refer to Figure 4 , a plurality of device structures 100 may include an internal connection structure 122. The internal connection structure 122 includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 is located in the device structure 100A. The second portion P2 and the third portion P3 are located in the device structure 100B and are separated from each other. The second portion P2 and the third portion P3 may be connected to the first portion P1. The second portion P2 and the third portion P3 may be electrically connected to each other through the first portion P1. In this way, when there is a seal ring (not shown) between the first region R1 and the second region R2 of the device structure 100B, since the internal connection structure 122 can cross the seal ring, the device (not shown) in the first region R1 and the device (not shown) in the second region R2 can be electrically connected to each other through the internal connection structure 122. In some embodiments, the internal connection structure 122 includes a fourth portion P4 and a fifth portion P5. The fourth portion P4 and the fifth portion P5 are located in the device structure 100A. The first part P1, the fourth part P4 and the fifth part P5 can be separated from each other. The fourth part P4 can be connected to the second part P2. The fifth part P5 can be connected to the third part P3.

[0074] In some embodiments, the interconnect structure 122 may include a plurality of redistribution layers 124, substrate through vias 104C, a plurality of conductive lines 126, a plurality of vias 128, a plurality of bonding pads 108, or a combination thereof. Figure 4 As shown, the interconnect structure 122 may include a plurality of redistribution layers 124, substrate through-holes 104C, a plurality of conductive lines 126, a plurality of through-holes 128, and a plurality of bonding pads 108, but the present invention is not limited thereto. Figure 5 As shown, the interconnect structure 122 may not include the bonding pad 108, and the interconnect structure 122 may include a plurality of redistribution layers 124 and a plurality of through substrate vias 104C. In some embodiments, the material of the interconnect structure 122 may include copper, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof.

[0075] In addition, Figures 1 to 5In the drawings, the same or similar components are denoted by the same symbols, and their description is omitted.

[0076] Based on the above embodiments, it can be known that in the semiconductor structure 10 proposed by the present invention, each device structure 100 includes a corresponding substrate 102 and a corresponding substrate through-hole 104A. Each substrate through-hole 104A penetrates the corresponding substrate 102. The number of substrate through-holes 104 in the last device structure 100 (e.g., device structure 100A) is less than the number of substrate through-holes 104 in another device structure 100 (e.g., device structure 100B). The substrate through-hole 104A in the last device structure 100 (e.g., device structure 100A) and the substrate through-hole 104A in another device structure 100 (e.g., device structure 100B) are aligned with each other and electrically connected to each other. Therefore, a good heat conduction path can be provided by the substrate through-holes 104A that are aligned with each other and electrically connected to each other, thereby improving the heat dissipation capacity of the semiconductor structure 10. In addition, a good signal transmission path can be provided and the signal transmission path can be shortened by the substrate through-holes 104A that are aligned with each other and electrically connected to each other.

[0077] In summary, in the semiconductor structure of the above embodiment, the heat dissipation capability of the semiconductor structure can be improved, a good signal transmission path can be provided, and the signal transmission path can be shortened by using the substrate through holes that are aligned with each other and electrically connected to each other.

[0078] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A semiconductor structure comprising a plurality of element structures stacked together, wherein the plurality of element structures comprise: Multiple substrates; as well as A plurality of substrate through-holes are located in the plurality of substrates and include a plurality of first substrate through-holes, wherein Each of the element structures comprises a corresponding substrate and a corresponding first substrate through-hole, Each of the first substrate perforations penetrates the corresponding substrate, The number of the substrate through-holes in the last element structure is smaller than the number of the substrate through-holes in another element structure, and The first substrate through-hole in the last device structure and the first substrate through-hole in another device structure are aligned with each other and electrically connected to each other.

2. The semiconductor structure of claim 1, wherein The number of the substrate through-holes in the last element structure is smaller than the number of the substrate through-holes in each of the remaining element structures, and The first substrate through-hole in the last device structure and the first substrate through-holes in the remaining device structures are aligned with each other and electrically connected to each other.

3. The semiconductor structure of claim 1, wherein the plurality of substrate through holes further comprises: A plurality of second substrate through-holes are located in the plurality of substrates, wherein Each of the second substrate perforations penetrates the corresponding substrate, A plurality of the second substrate through holes in a plurality of the element structures are aligned with each other, and The plurality of second substrate through holes aligned with each other are not electrically connected to each other. 4 . The semiconductor structure of claim 3 , wherein a plurality of the first through-substrate vias are separated from each other, and a plurality of the second through-substrate vias are separated from each other. The semiconductor structure as claimed in claim 3 , wherein the second through-substrate vias and the first through-substrate vias are separated from each other. 6 . The semiconductor structure as claimed in claim 1 , wherein one of the two adjacent device structures is hybrid-bonded to the other of the two adjacent device structures.

7. The semiconductor structure according to claim 1, wherein the plurality of device structures further comprises: A plurality of dielectric layers, located on the plurality of substrates; as well as A plurality of bonding pads are located in the plurality of dielectric layers. 8 . The semiconductor structure as claimed in claim 7 , wherein two adjacent dielectric layers in two adjacent device structures are bonded to each other. 9 . The semiconductor structure as claimed in claim 7 , wherein two adjacent bonding pads in two adjacent device structures are bonded to each other. 10 . The semiconductor structure of claim 7 , wherein the plurality of bonding pads and the plurality of first through substrate vias are aligned with each other. 11 . The semiconductor structure as claimed in claim 10 , wherein the plurality of bonding pads aligned with each other and the plurality of the first through substrate vias are electrically connected to each other.

12. The semiconductor structure according to claim 7, wherein the plurality of device structures further comprises: A plurality of through holes are located in a plurality of the dielectric layers, wherein Each of the through holes is located between the corresponding bonding pad and the corresponding first substrate through hole. 13 . The semiconductor structure of claim 12 , wherein a width of the plurality of through holes is equal to a width of the plurality of first substrate through holes. 14 . The semiconductor structure of claim 12 , wherein a width of the plurality of through holes is smaller than a width of the plurality of first substrate through holes. 15 . The semiconductor structure of claim 12 , wherein the plurality of bonding pads, the plurality of through holes, and the plurality of first through substrate vias are aligned with each other. 16 . The semiconductor structure as claimed in claim 15 , wherein the plurality of bonding pads, the plurality of through holes and the plurality of first substrate through vias aligned with each other are electrically connected to each other. 17 . The semiconductor structure as claimed in claim 1 , wherein each of the device structures comprises a wafer structure or a chip structure.

18. The semiconductor structure of claim 1, wherein the last device structure comprises a logic device structure, and the remaining device structures comprise memory device structures.

19. The semiconductor structure of claim 1, wherein the plurality of device structures comprises: a first component structure; a second component structure, located on the first component structure; as well as Internal connection structure, including: A first portion, located in the first element structure; as well as The second part and the third part are located in the second element structure and are separated from each other, wherein the second part and the third part are connected to the first part, and The second portion and the third portion are electrically connected to each other through the first portion. 20 . The semiconductor structure of claim 19 , wherein the interconnect structure comprises a redistribution layer, a second through substrate via, a conductive line, a via, a bonding pad, or a combination thereof.

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