Semiconductor structure, manufacturing method thereof and adapter plate

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and an adapter plate. The semiconductor structure comprises a glass substrate; the conductive structure penetrates through the glass substrate; the glass dielectric layer is positioned between the glass substrate and the conductive structure; the melting point of the glass substrate is higher than that of the glass dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof, and an adapter plate. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. As the consumer market has higher and higher requirements for electronic products in terms of miniaturization and diversified functions, advanced packaging technology that integrates multiple chips has emerged.

[0003] In 2.5D or 3D advanced packaging, interposers are usually used to integrate multiple chips and realize the interconnection between multiple chips. Common interposers include silicon interposers, organic interposers, and glass interposers. Among them, glass interposers have advantages such as excellent insulation and low cost. However, how to simplify the manufacturing process of glass interposers and improve the process yield has become an urgent problem to be solved in the industry. Summary of the invention

[0004] The present disclosure provides a semiconductor structure and a manufacturing method thereof, and an adapter plate.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] Glass substrate;

[0007] A conductive structure extending through the glass substrate;

[0008] A glass dielectric layer is located between the glass substrate and the conductive structure; the melting point of the glass substrate is higher than the melting point of the glass dielectric layer.

[0009] In some embodiments, the glass substrate and / or the glass dielectric layer may be made of silicate glass.

[0010] In some embodiments, the conductive structure includes:

[0011] A conductive column, passing through the glass substrate;

[0012] The barrier layer is located between the conductive pillar and the glass dielectric layer.

[0013] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising:

[0014] providing a glass substrate, the glass substrate comprising a hole extending in a thickness direction;

[0015] Filling the hole with molten glass dielectric material; the melting point of the glass substrate is higher than the melting point of the glass dielectric material;

[0016] placing a conductive structure in the hole; wherein the glass dielectric material between the glass substrate and the conductive structure solidifies to form a glass dielectric layer;

[0017] The glass substrate is thinned so that two ends of the conductive structure are exposed from two sides of the glass substrate respectively.

[0018] In some embodiments, the material of the glass substrate and / or the glass dielectric material includes silicate glass.

[0019] In some embodiments, providing a glass substrate comprises:

[0020] providing an initial glass substrate;

[0021] A blind hole extending in a thickness direction is formed in the initial glass substrate.

[0022] In some embodiments, the manufacturing method further comprises:

[0023] forming the conductive structure on a carrier;

[0024] Placing the conductive structure in the hole comprises:

[0025] The conductive structure on the carrier is placed in the blind hole on the glass substrate, so that an end of the conductive structure away from the carrier is spaced a preset distance from the bottom of the blind hole.

[0026] In some embodiments, the glass substrate includes a first surface and a second surface opposite to each other, and the blind hole is exposed from the first surface; and thinning the glass substrate so that two ends of the conductive structure are respectively exposed from two sides of the glass substrate includes:

[0027] removing the carrier plate;

[0028] forming a dielectric layer covering the conductive structure on the first surface;

[0029] removing the dielectric layer and a portion of the conductive structure above the first surface to expose one end of the conductive structure;

[0030] A portion of the glass substrate is removed from the second surface to expose the other end of the conductive structure.

[0031] In some embodiments, forming the conductive structure on the carrier includes:

[0032] forming a conductive column on the carrier;

[0033] A barrier layer is formed covering the conductive pillar.

[0034] In a third aspect, the present disclosure provides an adapter plate, wherein the adapter plate includes a semiconductor structure formed by the manufacturing method according to any one of the above embodiments.

[0035] In the disclosed embodiment, the glass dielectric layer is located between the glass substrate and the conductive structure, and the melting point of the glass substrate is higher than that of the glass dielectric layer, that is, the glass dielectric layer can be formed by cooling and solidifying the molten glass dielectric material. In this way, the glass dielectric layer makes the adhesion between the conductive structure and the glass substrate stronger, which is conducive to improving the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided by the present disclosure;

[0037] Figure 2a and Figure 2b A schematic diagram of an initial glass substrate provided by the present disclosure;

[0038] Figure 3a and Figure 3b A schematic diagram of laser modification of an initial glass substrate provided by the present disclosure;

[0039] Figure 4a and Figure 4b A schematic diagram of etching an initial glass substrate to form a hole provided by the present disclosure;

[0040] Figure 5a and Figure 5b A schematic diagram of forming a conductive column on a carrier provided by the present disclosure;

[0041] Figure 6 A schematic diagram of forming a barrier layer provided in the present disclosure;

[0042] Figure 7 A schematic diagram of filling a molten glass medium material in a hole provided by the present disclosure;

[0043] Figure 8 A schematic diagram of placing a conductive structure in a hole provided by the present disclosure;

[0044] Fig. 9 A schematic diagram of a semiconductor structure after removing a carrier provided by the present disclosure;

[0045] Fig.10 A schematic diagram of forming a dielectric layer provided by the present disclosure;

[0046] Fig.11 A schematic diagram of a semiconductor structure after thinning a glass substrate provided by the present disclosure;

[0047] Fig.12 A schematic diagram of an adapter plate provided in the present invention. DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0050] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0051] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0053] In some embodiments, the preparation of through glass vias (TGV) in the glass transfer plate is mainly to first carve holes in the glass by laser induced etching, and then fill the formed holes with conductive materials. For example, the filling materials include an adhesion layer, a seed layer, and electroplated copper in sequence. However, this method has a complex process and a high manufacturing cost. When filling the through glass holes, it also faces the problem of weak metal-glass adhesion. The electroplating of copper is prone to problems such as holes and uneven filling, which affects the subsequent electrical interconnection performance and has a low product yield.

[0054] like Figure 1 As shown, the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising the following steps:

[0055] Step S10, providing a glass substrate, wherein the glass substrate comprises a hole extending along a thickness direction;

[0056] Step S20, filling the hole with molten glass dielectric material; the melting point of the glass substrate is higher than the melting point of the glass dielectric material;

[0057] Step S30, placing a conductive structure in the hole; wherein the glass dielectric material between the glass substrate and the conductive structure solidifies to form a glass dielectric layer;

[0058] Step S40 , thinning the glass substrate so that two ends of the conductive structure are exposed from two sides of the glass substrate respectively.

[0059] It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown. For example, the execution order of step S20 and step S30 may be interchanged. Figures 2a to 11 The process diagram corresponding to the manufacturing flow of the semiconductor structure 100 is described in detail.

[0060] refer to Figure 4a and Figure 4b ,in Figure 4b for Figure 4aThe top view corresponding to the semiconductor structure 100 shown. The material of the glass substrate 110 includes but is not limited to silicon dioxide (quartz glass), silicate, borosilicate, aluminosilicate, etc. The glass substrate 110 includes a hole 111 extending in the thickness direction, and the hole 111 can be formed in the glass substrate by laser induced modification, etching and other processes. In the present disclosure, the etching process can be divided into dry etching (Dry Etching) and wet etching (Wet Etching). Among them, dry etching can include ion milling etching (Ion Neam Milling Etching), plasma etching (Plasma Etching), reactive ion etching (Reactive Ion Etching) or laser ablation (Laser Ablation), etc.; wet etching is etching using a solvent or solution, such as an acid or alkali solution. Exemplarily, the hole 111 can be formed by laser induced modification and acid wet etching. It should be noted that, Figure 4a and Figure 4b Only the case where the hole 111 is a blind hole is shown in the figure, but the hole 111 can be either a through hole or a blind hole, and the present disclosure does not impose too many restrictions.

[0061] refer to Figure 7 , the hole 111 of the glass substrate 110 is filled with molten glass dielectric material 112, and the glass dielectric material 112 can be used to solidify to form a glass dielectric layer, so as to fix the conductive structure in the hole 111, so that the conductive structure and the glass substrate 110 have strong adhesion. The glass dielectric material 112 is different from the material of the glass substrate 110, and the melting point of the glass substrate 110 is higher than the melting point of the glass dielectric material 112. In this way, the temperature of the molten glass dielectric material 112 is lower than the melting point of the glass substrate 110, thereby ensuring that the glass substrate 110 will not melt during the manufacturing process.

[0062] refer to Figure 8, the pre-prepared conductive structure 120 can be placed in the hole 111, and the glass dielectric material between the glass substrate 110 and the conductive structure 120 solidifies to form a glass dielectric layer 113, so that the conductive structure 120 is fixed in the hole 111. In this way, compared with the method of sequentially forming an adhesion layer, a seed layer and an electroplated metal in the hole 111, the embodiment of the present disclosure uses the molten glass dielectric material to cool and fix the pre-prepared conductive structure 120, thereby avoiding the problems of voids and uneven filling in the process of filling the electroplated metal. Exemplarily, the conductive structure 120 can be a metal material or an alloy material, for example, a material containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0063] refer to Fig.11 , the glass substrate 110 is thinned so that the two ends of the conductive structure 120 are exposed from the two sides of the glass substrate 110. Exemplarily, at least one surface of the glass substrate 110 can be thinned by etching, mechanical polishing, chemical mechanical polishing (CMP) and other processes, so that the two ends of the conductive structure 120 are exposed. In some embodiments, the two ends of the conductive structure 120 are substantially flush with the two opposite surfaces of the thinned glass substrate 110.

[0064] In this way, the embodiment of the present disclosure utilizes molten glass dielectric material to cool and fix the pre-prepared conductive structure 120, which can avoid the problem of voids and uneven filling during the electroplating metal filling process and simplify the manufacturing process. On the other hand, the glass dielectric layer 113 makes the adhesion between the conductive structure 120 and the glass substrate 110 stronger, which is conducive to improving the process yield.

[0065] It is understandable that for the preparation of glass through holes with a high aspect ratio, filling with electroplated metal is more prone to voids and unevenness problems, and the manufacturing method of the semiconductor structure provided by the present disclosure is more advantageous because the conductive structure is prepared in advance.

[0066] In some embodiments, the hole may be first filled with molten glass dielectric material, and then the conductive structure may be placed in the hole with the molten glass dielectric material; in other embodiments, the conductive structure may be first placed in the hole without contacting the inner wall of the hole, and then the hole with the conductive structure may be filled with molten glass dielectric material.

[0067] In some embodiments, the material of the glass substrate 110 and / or the glass dielectric material 112 includes silicate glass.

[0068] In the embodiment of the present disclosure, the glass substrate 110 and the glass dielectric material 112 are made of different materials, and at least one of the glass substrate 110 and the glass dielectric material 112 is silicate glass, which has advantages such as good light transmittance and thermal stability. Exemplarily, the material of the glass substrate 110 is aluminosilicate glass, and the glass dielectric material 112 is soda-lime silicate glass (such as Na2O·CaO·6SiO2). The temperature of molten soda-lime silicate glass is 550-600°C, while the melting point of aluminosilicate glass is above 1500°C.

[0069] In some embodiments, Figures 2a to 4b As shown, providing the glass substrate 110 includes: providing an initial glass substrate 101 ; and forming a blind hole extending along a thickness direction in the initial glass substrate 101 .

[0070] For example, reference Figure 2a and Figure 2b ,in Figure 2b for Figure 2a The top view corresponding to the semiconductor structure 100 is shown, and an initial glass substrate 101 is provided. Here, the initial glass substrate 101 is an aluminosilicate glass substrate as an example for description.

[0071] refer to Figure 3a and Figure 3b ,in Figure 3b for Figure 3a The top view corresponding to the semiconductor structure 100 is shown, and the corresponding area of ​​the initial glass substrate 101 is laser-induced modified to facilitate subsequent wet etching.

[0072] Reference 4a and Figure 4b , using acid wet etching to remove part of the material in the laser-induced modified area in the above step, to form a blind hole (ie, hole 111).

[0073] In some embodiments, blind holes may be formed in the initial glass substrate by laser ablation, plasma etching, or the like.

[0074] In some embodiments, a through hole may be formed in the initial glass substrate. In this case, before the molten glass dielectric material is filled, a blocking structure (such as temporarily bonding another substrate) needs to be provided on one side of the through hole to prevent the molten glass dielectric material from flowing out. It is understandable that directly forming a through hole in the initial glass substrate can reduce the thickness of the glass substrate in the subsequent process.

[0075] In some embodiments, Figures 5a to 6 As shown, forming a conductive structure 120 on the carrier 102 includes: forming a conductive column 121 on the carrier 102; and forming a barrier layer 122 covering the conductive column 121.

[0076] refer to Figure 5a and Figure 5b ,in Figure 5b for Figure 5a Corresponding to the top view, a conductive column 121 can be formed on the carrier 102 by deposition, photolithography, etching and other processes. The material of the carrier 102 includes but is not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), polymer materials, etc. The material of the conductive column 121 includes but is not limited to metal materials, doped semiconductor materials, etc., and the material of the conductive column 121 is copper or tungsten as an example for illustration. In the present disclosure, the deposition process includes but is not limited to: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD) and combinations thereof. Exemplarily, the arrangement of the conductive pillars 121 is designed in advance by exposing a pattern, and a corresponding mask is formed, and then etching is performed through the mask to form the corresponding conductive pillars 121 .

[0077] refer to Figure 6, a barrier layer 122 is formed on the surface of the conductive pillar 121 by a deposition process. The barrier layer 122 can be used to prevent the diffusion of the material of the conductive pillar 121, and can also improve the adhesion between the conductive structure 120 and the glass dielectric layer. The material of the barrier layer 122 includes but is not limited to titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. Exemplarily, a titanium or titanium nitride barrier layer can be deposited on a copper conductive pillar or a tungsten conductive pillar by a physical vapor deposition process, and the thickness of the barrier layer is about 300 to 500 nm. In some embodiments, the barrier layer 122 can also improve the stress distribution between the conductive pillar 121 and the glass dielectric layer to further improve the process yield.

[0078] In some embodiments, the manufacturing method further includes: forming a conductive structure on the carrier; Figure 8 As shown, placing the conductive structure in the hole includes: placing the conductive structure 120 on the carrier 102 in the blind hole (i.e., hole 111) on the glass substrate 110, so that the end of the conductive structure 120 away from the carrier 102 is spaced a preset distance from the bottom of the blind hole (i.e., hole 111).

[0079] In the disclosed embodiment, the conductive structure 120 on the carrier 102 is first aligned with the hole 111 on the glass substrate 110; then the carrier 102 is slowly pressed down so that the conductive structure 120 gradually enters the hole 111 filled with molten glass dielectric material until the end of the conductive structure 120 away from the carrier 102 is spaced from the bottom of the hole 111 by a preset distance. The preset distance here is to prevent the conductive structure 120 from being bent and damaged due to the conductive structure 120 being inserted too deep and touching the bottom of the blind hole. It can be understood that based on the length of the conductive structure 120, the depth of the hole 111 and the moving distance of the carrier 102, it can be determined whether the conductive structure 120 has reached the predetermined position, that is, whether the distance between the end of the conductive structure 120 away from the carrier 102 and the bottom of the blind hole has reached the preset distance. It should be noted that the process of the conductive structure 120 entering the hole 111 filled with molten glass dielectric material needs to be carried out in an inert gas atmosphere to prevent the conductive structure 120 from being oxidized.

[0080] For example, in an inert gas atmosphere containing a small amount of formic acid gas (e.g., formic acid gas with a concentration of 2%), a conductive structure 120 made of copper or tungsten is slowly pressed into a hole 111 filled with a molten glass dielectric material, and then the glass dielectric material is cooled and solidified to form a glass dielectric layer 113. The diameter of the conductive structure 120 (copper or tungsten) is about 25 to 100 μm, the diameter of the hole 111 is about 10 to 100 μm, and the aspect ratio of the hole 111 is 10:1 to 50:1.

[0081] In some embodiments, the conductive structure 120 may be placed in the hole 111 first, and then the molten glass dielectric material may be filled into the hole 111. Specifically, the conductive structure 120 on the carrier 102 is aligned with the hole 111 on the glass substrate 110; then the carrier 102 is slowly pressed down so that the conductive structure 120 gradually enters the hole 111 until the end of the conductive structure 120 away from the carrier 102 is spaced a preset distance from the bottom of the hole 111; finally, the molten glass dielectric material is filled into the hole 111. It is understood that the above process also needs to be performed under an inert gas atmosphere.

[0082] In some embodiments, Figures 9 to 11 As shown, the glass substrate 110 includes a first surface 110a and a second surface 110b opposite to each other, and the blind hole (i.e., hole 111) is exposed from the first surface 110a; the glass substrate 110 is thinned so that the two ends of the conductive structure 120 are exposed from the two sides of the glass substrate 110 respectively, including: removing the carrier 102; forming a dielectric layer 114 covering the conductive structure 120 on the first surface 110a; removing the dielectric layer 114 and a portion of the conductive structure 120 above the first surface 110a to expose one end of the conductive structure 120; and removing a portion of the glass substrate 110 from the second surface 110b to expose the other end of the conductive structure 120.

[0083] refer to Fig. 9 After the glass dielectric material cools and solidifies to form the glass dielectric layer 113 , the carrier 102 is removed. At this time, the end of the conductive structure 120 away from the bottom of the hole 111 is higher than the first surface 110 a of the glass substrate 110 .

[0084] refer to Fig.10 , a dielectric layer 114 covering the conductive structure 120 can be formed on the first surface 110a of the glass substrate 110 by using a deposition process, that is, the top of the dielectric layer 114 is higher than the end of the conductive structure 120 away from the bottom of the hole 111. In this way, the dielectric layer 114 is conducive to reducing the difficulty of removing the portion of the conductive structure 120 above the first surface 110a in the subsequent planarization process. Exemplarily, the material of the dielectric layer 114 includes but is not limited to silicon oxide (such as silicon dioxide), silicon nitride (such as silicon oxynitride), nitride (such as silicon nitride), etc.

[0085] refer to Fig.11 , a chemical mechanical polishing process can be used to remove the dielectric layer and a portion of the conductive structure 120 above the first surface to expose one end of the conductive structure 120, and a portion of the glass substrate 110 can be polished away from the second surface to expose the other end of the conductive structure 120. In some embodiments, after chemical mechanical polishing, the two ends of the conductive structure 120 are substantially flush with two opposite surfaces of the thinned glass substrate 110.

[0086] like Fig.11 As shown, the present disclosure provides a semiconductor structure 100, including: a glass substrate 110; a conductive structure 120, which penetrates the glass substrate 110; a glass dielectric layer 113, which is located between the glass substrate 110 and the conductive structure 120; the melting point of the glass substrate 110 is higher than the melting point of the glass dielectric layer 113.

[0087] In the disclosed embodiment, the glass dielectric layer 113 is located between the glass substrate 110 and the conductive structure 120. The melting point of the glass substrate 110 is higher than that of the glass dielectric layer 113, that is, the glass dielectric layer 113 can be formed by cooling and solidifying the molten glass dielectric material. In this way, the glass dielectric layer 113 makes the adhesion between the conductive structure 120 and the glass substrate 110 stronger, which is conducive to improving the process yield.

[0088] In some embodiments, the material of the glass substrate 110 and / or the glass dielectric layer 113 includes silicate glass.

[0089] In the disclosed embodiment, the glass substrate 110 and the glass dielectric layer 113 are made of different materials, and at least one of the glass substrate 110 and the glass dielectric layer 113 is made of silicate glass, which has advantages such as good light transmittance and thermal stability. Exemplarily, the material of the glass substrate 110 is aluminosilicate glass, and the material of the glass dielectric layer 113 is soda-lime silicate glass (such as Na2O·CaO·6SiO2). The temperature of molten soda-lime silicate glass is 550-600°C, while the melting point of aluminosilicate glass is above 1500°C.

[0090] In some embodiments, the conductive structure 120 includes: a conductive column 121 penetrating the glass substrate 110 ; and a barrier layer 122 located between the conductive column 121 and the glass dielectric layer 113 .

[0091] The material of the conductive pillar 121 includes but is not limited to metal materials, doped semiconductor materials, etc., and illustratively, the material of the conductive pillar 121 is copper or tungsten. The barrier layer 122 can be used to prevent the diffusion of the material of the conductive pillar 121, and can also improve the adhesion between the conductive structure 120 and the glass dielectric layer. The material of the barrier layer 122 includes but is not limited to titanium, titanium nitride, tantalum, tantalum nitride, etc. In some embodiments, the barrier layer has a thickness of about 300 to 500 nm, and the barrier layer 122 can also improve the stress distribution between the conductive pillar 121 and the glass dielectric layer 113 to further improve the process yield.

[0092] like Fig.12 As shown, the present disclosure further provides a transfer board 200 , comprising a semiconductor structure 100 formed by the manufacturing method of any one of the above embodiments.

[0093] In the embodiment of the present disclosure, the adapter board 200 includes a semiconductor structure 100, and an upper wiring layer 201 and a lower wiring layer 202 located on both sides of the semiconductor structure 100. The upper wiring layer 201 is connected to a plurality of conductive structures 120, and the lower wiring layer 202 is connected to a plurality of conductive structures 120. The adapter board 200 can be applied to 2.5D packaging technology and 3D packaging technology, and a plurality of chips can be integrated on the adapter board 200, and interconnection between the plurality of chips can be realized.

[0094] It should be noted that the semiconductor structure and the manufacturing method thereof provided by the present disclosure are not only applicable to glass transfer plates, but also applicable to related components such as glass substrates, and no further limitations are given here.

[0095] The present disclosure also provides an electronic device, comprising any semiconductor structure in the above embodiments.

[0096] The semiconductor structure involved in the embodiments of the present disclosure can be used in various electronic devices. The electronic devices here include but are not limited to mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, and any other suitable electronic devices.

[0097] In the semiconductor structure and its manufacturing method and adapter plate provided by the present disclosure, the pre-prepared conductive structure is cooled and fixed by using molten glass dielectric material, which can avoid the problems of voids and uneven filling during the process of filling the electroplated metal, and simplify the manufacturing process. On the other hand, the glass dielectric layer makes the adhesion between the conductive structure and the glass substrate stronger, which is conducive to improving the process yield. In addition, for the preparation of glass through holes with a high depth-to-width ratio, filling the electroplated metal is more prone to voids and unevenness, and the present disclosure has more advantages because the conductive structure is prepared in advance.

[0098] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0099] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: Glass substrate; A conductive structure extending through the glass substrate; A glass dielectric layer, located between the glass substrate and the conductive structure; The melting point of the glass substrate is higher than the melting point of the glass dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The glass substrate and / or the glass dielectric layer may be made of silicate glass.

3. The semiconductor structure according to claim 1, characterized in that: The conductive structure comprises: A conductive column, passing through the glass substrate; The barrier layer is located between the conductive pillar and the glass dielectric layer.

4. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: providing a glass substrate, the glass substrate comprising a hole extending in a thickness direction; Filling the hole with molten glass dielectric material; the melting point of the glass substrate is higher than the melting point of the glass dielectric material; placing a conductive structure in the hole; wherein the glass dielectric material between the glass substrate and the conductive structure solidifies to form a glass dielectric layer; The glass substrate is thinned so that two ends of the conductive structure are exposed from two sides of the glass substrate respectively.

5. The manufacturing method according to claim 4, characterized in that: The material of the glass substrate and / or the glass medium material includes silicate glass.

6. The manufacturing method according to claim 4, characterized in that: Providing a glass substrate comprises: providing an initial glass substrate; A blind hole extending in a thickness direction is formed in the initial glass substrate.

7. The manufacturing method according to claim 6, characterized in that: The manufacturing method further comprises: forming the conductive structure on a carrier; Placing the conductive structure in the hole comprises: The conductive structure on the carrier is placed in the blind hole on the glass substrate, so that an end of the conductive structure away from the carrier is spaced a preset distance from the bottom of the blind hole.

8. The manufacturing method according to claim 7, characterized in that: The glass substrate comprises a first surface and a second surface opposite to each other, the blind hole is exposed from the first surface; and thinning the glass substrate so that two ends of the conductive structure are exposed from two sides of the glass substrate respectively, comprises: removing the carrier plate; forming a dielectric layer covering the conductive structure on the first surface; removing the dielectric layer and a portion of the conductive structure above the first surface to expose one end of the conductive structure; A portion of the glass substrate is removed from the second surface to expose the other end of the conductive structure.

9. The manufacturing method according to claim 7, characterized in that: The step of forming the conductive structure on the carrier includes: forming a conductive column on the carrier; A barrier layer is formed covering the conductive pillar.

10. An adapter plate, characterized in that: The interposer includes a semiconductor structure formed by the manufacturing method according to any one of claims 4 to 9.

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