Wireless power-enabled receive circuit

Abstract

The application discloses a wireless energy supply receiving circuit and relates to the technical field of integrated circuits, which comprises an active rectifier, two adaptive voltage feedback circuits and two hybrid gate control circuits, wherein the input end of the active rectifier is connected with two ends of a receiving coil on a body chip; the active rectifier comprises a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2; the input end of each adaptive voltage feedback circuit is connected with the gate of the NMOS power tube NM1 or NM2; and each hybrid gate control circuit comprises a common-gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit. The application is a complete implant, does not need an additional battery for power supply, greatly saves the volume of the implant, and brings smaller physical burden to a patient.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wireless power supply receiving circuit. Background Art

[0002] Over the past few decades, with the rapid development of semiconductor technology and wireless technology, as well as the emergence of emerging technologies and concepts such as the Internet of Things, big data, and artificial intelligence, implantable medical devices have gradually entered people's field of vision and played a huge role. In the application of invasive brain-computer interfaces, it is only necessary to implant a highly integrated medical device into the body, and the electrical signals generated by the brain can be monitored and utilized through the chip. At present, most implantable medical devices are driven by batteries with limited lifespans (i.e., the energy supply is active), and the batteries must be replaced regularly or the batteries integrated in the implanted devices must be wirelessly charged. Such devices are too large and will impose a burden on the patient's body and finances. Summary of the Invention

[0003] Based on the above-mentioned defects of the existing technology, the present invention provides a wireless energy supply receiving circuit, which solves the problem that the existing implantable medical devices are too large and will bring physical and financial burdens to patients.

[0004] The present invention adopts the following technical solutions:

[0005] The present invention provides a wireless energy supply receiving circuit, comprising:

[0006] The active rectifier has its input end connected to the two ends of the receiving coil L2 on the chip inside the body. The active rectifier includes a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2. The drains of the NMOS power tubes NM1 and NM2 are respectively used to receive the AC input signal V WP and V WN The source of the PMOS power tube is used to generate a DC voltage V REC ;

[0007] Two adaptive voltage feedback circuits, whose input terminals are connected to the gates of NMOS power tubes NM1 and NM2 respectively, adjust V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB ON and the feedback voltage V at the turn-off time FB OFF ;

[0008] Two hybrid gate control circuits, each of which comprises a common-gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit; the common-gate comparator is used for receiving V FB_ON , and generating a delay when NMOS power tubes NM1 and NM2 are turned on according to a comparison between V FB_ON and a corresponding V WP or V WN , the delay being connected to a set end of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay chain circuit is used for receiving V FB_OFF , and generating a delay when NMOS power tubes NM1 and NM2 are turned off according to a comparison between V FB_OFF and a corresponding V GP or V GN , the delay being connected to a reset end of the first SR latch; an output end of the first SR latch drives gate voltages V GP and V GN of the NMOS power tubes NM1 and NM2 after passing through the driving circuit.

[0009] Preferably, the receiving coil L2 is used for receiving an alternating current signal transmitted by an external wireless function transmitting circuit, the wireless function transmitting circuit comprising an MCU, a power amplifier and an LC network, the power amplifier transmitting the alternating current signal under the control of the MCU, and the alternating current signal being coupled to the receiving coil L2 on the in-vivo chip through a transmitting coil L1 of the LC network.

[0010] Preferably, the drains of the two PMOS power tubes are respectively connected to the drains of the NMOS power tubes NM1 and NM2, the gates are respectively connected to the drains of the NMOS power tubes NM1 and NM2 after being crossed, and the sources of the NMOS power tubes NM1 and NM2 are grounded.

[0011] Preferably, each of the adaptive voltage feedback circuits comprises a sample-and-hold circuit, a level shifter, a window voltage comparator and an integrator; the sample-and-hold circuit comprises a switched-capacitor circuit, a rising edge pulse generator, a falling edge pulse generator and a second SR latch, a timing control voltage being generated after the gate voltages of the NMOS power tubes NM1 and NM2 pass through the pulse generators and the second SR latch, the output of the second SR latch being connected to and controlling the switches of the switched-capacitor circuit, the input of the switched-capacitor circuit being connected to receive the voltage across the receiving coil, and the voltage across the receiving coil being sampled and held according to the timing change; the output of the sample-and-hold circuit is connected to the input of the level shifter; the level shifter is composed of four PMOS source followers, and its output is connected to the input of the window comparator; the window comparator is composed of two open-loop error amplifiers, and its output is connected to the input of the integrator; the integrator is composed of a PMOS tube, an NMOS tube, a current source and a load capacitor, and its output is connected to the hybrid gate control circuit as the output of the adaptive feedback circuit.

[0012] Preferably, the positive input end of the common-gate comparator is used for receiving VFB_ON , the negative input end is connected with corresponding V WP or V WN , the output end is connected with one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected with the setting end of the first SR latch; one end of the voltage-controlled delay circuit is also used for receiving V FB_OFF , and the other end is connected with the resetting end of the first SR latch; the output end of the driving circuit is connected with the gate of the NMOS power tube NM1 or NM2.

[0013] Preferably, the output end of the active rectifier is connected in parallel with a load capacitor C L and load resistors R1 and R2; one end of the load capacitor C L is connected with the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected with the source of the PMOS power tube, and the other end is grounded.

[0014] Preferably, the wireless energy supply receiving circuit further comprises a load power detection and modulation circuit, which comprises a resistor R3, a load power detection tube N OVP , an error amplifier and an analog-to-digital converter; one end of the resistor R3 is connected with the source of the PMOS power tube, and the other end is connected with the drain V OVP of the load power detection tube N OVP ; the positive input end of the error amplifier is connected between the load resistors R1 and R2, and the negative input end is connected on the reference voltage V ref ; the source of the load power detection tube N OVP is grounded, the gate is connected with the output end of the error amplifier, the drain is connected with the output of the active rectifier and the input of the analog-to-digital converter, and the output D OUT of the analog-to-digital converter is used for reflecting the change of the load power and feeding back to the MCU of the wireless energy supply transmitting circuit to generate corresponding logical output to control the output power of the power amplifier.

[0015] Compared with the prior art, the above-mentioned at least one technical scheme of the present application can achieve the following beneficial effects:

[0016] The wireless energy receiving circuit of the present invention is a receiving end of a single-coil wireless power transmission circuit. The circuit comprises an active rectifier, an adaptive voltage feedback circuit, and a hybrid gate control circuit. The circuit receives an AC input signal from an external chip via the single coil and feeds the AC input signal into the active rectifier, which comprises a cross-coupled PMOS power transistor and NMOS power transistors NM1 and NM2. The gate voltages of the NMOS power transistors NM1 and NM2 are fed into the adaptive voltage feedback circuit, which controls the timing of the circuit to sample the AC input signal and generate turn-on and turn-off feedback voltages. These turn-on and turn-off feedback voltages are then fed into the hybrid gate control circuit to drive the gate voltages of the NMOS power transistors NM1 and NM2 in the active rectifier. Ultimately, a DC voltage is output via the PMOS power transistors of the active rectifier. The present invention is a complete implant that does not require an additional battery, significantly reducing the size of the implant and placing less physical burden on the patient. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of an application environment of a wireless energy supply receiving circuit of the present invention;

[0019] Figure 2 This is a transistor-level schematic diagram of a wireless energy receiving circuit of the present invention;

[0020] Figure 3 The hybrid gate control circuit and adaptive voltage feedback circuit schematic and timing diagram of the present invention;

[0021] Figure 4 is a circuit schematic diagram of the level shift circuit of the present invention;

[0022] Figure 5 is a circuit diagram of a window voltage comparator of the present invention;

[0023] Figure 6 is a circuit diagram of an integrator of the present invention;

[0024] Figure 7 is a transistor-level circuit diagram of a common-gate comparator of the present invention;

[0025] Figure 8 This is a transistor-level circuit diagram of the voltage-controlled delay circuit of the present invention. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] In order to solve the deficiencies of the prior art, the present invention provides a wireless energy supply receiving circuit.

[0028] like Figure 1 As shown, this embodiment provides a wireless power supply circuit for an invasive brain-computer interface and its application environment. The user controls the first MCU in the external chip to control the power amplifier to transmit the signal. The AC signal passing through the LC network is coupled to the receiving coil L2 on the internal chip through the transmitting coil L1, and the signal V at both ends of the receiving coil is WP and V WN This is the AC input signal of the present invention, which includes an adaptively regulated active rectifier (composed of an active rectifier, two hybrid gate control circuits, and two adaptive voltage feedback circuits) and a load power detection and modulation circuit. WP and V WN After processing, it is converted into a DC output signal V REC The structures of the two hybrid gate control circuits are identical and symmetrical to each other, and the structures of the two adaptive voltage feedback circuits are identical and symmetrical to each other.

[0029] Furthermore, to further explain the working principle of the wireless power supply receiving circuit in detail, Figure 2 The transistor-level schematic diagram of the wireless power supply receiving circuit used in invasive brain-computer interfaces is shown. The active rectifier input is connected to the two ends of the receiving coil L2 on the chip inside the body. It includes a pair of cross-coupled PMOS power transistors and NMOS power transistors NM1 and NM2. The drains of the NMOS power transistors NM1 and NM2 are used to receive the AC input signal V WP and V WN , the source of the PMOS power tube is used to generate a DC voltage V REC The gate voltage of NMOS power tubes NM1 and NM2 is V GP and V GN As the input of the adaptive voltage feedback circuit, it controls the sampling timing and samples the other two inputs VWP and VWN.

[0030] Reference Figure 2The input terminals of the two adaptive voltage feedback circuits are connected to the gates of the NMOS power tubes NM1 and NM2 respectively. The gate voltages of NM1 and NM2 are used to adjust the voltage of V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB_ON and the feedback voltage V at the turn-off time FB_OFF .

[0031] The adaptive voltage feedback circuit generates the feedback voltage V at the turn-on time. FB_ON , determines the comparator's discrimination level to compensate for the transmission delay during the conduction process; the feedback voltage V at the turn-off time FB_OFF Determines how long the rising edge of the comparator is delayed, controls the first SR latch to output a low level, and turns off the NMOS power tube. For the conduction process, when the active diode is turned on ahead of the ideal conduction time, the V generated by the adaptive feedback circuit FB_ON When the comparator starts comparing later, the turn-on time of the active diode is delayed, and the turn-on time of the active diode is gradually approaching the ideal turn-on time. When the active diode is turned on later than the ideal turn-on time, V FB_ON When the active diode turns off earlier than the ideal turn-off time, the V generated by the adaptive feedback circuit FB_OFF As V increases, the voltage-controlled delay circuit delay increases, and the turn-off time of the active diode is delayed, approaching the ideal turn-off time. When the active diode turns off later than the ideal turn-off time, V FB_OFF The hybrid delayed gate voltage control structure avoids the problem of multiple pulses and can establish stability in a shorter time.

[0032] During the turn-on process, the rising edge detection circuit generates a pulse after detecting the rising edge of the comparator, controlling the first SR latch to output a high level, turning on the NMOS power tube. During the turn-off process, the rising edge of the comparator is delayed by the voltage-controlled delay circuit, causing the first SR latch to output a low level, turning off the NMOS power tube. Therefore, the rising edge of the comparator determines the turn-on time, while the delay generated by the voltage-controlled delay circuit determines the turn-off time.

[0033] Each hybrid gate control circuit includes a common gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit; the common gate comparator is used to receive V FB_ON , according to V FB_ON With the corresponding V WP or V WN The comparison generates the delay when the NMOS power tubes NM1 and NM2 are turned on. The delay is connected to the set terminal of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay chain circuit is used to receive VFB_OFF , according to V FB_OFF Generate a delay when the NMOS power tubes NM1 and NM2 are turned off, and the delay is connected to the reset terminal of the first SR latch; the output terminal of the first SR latch drives the gate voltage V of the NMOS power tubes NM1 and NM2 after passing through the driving circuit GP and V GN The common gate comparator’s discrimination level and the delay of the voltage-controlled delay circuit are adjusted by adaptive feedback voltage. The positive input of the common gate comparator is used to receive V FB_ON , the negative input terminal corresponds to V WP or V WN The output end is connected to one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected to the set end of the first SR latch; one end of the voltage-controlled delay circuit is also used to receive V FB_OFF , and the other end is connected to the reset end of the first SR latch; the output end of the driving circuit is connected to the gate of the NMOS power tube NM1 or NM2.

[0034] Load capacitance C L , load resistors R1 and R2 are connected in parallel at the output of the active rectifier, and load capacitor C L One end is connected to the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected to the source of the PMOS power tube, and the other end is grounded.

[0035] Reference Figure 3-Figure 6 Each adaptive voltage feedback circuit includes a sample-and-hold circuit, a level shifter circuit, a window voltage comparator, and an integrator. The sample-and-hold circuit includes a switched capacitor circuit, a rising-edge pulse generator, a falling-edge pulse generator, and a second SR latch. The gate voltages of the NMOS power transistors NM1 and NM2 pass through the pulse generator and the second SR latch to generate a timing control voltage. The output of the second SR latch is connected to and controls the switching of the switched capacitor circuit. The input of the switched capacitor circuit is connected to the two ends of the receiving coil, sampling and holding the voltages at these two ends according to timing changes. The output of the sample-and-hold circuit is connected to the input of the level shifter. The level shifter is composed of four PMOS source followers, whose output is connected to the input of the window comparator. The window comparator is composed of two open-loop error amplifiers, whose output is connected to the input of the integrator. The integrator is composed of a PMOS transistor, an NMOS transistor, a current source, and a load capacitor. Its output is connected to the hybrid gate control circuit as the output of the adaptive feedback circuit.

[0036] In order to show the working sequence of the circuit more clearly, Figure 3 The circuit diagram is simplified and the timing of the circuit is shown. At the turn-on moment of NM1, that is, V GP The rising edge of V WP Sampling, VWP If the actual turn-on time is ahead of the ideal turn-on time, V WP If it is negative, the actual turn-on time is later than the ideal turn-on time. At the turn-off time of NM1, that is, V GP At the falling edge of V WP If it is negative, the actual shutdown time is ahead of the ideal shutdown time, V WP If the actual turn-on time is later than the ideal turn-off time, the turn-on and turn-off time of NM2 can be judged in the same way. GN The rising edge of V WN sampling.

[0037] To V WP Take the sample and hold circuit as an example, Figure 3 As shown, at V GN The falling edge will S ON_P / S OFF_P Open, the voltage on C1 and C2 follows V WP . In V GP The rising edge of S ON_P , C1 upsamples to get V GP V at the rising edge WP Voltage V SH_ON ; In V GP The falling edge turns off S OFF_P , C2 upsamples to get V GP V at the falling edge WP Voltage V SH_OFF In the next cycle V GN When high, open S HOLD_P , C1 and C3 share the charge, and the sampled voltage at the turn-on time is stored in C3; C2 and C4 share the charge, and the sampled voltage at the turn-off time is stored in C4. Similarly, we can get V WN The sample and hold circuit logic.

[0038] In V GP / V GN V sampled along the rising and falling edges SH_ON / V SH_OFF The voltages are all close to zero, and the comparator cannot be used to directly determine the magnitude relationship with the zero level. A level shift circuit is needed to move the sampling level and the zero level to the appropriate common mode. The structure of the level shift circuit is as follows: Figure 4 As shown. Under the same current bias, the 0 level is passed through a large-size source follower input tube to generate V L ; Then use a small size source follower input tube to generate V H ; V SH_ON / V SH_OFF Get V through an input tube of intermediate size LS_ON / V LS_OFF, by adjusting the input tube size, set a reasonable V H With V L Interval: If the interval is too small, it is difficult to establish a stable feedback loop. If the interval is too large, there will be a large error in the turn-on and turn-off moments, causing the PCE to decrease.

[0039] The window voltage comparator and integrator structures are as follows: Figure 5 and Figure 6 As shown. After level shifting, the sampled voltage is combined with the two window voltages V H / V L By comparing, we can determine whether the turn-on and turn-off moments of the active diode are ahead or behind. Taking the turn-on moment as an example, when V LS_ON In V H and V L In the middle, the active diode is considered to be turned on at the ideal time, and the window comparator outputs V DN / V UP are low level and high level respectively, the capacitor is not charged or discharged, V FB The voltage remains stable. When V LS Greater than V H When the active diode is considered to be turned on ahead of time, the window comparator outputs V DN / V UP Both are high level, the capacitor is discharged, V FB Voltage drops. When V LS Less than V L When the active diode is considered to be turned on with hysteresis, the window comparator outputs V DN / V UP Both are low level, the capacitor is charged, V FB The voltage rises. The integrator generates V FB The voltage is used as the input of the hybrid gate control circuit to control the hybrid gate control circuit to generate compensation delay until V WP / V WN It approaches 0 at the turn-on and turn-off moments, or is controlled within the window voltage.

[0040] The key circuits in the hybrid gate control circuit are the common gate comparator and the voltage-controlled delay circuit. Figure 7 This is the common gate comparator of the present invention. The two sources on the right are V WP or V WN The left source is connected to the V generated by the adaptive feedback circuit. FB_ON , but the feedback voltage has no driving capability, so the leftmost circuit is added to provide a driving capability and the output voltage follows V FB_ON The current flowing through PM1 / PM2 is the same as I. When V W Higher than V FB_ON When V G1 Higher than VG2 , NM4 current is higher than NM2 current, that is, higher than I; NM3 current is lower than NM2 current, that is, lower than I. According to the mirror relationship of the current mirror, PM4 current is lower than I. For NM4 and PM4, NM4 is a strong current source, so the comparator output V CMP_OUT V FB_ON , after passing through the buffer, the output is low level; similarly, when V W Lower than V FB_ON When V FB_ON The comparator's discrimination level can be adjusted by V FB_ON To adjust the comparator comparison time.

[0041] Figure 8 It is a voltage-controlled delay circuit, PM2 is equivalent to V FB_OFF When the comparator level changes from low to high, NM1 is turned off, PM1 is turned on, and the current source charges the capacitor. D After reaching the buffer's flip level, the buffer outputs a high voltage. FB_OFF Adjust the current source current to adjust the delay.

[0042] Refer again Figure 1 , the load power detection and modulation circuit detects the voltage V on the load resistor R2 OVP , the detected data D OUT The data is transmitted to the second MCU and controls the transistor M after passing through the uplink data modulator. L The rectifier input is short-circuited. At this time, the change in reflected impedance will cause the current of the transmitting coil L1 to increase rapidly, resulting in an increase in the swing of the AC signal on the transmitting coil L1. The signal will be filtered and rectified in the uplink data demodulator to obtain an average value. Once this average value exceeds a certain threshold, it indicates that the power at the load end is too large. Then, a signal is fed back to the first MCU to reduce the transmit power of the power amplifier, thereby regulating the load power and saving energy.

[0043] Conventional active rectifiers can only achieve high power conversion efficiency under specific load conditions. Once the load changes, the circuit's operating conditions will also change. Therefore, the present invention uses a load power detection and modulation circuit to achieve high-efficiency operation under different load conditions. This circuit can adaptively adjust the active rectifier through a hybrid gate-controlled circuit, achieving a power conversion efficiency of 94%. Simultaneously, the detected load power data is fed back to the wireless power transmitter, achieving energy conservation through transmitter power regulation. Furthermore, this circuit can be combined with related communication circuits to achieve a perfect combination of wireless power supply and communication.

[0044] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0045] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A wireless power supply receiving circuit, characterized in that: include: The active rectifier has its input end connected to the two ends of the receiving coil L2 on the chip inside the body. The active rectifier includes a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2. The drains of the NMOS power tubes NM1 and NM2 are respectively used to receive the AC input signal V WP and V WN The source of the PMOS power tube is used to generate a DC voltage V REC ; Two adaptive voltage feedback circuits, whose input terminals are connected to the gates of NMOS power tubes NM1 and NM2 respectively, adjust V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB_ON and the feedback voltage V at the turn-off time FB_OFF ; Two hybrid gate control circuits, each hybrid gate control circuit includes a common gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit; the common gate comparator is used to receive V FB_ON , according to V FB_ON With the corresponding V WP or V WN Comparison generates the delay when the NMOS power tubes NM1 and NM2 are turned on. The delay is connected to the set end of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay circuit is used to receive V FB_OFF , according to V FB_OFF Generate a delay when the NMOS power tubes NM1 and NM2 are turned off, and the delay is connected to the reset terminal of the first SR latch; the output terminal of the first SR latch drives the gate voltage V of the NMOS power tubes NM1 and NM2 after passing through the driving circuit GP and V GN ; Each of the adaptive voltage feedback circuits includes a sampling and holding circuit, a level shifting circuit, a window voltage comparator and an integrator; the sampling and holding circuit includes a switched capacitor circuit, a rising edge pulse generator, a falling edge pulse generator and a second SR latch; the gate voltages of the NMOS power tubes NM1 and NM2 generate a timing control voltage after passing through the pulse generator and the second SR latch; the output of the second SR latch is connected to and controls the switch of the switched capacitor circuit; the input of the switched capacitor circuit is connected to the two ends of the receiving coil, and the voltages at these two ends are sampled and held according to the timing changes; the output of the sampling and holding circuit is connected to the input of the level shifter; the level shifter is composed of four PMOS source followers, and its output is connected to the input of the window comparator; the window comparator is composed of two open-loop error amplifiers, and its output is connected to the input of the integrator; the integrator is composed of a PMOS tube, an NMOS tube, a current source and a load capacitor, and its output is connected to the hybrid gate control circuit as the output of the adaptive feedback circuit.

2. The wireless power supply receiving circuit according to claim 1, wherein: The receiving coil L2 is used to receive the AC signal transmitted by the wireless function transmitting circuit outside the body. The wireless function transmitting circuit includes an MCU, a power amplifier and an LC network. The MCU controls the power amplifier to transmit the AC signal, and the AC signal is coupled to the receiving coil L2 on the chip inside the body through the transmitting coil L1 of the LC network.

3. The wireless power supply receiving circuit according to claim 1, wherein: The drains of the two PMOS power tubes are connected to the drains of the NMOS power tubes NM1 and NM2 respectively, and the gates are connected to the drains of the NMOS power tubes NM1 and NM2 respectively after crossing. The sources of the NMOS power tubes NM1 and NM2 are grounded.

4. The wireless power supply receiving circuit according to claim 1, wherein: The positive input of the common-gate comparator is used to receive V FB_ON , the negative input terminal corresponds to V WP or V WN The output end is connected to one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected to the set end of the first SR latch; one end of the voltage-controlled delay circuit is also used to receive V FB_OFF , and the other end is connected to the reset end of the first SR latch; the output end of the driving circuit is connected to the gate of the NMOS power tube NM1 or NM2.

5. The wireless power supply receiving circuit according to claim 2, wherein: The output end of the active rectifier is connected in parallel with a load capacitor C L As well as the load resistors R1 and R2, the load capacitor C L One end is connected to the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected to the source of the PMOS power tube, and the other end is grounded.

6. The wireless power supply receiving circuit according to claim 5, characterized in that: The wireless power supply receiving circuit also includes a load power detection and modulation circuit, and the load power detection and modulation circuit includes a resistor R3, a load power detection tube N OVP , error amplifier and analog-to-digital converter, one end of the resistor R3 is connected to the source of the PMOS power tube, and the other end is connected to the load power detection tube N OVP The drain terminal V OVP Connection; the positive input of the error amplifier is connected between the load resistors R1 and R2, and the negative input is connected to the reference voltage V ref The load power detection tube N OVP The source is grounded, the gate is connected to the output of the error amplifier, the drain and the output of the active rectifier are connected to the input of the analog-to-digital converter, and the output of the analog-to-digital converter D OUT , which is used to reflect the change of load power and feed back to the MCU of the wireless power supply transmission circuit to generate corresponding logic output to control the output power of the power amplifier.

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