Zero-voltage starting control module, driving circuit and active clamping converter

Abstract

The invention provides a zero-voltage starting control module, a driving circuit and an active clamping converter, and the module comprises a timing unit which carries out the timing of a first time length; the time length acquisition unit is used for acquiring the time length from the turn-off of the clamping tube to the complete release of the secondary inductive current of the transformer to obtain a second time length; the comparison unit is used for comparing the first duration with the second duration; and the dead time adjusting unit is used for adjusting the conduction time and the first duration of the clamping tube in the next period based on the comparison result of the current period so as to realize self-adaptive zero-voltage starting control. The circuit is realized by adopting a digital circuit, accurate control can be realized, the control range is relatively wide, zero-voltage conduction control is dynamically realized, the system efficiency is improved, the use of a capacitor in an analog circuit is reduced, and the area cost of a chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a zero voltage turn-on control module, a drive circuit and an active clamping converter. Background Art

[0002] The current energy shortage drives the electronic technology to continue to develop. How to further reduce the power consumption of electronic equipment has always been the mission of electronic design engineers. In recent years, flyback converters, which have advantages in volume cost and high reliability, have been well developed. Among them, active clamp converters (such as active clamp flyback converters, Active Clamp Flyback, ACF) use active components to recover (absorb) the energy in the transformer leakage inductance through a resonant process. Compared with traditional RCD clamp converters and LCD clamp converters, active clamp converters can meet the ZVS requirements of the primary power tube. Therefore, the switching frequency is higher and the efficiency is higher. They are widely used in the field of power isolation conversion.

[0003] In the prior art, analog circuits are mostly used to adjust the dead time between the clamp tube and the main switch tube, which cannot accurately control the dead time. At the same time, the adjustable range is too narrow, and zero voltage conduction control in the full load range cannot be achieved. There are disadvantages such as more main switch tube losses and low system efficiency. Some circuit control schemes also affect system stability and do not have good applicability. At present, there is a scheme that determines whether the zero voltage turn-on of the main switch tube is achieved by reusing the auxiliary winding voltage sampling pin. It is necessary to design a forward counter and a reversible counter inside the circuit. The circuit structure is complex, which is not conducive to the preparation of integrated circuits and the requirements of miniaturization and low cost.

[0004] Therefore, how to improve the accuracy of zero-voltage turn-on control of the main switch tube, reduce costs, and reduce circuit area has become one of the problems that technical personnel in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a zero voltage turn-on control module, a drive circuit and an active clamp converter to solve the problems of poor accuracy, complex circuit structure and high cost in adjusting the dead time of analog circuits in the prior art.

[0007] To achieve the above objectives and other related objectives, the present invention provides an adaptive zero voltage turn-on control module, which is applied to an active clamp converter. The adaptive zero voltage turn-on control module at least includes:

[0008] Timing unit, duration acquisition unit, comparison unit and dead time adjustment unit;

[0009] The timing unit is connected to the output end of the dead time adjustment unit, and counts the first duration provided by the dead time adjustment unit, wherein the first duration is a preset dead time duration between the closing of the clamping tube and the opening of the main switch tube in the active clamping converter;

[0010] The duration acquisition unit acquires the duration from when the clamping tube in the active clamping converter is turned off to when the secondary inductance current of the transformer is completely released, to obtain a second duration;

[0011] The comparison unit is connected to the output end of the timing unit and the duration acquisition unit, and compares the first duration with the second duration;

[0012] The dead time adjustment unit is connected to the output end of the comparison unit, and adjusts the conduction time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control; when the first duration is greater than the second duration, the conduction time of the clamp tube is reduced by a preset duration; when the first duration is less than the second duration, the conduction time of the clamp tube is increased by a preset duration; when the first duration is equal to the second duration, the conduction time of the clamp tube remains unchanged.

[0013] Optionally, the timing unit includes a timer, which starts timing from when the clamp tube is turned off and outputs a timing end signal when the timing reaches the first time length.

[0014] Optionally, the duration acquisition unit includes a controller, a frequency divider and a counter;

[0015] The controller receives the driving signal and the zero current detection signal of the clamp tube, triggers the timing start signal when the clamp tube is turned off, and triggers the timing end signal when the zero current detection signal is valid;

[0016] The frequency divider is connected to the output end of the controller and receives the working clock. When the timing start signal is valid, the working clock is divided into two parts in sequence. i times the frequency to obtain a counting clock; wherein i=1, 2...n, n is the number of bits of the output signal of the duration acquisition unit, and is set to a natural number greater than 2;

[0017] The counter is connected to the output end of the controller and the frequency divider, and performs timing based on the counting clock when the timing start signal is valid, and stops timing when the timing end signal is valid.

[0018] More optionally, the controller is implemented using an RS trigger, a set end of the RS trigger is connected to the drive signal of the clamp tube, a reset end is connected to the zero current detection signal, and a control signal for timing start and end is output.

[0019] More optionally, the frequency divider includes n stages of D flip-flops cascaded in sequence, the data input terminal of each D flip-flop is connected to the inverting output terminal, and the non-phase output terminal outputs the frequency division signal; the clock terminal of the first stage D flip-flop is connected to the working clock, and the clock terminal of the subsequent stage D flip-flop is connected to the inverting output terminal of the previous stage D flip-flop; the asynchronous reset terminal of the first stage D flip-flop is connected to the output terminal of the controller, and the asynchronous reset terminals of the second to nth stage D flip-flops are connected to the inverting signal of the zero current detection signal.

[0020] More optionally, the counter comprises n stages of D flip-flops cascaded in sequence, the asynchronous reset terminal of each D flip-flop is connected to the delayed signal of the controller output signal, and the clock terminal of the i-th stage D flip-flop is connected to 2 i A counting clock with a multiple frequency; the data input terminal of the first-stage D-type flip-flop is connected to a preset voltage, and the data input terminal of the subsequent-stage D-type flip-flop is connected to the positive-phase output terminal of the previous-stage D-type flip-flop; and the negative-phase output terminal of each D-type flip-flop outputs the timing result.

[0021] More optionally, the comparison unit includes n comparison sub-units, each comparison sub-unit includes an XOR gate, a first NAND gate, a second NAND gate and a third NAND gate;

[0022] The input ends of the XOR gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the timer; the input ends of the first NAND gate are respectively connected to the corresponding bit output signal of the timer and the output signal of the XOR gate, and output a first comparison result; the input ends of the second NAND gate are respectively connected to the output signal of the timing unit and the output signal of the XOR gate, and output a second comparison result; the input ends of the third NAND gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the timer, and output a third comparison result.

[0023] More optionally, the dead time adjustment unit includes a time adjustment subunit and n control subunits;

[0024] Each control subunit is connected to the output end of each comparison subunit in a one-to-one correspondence, and each adjustment subunit includes a first enabling tube, a second enabling tube, a third enabling tube, a first transistor, a second transistor and a third transistor; one end of each enabling tube is connected to a preset voltage, and the other end is connected to the control end of the corresponding transistor. When the enable signal is invalid, each enabling tube is turned on to control each transistor to be turned off respectively; one end of the first transistor is connected to the preset voltage, and the other end generates a control signal for reducing the conduction time of the clamping tube, and the control end is connected to the corresponding first comparison result; one end of the second transistor is connected to the preset voltage, and the other end generates a control signal for increasing the conduction time of the clamping tube, and the control end is connected to the corresponding second comparison result; one end of the third transistor is connected to the preset voltage, and the other end generates a control signal for maintaining the conduction time of the clamping tube, and the control end is connected to the corresponding third comparison result;

[0025] The time adjustment subunit is connected to the output end of each control subunit and receives a working clock. It uses the working clock to generate a counting time according to a control signal output by each control subunit, thereby adjusting the conduction time of the clamp tube.

[0026] In order to achieve the above-mentioned object and other related objects, the present invention further provides a driving circuit, wherein the driving circuit at least comprises:

[0027] Logic control module, power-on reset module and the above-mentioned adaptive zero voltage turn-on control module;

[0028] The adaptive zero voltage turn-on control module generates and adjusts the dead time between the closing of the clamp tube and the opening of the main switch tube in the next cycle based on the driving signal of the clamp tube and the zero current detection signal;

[0029] The power-on reset module is used to reset the logic control module when the active clamp converter is powered on;

[0030] The logic control module is connected to the output ends of the adaptive zero voltage turn-on control module and the power-on reset module, and receives the zero voltage detection signal and the output current sampling signal of the active clamp converter, so as to generate the driving signals of the clamp tube and the main switch tube.

[0031] Optionally, the driving circuit further includes an oscillator, which provides a working clock for the driving circuit.

[0032] To achieve the above-mentioned object and other related objects, the present invention further provides an active clamped converter, the active clamped converter at least comprising:

[0033] Active clamping conversion circuit and the above driving circuit;

[0034] The driving circuit obtains a feedback signal from the active clamping conversion circuit, and generates driving signals for the clamping tube and the main switch tube based on the feedback signal;

[0035] The active clamp conversion circuit converts an input voltage into an output voltage based on control of the drive circuit.

[0036] As described above, the zero voltage turn-on control module, drive circuit and active clamp converter of the present invention have the following beneficial effects:

[0037] 1. The zero voltage turn-on control module, drive circuit and active clamp converter of the present invention realize zero voltage adaptive control of the main switch tube by introducing dynamic dead time adjustment control technology, so that the system can quickly reach the optimal working state, reduce the switching loss of the main switch tube, and better improve the efficiency of the active clamp converter.

[0038] 2. The zero voltage turn-on control module, drive circuit and active clamp converter of the present invention use digital circuits to adjust the dead time between the clamp tube and the main switch tube, which can avoid the use of large capacitors in analog circuits, thereby greatly reducing circuit size and reducing costs.

[0039] 3. The zero voltage start-up control module of the present invention is implemented by a digital circuit, which has a simple circuit structure, high accuracy, and no effect on system stability.

[0040] 4. The zero voltage turn-on control module, drive circuit and active clamp converter of the present invention can realize zero voltage turn-on control in the full load range, can operate in a higher frequency range, and further improve the efficiency of the system. At the same time, the circuit has good portability and meets the application scenarios of ordinary Si tubes and third-generation semiconductor GaN. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Shown is the control operation waveform of the active clamp flyback converter.

[0042] Figure 2 Shown is a structural schematic diagram of the adaptive zero voltage turn-on control module of the present invention.

[0043] Figure 3 Shown is a specific circuit diagram of the adaptive zero voltage turn-on control module of the present invention.

[0044] Figure 4 Shown is a schematic structural diagram of the driving circuit of the present invention.

[0045] Figure 5 Shown is a schematic structural diagram of the active clamping converter of the present invention.

[0046] Component number description

[0047] 1. Driving circuit

[0048] 11 Adaptive zero voltage start control module

[0049] 111 Timing Unit

[0050] 112 Duration Collection Unit

[0051] 112a Controller

[0052] 112b Crossover

[0053] 112c Counter

[0054] 113 Comparison unit

[0055] 113a Comparison subunit

[0056] 114 Dead time adjustment unit

[0057] 114a Adjustment subunit

[0058] 12 Power-on reset module

[0059] 13 Logic Control Module

[0060] 14 Oscillator

[0061] 2 Active clamp conversion circuit

[0062] 21 Voltage input module

[0063] 22 Output Module

[0064] 23. Zero current detection module DETAILED DESCRIPTION

[0065] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] See also Figure 1 to Figure 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0067] Taking the active clamp flyback converter as an example, in order to realize the zero voltage turn-on control of the main switch tube in the active clamp flyback converter, a control mode of complementary turn-on of the main switch tube and the clamp tube is usually adopted; Figure 1 The figure shows the control operation waveform of the active clamp flyback converter, where V DS is the drain-source voltage of the main switch tube, PWM_C is the driving signal of the clamp tube, PWM_P is the driving signal of the main switch tube, i m is the transformer primary inductor current. In the active clamp flyback converter, the main switch tube can be set according to its drain-source voltage V DS The output power is turned on and off. After the main switch is turned on, the transformer primary inductor current i m It increases linearly (at this time, the transformer primary inductor current flows through the main switch tube, recorded as I P ); When the output current sampling signal reaches the preset reference value (the preset reference value is adjustable, and different values ​​correspond to different stages), the control system turns off the main switch tube, and the energy stored in the primary inductance of the transformer is instantly coupled to the secondary side. At the same time, the clamping tube is turned off after a delay T after the main switch tube is turned off. DP_C Then turn on (at this time, the primary inductor current of the transformer flows through the clamp tube, recorded as i clamp ; The drain-source voltage V of the main switch tube N0 DS =Vin+mVo, where Vin is the input voltage, Vo is the output voltage, and m is the turns ratio of the primary winding to the secondary winding in the transformer. After the clamp tube is turned on, the energy in the leakage inductance can be recovered through the clamp resistor and the clamp capacitor. Since the clamp tube is turned on, the primary inductance current i m However, due to the parasitic capacitance between the drain and source of the main switch tube, the transformer capacitance, and the secondary rectifier diode capacitance, the transformer primary inductor current i m There will be an increasing process. According to the above analysis, in order to achieve zero voltage turn-on control of the main switch tube, the following zero voltage turn-on conditions need to be met:

[0068]

[0069] Among them, L M is the inductance of the primary side of the transformer, i clamp- Direction and i clamp The specified directions are opposite and the magnitudes are equal; similarly, i m- Direction and i m The specified currents are opposite in direction and equal in magnitude; C eq The drain-source equivalent capacitance of the main switch tube; due to the leakage inductance L Kis very small, and part of the leakage inductance energy has been recovered, so formula (1) no longer considers the leakage inductance energy. From the above formula, it can be seen that the main switch tube drain-source equivalent capacitance C eq , Clamping capacitor C RD And the parasitic capacitance between the drain and source of the clamp tube is discharged until a zero voltage detection signal is detected. Therefore, in order to achieve zero voltage turn-on control, it is necessary to continuously adaptively adjust the opening time of the clamp tube, thereby realizing the adjustment of the dead time between the closing of the clamp tube and the opening of the main switch tube.

[0070] like Figure 2 As shown, the present invention provides an adaptive zero voltage turn-on control module 11, which is applied to an active clamp converter. The adaptive zero voltage turn-on control module 11 includes:

[0071] A timing unit 111 , a duration collecting unit 112 , a comparing unit 113 and a dead time adjusting unit 114 .

[0072] like Figure 2 As shown, the timing unit 111 is connected to the output end of the dead time adjustment unit 114, and times the first time length T1 provided by the dead time adjustment unit 114. The first time length T1 is a preset dead time length between the closing of the clamping tube and the opening of the main switch tube in the active clamping converter.

[0073] Specifically, in the initial state, the timing unit 111 obtains the first duration T1 based on the zero voltage detection signal ZVS. At this time, the first duration T1 is the duration from the clamp tube being turned off to the main switch tube being turned on (actual measurement value). Subsequently, the timing unit 111 obtains the first duration T1 (calculated preset value) that is continuously updated based on the dead time adjustment unit 114. In this embodiment, the timing unit 111 is implemented by a timer, and the count value of the timer is set based on the first duration T1. The timer starts timing from the clamp tube being turned off. When the count value is reached, it is determined that the timing of the first duration T1 is ended, and a corresponding count end signal (for example, high level is valid) is output; as the dead time adjustment unit 114 continuously adjusts the first duration T1, the set count value of the timer is also continuously updated.

[0074] It should be noted that any circuit structure that can time the first duration T1 and output a corresponding signal is applicable to the present invention, and is not limited to this embodiment.

[0075] like Figure 2 As shown, the duration acquisition unit 112 acquires the duration from the closing of the clamping tube in the active clamping converter to the complete release of the secondary inductor current of the transformer to obtain a second duration t2. Figure 3As shown, in this embodiment, the duration acquisition unit 112 includes a controller 112a, a frequency divider 112b and a counter 112c.

[0076] Specifically, Figure 3 As shown, in this embodiment, the controller 112a receives the driving signal PWM_C and the zero current detection signal ZCD of the clamp tube, triggers the timing start signal when the clamp tube is turned off, and triggers the timing end signal when the zero current detection signal ZCD is valid. As an example, the controller 112a is implemented by an RS trigger, the set end s of the RS trigger is connected to the driving signal PWM_C of the clamp tube, the reset end is connected to the zero current detection signal ZCD, and the timing start and end control signals are output. When the driving signal PWM_C of the clamp tube jumps to a low level, the output signal CTR of the RS trigger jumps to a high level (i.e., the timing start signal), and when the zero current detection signal ZCD is valid at a high level, the output signal CTR of the RS trigger jumps to a low level (i.e., the timing end signal); in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0077] Specifically, Figure 3 As shown, in this embodiment, the frequency divider 112b is connected to the output end of the controller 112a and receives the working clock OSC. When the timing start signal is valid, the working clock OSC is divided into two parts in sequence. i times the frequency to obtain a counting clock; wherein, i=1, 2…n, n is the number of bits of the output signal of the duration acquisition unit 112, which is set to a natural number greater than 2. In actual use, the corresponding value can be set as needed. As an example, the frequency divider 112b includes n levels of D flip-flops cascaded in sequence, the data input terminal D of each D flip-flop is connected to the inverting output terminal Q-, and the positive output terminal Q+ outputs the divided frequency signal, wherein the first-level D flip-flop outputs a two-frequency division signal 2clk, the second-level D flip-flop outputs a four-frequency division signal 4clk, and so on, the n-th level D flip-flop outputs 2clk. n Frequency division signal 2 nclk; the clock terminal clk of the first-stage D flip-flop is connected to the working clock OSC, and the clock terminal clk of the subsequent-stage D flip-flop is connected to the inverting output terminal Q- of the previous-stage D flip-flop; the asynchronous reset terminal Clr of the first-stage D flip-flop is connected to the output terminal of the controller 112a, and the asynchronous reset terminal Clr of the second to n-th stage D flip-flops is connected to the inverting signal ZCD_N of the zero current detection signal; when the output signal CTR of the RS flip-flop jumps to a high level and the inverting signal ZCD_N of the zero current detection signal is a high level, the divider 112b starts frequency division; when the output signal CTR of the RS flip-flop jumps to a low level and the inverting signal ZCD_N of the zero current detection signal is a low level, the divider 112b is reset; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0078] Specifically, Figure 3 As shown, in this embodiment, the counter 112c is connected to the output end of the controller 112a and the frequency divider 112b, and when the timing start signal is valid, timing is performed based on the counting clock, and when the timing end signal is valid, timing is stopped. As an example, the counter 112c includes n stages of D flip-flops cascaded in sequence, the asynchronous reset end Clr of each D flip-flop is connected to the delay signal CTR_D of the controller output signal, and the clock end of the i-th stage D flip-flop is connected to 2 i The counting clock with multiple frequency division (that is, the clock end of the first-stage D flip-flop receives the two-frequency division signal 2clk, the clock end of the second-stage D flip-flop receives the four-frequency division signal 4clk, and so on. The clock end of the n-th stage D flip-flop receives the 2 n Frequency division signal 2 n clk); the data input terminal D of the first-stage D flip-flop is connected to the preset voltage LV, and the data input terminal D of the subsequent D flip-flop is connected to the positive phase output terminal Q+ of the previous D flip-flop; the negative phase output terminal Q- of each D flip-flop outputs the timing result, and each D flip-flop outputs a one-bit signal (t 2_DET1 ,t 2_DET2 …t 2_DETn ), the n-bit signal constitutes the timing result (as an example, the high level is valid); when the delay signal CTR_D of the controller output signal jumps to a high level and receives the corresponding counting clock, the counter 112c starts counting; when the delay signal CTR_D of the controller output signal jumps to a low level or does not receive the corresponding counting clock, the counter 112c stops working; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0079] like Figure 2As shown, the comparison unit 113 is connected to the output ends of the timing unit 111 and the duration acquisition unit 112, and compares the first duration T1 with the second duration t2.

[0080] Specifically, Figure 3 As shown, in this embodiment, the comparison unit 113 includes n comparison subunits 113a, each of which includes an XOR gate, a first NAND gate nand1, a second NAND gate nand2, and a third NAND gate nand3. The input end of the XOR gate is connected to the output signal of the timing unit 111 and the corresponding bit output signal of the timer 112c (respectively denoted as t 2_DET1 ,t 2_DET2 …t 2_DETn ), the input ends of the first NAND gate nand1 are respectively connected to the corresponding bit output signal of the timer 112c and the output signal of the XOR gate XOR, and output the first comparison result (respectively recorded as P11, P12...P1n); the input ends of the second NAND gate nand2 are respectively connected to the output signal of the timing unit 111 and the output signal of the XOR gate XOR, and output the second comparison result (respectively recorded as P21, P22...P2n); the input ends of the third NAND gate nand3 are respectively connected to the output signal of the timing unit 111 and the corresponding bit output signal of the timer, and output the third comparison result (respectively recorded as P31, P32...P3n); Among them, when the duration represented by the corresponding bit output signal of the timer 112c is less than the first duration T1, the first comparison result of the corresponding comparison subunit 113a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 112c is greater than the first duration T1, the second comparison result of the corresponding comparison subunit 113a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 112c is equal to the first duration T1, the third comparison result of the corresponding comparison subunit 113a jumps to a low level; in this example, taking the nth comparison unit 113a as an example, the first duration T1 is equal to the nth bit output signal t1 of the timer 112c. 2_DETn The one with high level, that is, the one that arrives first, is the one with shorter time. Combining the comparison results P11, P12...P1n, P21, P22...P2n, P31, P32...P3n, it can be known which one is longer between the first time length T1 and the second time length t2. The corresponding truth table is as follows:

[0081] T1 <![CDATA[t 2_DETn ]]> XOR Output P1n P2n P3n 0 0 0 1 1 1 0 1 1 0 1 1 <![CDATA[T1>t 2_DETn ]]> 1 0 1 1 0 1 <![CDATA[T1<t 2_DETn ]]> 1 1 0 0 0 1 <![CDATA[T1=t 2DETn ]]>

[0082] In actual use, any circuit structure that can compare two signals representing durations and obtain a comparison result is applicable to the present invention, and is not limited to this embodiment.

[0083] like Figure 2 As shown, the dead time adjustment unit 114 is connected to the output end of the comparison unit 113, and adjusts the conduction time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control; when the first duration T1 is greater than the second duration t2, the conduction time T1 of the clamp tube is adjusted. H_ON When the first time length T1 is less than the second time length t2, the conduction time T of the clamping tube is increased. H_ON Increase the preset time length Δt; when the first time length T1 is equal to the second time length t2, the conduction time T of the clamp tube H_ON Remain unchanged.

[0084] Specifically, Figure 3 As shown, in this embodiment, the dead time adjustment unit 114 includes a time adjustment subunit 114b and n control subunits 114a, and each control subunit 114a is connected to the output end of each comparison subunit 113a in a one-to-one correspondence. Each control subunit 114a includes a first enabling transistor M1, a second enabling transistor M2, a third enabling transistor M3, a first transistor M4, a second transistor M5, and a third transistor M6. One end of each enabling transistor is connected to a preset voltage LV, and the other end is connected to the control end of each transistor. When the enable signal T SSE When invalid, each enabling tube is turned on to control each transistor to be turned off; wherein, the first enabling tube M1 is connected to the control end of the first transistor M4, the second enabling tube M2 is connected to the control end of the second transistor M5, and the third enabling tube M3 is connected to the control end of the third transistor M6. As an example, each enabling tube and transistor is a PMOS tube. When the enabling signal T SSE When the enable signal T is changed to low level (invalid), each enable transistor is turned on, so that the control end of each transistor is connected to the preset voltage LV (high level) and turned off. At this time, the dead time adjustment unit 114 does not work; when the enable signal T SSE When it jumps to high level (valid), each enabling tube is turned off, and the control end of each transistor is connected to the corresponding comparison result. At this time, the dead time adjustment unit 114 is in working state. One end of the first transistor M4 is connected to the preset voltage LV, the control end is connected to the corresponding first comparison result, and the other end generates a voltage to reduce the conduction time T of the clamping tube. H_ON One end of the second transistor M5 is connected to the preset voltage LV, the control end is connected to the corresponding second comparison result, and the other end generates a signal to increase the conduction time T of the clamp tube. H_ON One end of the third transistor M6 is connected to the preset voltage LV, the control end is connected to the corresponding third comparison result, and the other end generates a voltage to maintain the clamping tube conduction time TH_ON When the corresponding comparison result jumps to a low level, the corresponding transistor is turned on and a control signal for adjusting the on-time of the clamping tube is output. The time adjustment subunit 114b is connected to the output end of each control subunit 114a, and receives the working clock OSC. According to the control signal output by each control subunit 114a, the working clock OSC is used to generate a counting time, thereby realizing the on-time T of the clamping tube. H_ON adjustments.

[0085] It should be noted that, in this embodiment, when the circuit is in the startup phase, the enable signal T SSE Invalid, the adaptive zero voltage start control module 11 does not work; when the circuit is started, the enable signal T SSE The jump becomes valid, and the adaptive zero voltage turn-on control module 11 starts to work. In addition, any circuit structure that can adjust the conduction time of the clamp tube and the first duration based on the output signal of the comparison unit 113 is applicable to the present invention, and is not limited to this embodiment.

[0086] It should be noted that the preset time length Δt is not greater than the conduction time of the clamp tube. If the accuracy of regulation is to be improved, the preset time length Δt is set to a smaller value. If the efficiency of regulation is to be improved, the preset time length Δt is set to a larger value. The specific value of the preset time length Δt is set according to actual design needs, and can achieve adaptive changes in the dead time of each cycle; as an example, the preset time length Δt is configured to n working clock cycles, where n is a natural number greater than or equal to 1, including but not limited to 1 to 10.

[0087] like Figure 4 As shown, the present invention further provides a driving circuit 1, the driving circuit 1 comprising:

[0088] The adaptive zero voltage turn-on control module 11 , the power-on reset module 12 and the logic control module 13 .

[0089] like Figure 4 As shown, the adaptive zero voltage turn-on control module 11 generates and adjusts the dead time between the closing of the clamp tube and the opening of the main switch tube in the next cycle based on the driving signal PWM_C and the zero current detection signal ZCD of the clamp tube.

[0090] Specifically, the structure and working principle of the adaptive zero voltage turn-on control module 11 are as mentioned above and will not be described in detail here.

[0091] like Figure 4 As shown, the power-on reset module 12 is used to reset the logic control module 13 when the active clamp converter is powered on.

[0092] Specifically, the structure of the power-on reset module 12 is not limited, and any circuit structure that can implement power-on reset is applicable to the present invention.

[0093] like Figure 4 As shown, the logic control module 13 is connected to the output ends of the adaptive zero voltage turn-on control module 11 and the power-on reset module 12, and receives the zero voltage detection signal ZVS and the output current sampling signal Vcs of the active clamp converter, so as to generate the driving signal PWM_C of the clamp tube and the driving signal PWM_P of the main switch tube.

[0094] Specifically, as an example, when the off time of the clamp tube in the current cycle reaches the set first time length T1 and the zero voltage detection signal ZVS is valid, the main switch tube is turned on; when the output current of the active clamp converter reaches the defined threshold value (as an example, in the circuit startup stage, when the output current sampling signal Vcs reaches the overcurrent protection point, it is determined that the output current reaches the defined threshold value; after the circuit is started, when the output current sampling signal Vcs reaches the preset reference value, it is determined that the output current reaches the defined threshold value, at this time, the output current sampling signal Vcs reaches the maximum value; the values ​​of the defined threshold values ​​in the two stages are different and are set as needed), the main switch tube is driven to turn off. After the main switch tube is turned off for the set time length, the clamp tube is turned on; when the conduction time of the clamp tube reaches the time length adjusted by the adaptive zero voltage start control module 11, the clamp tube is turned off. In actual use, the clamp tube and the main switch tube can be switched on and off according to different strategies combined with the feedback signals of the active clamp converter.

[0095] like Figure 4 As shown, as another implementation of the present invention, the driving circuit 1 also includes an oscillator 14, which provides a working clock for the driving circuit 1 (including a clock with at least one frequency, and clocks with different frequencies can meet the needs of different circuits). The purpose of the working clock includes but is not limited to counting, adjusting the conduction time of the clamp tube and adjusting the first duration. The clock signals required in the driving circuit 1 can all be provided by the oscillator 14, which will not be elaborated here.

[0096] like Figure 5 As shown, the present invention also provides an active clamping converter, the active clamping converter comprising:

[0097] Driving circuit 1 and active clamping conversion circuit 2.

[0098] like Figure 5 As shown, the driving circuit 1 obtains a feedback signal from the active clamping conversion circuit, and generates driving signals for the clamping tube and the main switching tube based on the feedback signal.

[0099] Specifically, the feedback signal includes but is not limited to the current sampling signal Vcs of the main switch tube, the zero voltage detection signal ZVS and the zero current detection signal ZCD. Any feedback signal that can be used to control the clamp tube and the main switch tube is applicable to the present invention and will not be described in detail here. The structure and principle of the driving circuit 1 are as mentioned above.

[0100] like Figure 5 As shown, the active clamp conversion circuit 2 converts the input voltage Vin into the output voltage Vo based on the control of the drive circuit 1 .

[0101] Specifically, in this embodiment, the active clamping conversion circuit 2 adopts a flyback topology structure, including a voltage input module 21, a clamping tube Nc, a main switch tube N0, a leakage inductor L K , transformer T, clamping resistor R1, clamping capacitor C RD , sampling resistor Rs, output module 22 and zero current detection module 23. As an example, the clamp tube Nc and the main switch tube N0 use GaN semiconductor power devices. The voltage input module 21 converts the AC voltage AC into a DC input voltage Vin; as an example, the voltage input module 21 includes a rectifier bridge and an input capacitor Ci; one end of the input capacitor Ci is connected to the output end of the rectifier bridge, and the other end is grounded. The leakage inductance L K One end of is connected to the output end of the voltage input module 21, and the other end is connected to the first end of the primary inductor of the transformer T. The second end of the primary inductor of the transformer T is connected to the ground via the main switch tube N0 and the sampling resistor Rs in sequence. The clamping resistor R1 and the clamping capacitor C RD After the parallel connection, one end is connected to the output end of the voltage input module 21, and the other end is connected to the second end of the primary inductor of the transformer T via the clamp tube Nc. The output module 22 is connected to the secondary inductor of the transformer T to generate the output voltage Vo; as an example, the output module 22 includes a diode Do, an output capacitor Co, and a load R L The anode of the diode Do is connected to the first end of the secondary inductor of the transformer T, and the cathode is connected to the second end (grounded) of the secondary inductor of the transformer T via the output capacitor Co; the load R L The zero current detection module 23 realizes zero current detection through the auxiliary inductor to obtain a zero current detection signal ZCD; as an example, the zero current detection module 23 includes a transformer auxiliary winding, voltage-dividing resistors R2 and R3; one end of the transformer auxiliary winding is grounded, and the other end is grounded through the voltage-dividing resistors R2 and R3 in turn; the zero current detection signal ZCD is output between the voltage-dividing resistors R2 and R3.

[0102] It should be noted that the active clamping conversion circuit 2 is not limited to the structure listed in this embodiment, and any active clamping circuit structure is applicable, including but not limited to forward, flyback and other structures. In addition, the active clamping converter of the present invention can realize zero voltage turn-on control without additional components, has a simple structure and a wide range of applications.

[0103] The present invention introduces a dynamic dead time adjustment control technology. After the clamp tube reaches the pre-shutdown time and shuts down, the system turns on the main switch tube when a zero voltage signal is detected, thereby ensuring the zero voltage turn-on of the main power tube. The zero voltage turn-on control module starts working after the clamp tube is turned off, calculates the dead time from the clamp tube being turned off to the primary power tube being turned on, and samples the time from the clamp tube being turned off to the system detecting that the secondary side inductance current of the transformer is completely released. By comparing the two times, the dead time between the clamp tube and the main switch tube in the next cycle is dynamically adjusted, thereby realizing adaptive zero voltage turn-on control of the main switch.

[0104] In summary, the present invention provides a zero voltage turn-on control module, a driving circuit and an active clamping converter, comprising: a timing unit, a duration acquisition unit, a comparison unit and a dead time adjustment unit; the timing unit is connected to the output end of the dead time adjustment unit, and times the first duration provided by the dead time adjustment unit, the first duration being the preset dead time duration between the closing of the clamping tube in the active clamping converter and the opening of the main switch tube; the duration acquisition unit acquires the duration from the closing of the clamping tube in the active clamping converter to the complete release of the secondary inductor current of the transformer, and obtains the second duration; the comparison unit is connected to the output end of the dead time adjustment unit, and the comparison unit is used to calculate the dead time provided by the dead time adjustment unit; the dead time adjustment ... The output end of the timing unit and the duration acquisition unit compares the first duration with the second duration; the dead time adjustment unit is connected to the output end of the comparison unit, and adjusts the conduction time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control; when the first duration is greater than the second duration, the conduction time of the clamp tube is reduced by a preset duration; when the first duration is less than the second duration, the conduction time of the clamp tube is increased by a preset duration; when the first duration is equal to the second duration, the conduction time of the clamp tube remains unchanged. The zero voltage turn-on control module, the drive circuit and the active clamp converter of the present invention use digital circuits to adaptively adjust the dead time between the clamp tube and the main switch tube, with high accuracy and safety, and can realize zero voltage turn-on control in the full load range, with low loss of the main switch tube and high system efficiency; in addition, the circuit structure of the zero voltage turn-on control module of the present invention is simple, which can effectively reduce the area occupied by the chip and reduce the cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An adaptive zero voltage turn-on control module, applied to an active clamping converter, characterized in that: The adaptive zero voltage turn-on control module at least includes: Timing unit, duration acquisition unit, comparison unit and dead time adjustment unit; The timing unit is connected to the output end of the dead time adjustment unit, and counts the first duration provided by the dead time adjustment unit, wherein the first duration is a preset dead time duration between the closing of the clamping tube and the opening of the main switch tube in the active clamping converter; The duration acquisition unit acquires the duration from when the clamping tube in the active clamping converter is turned off to when the secondary inductance current of the transformer is completely released, to obtain a second duration; The comparison unit is connected to the output end of the timing unit and the duration acquisition unit, and compares the first duration with the second duration; The dead time adjustment unit is connected to the output end of the comparison unit, and adjusts the conduction time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control; when the first duration is greater than the second duration, the conduction time of the clamp tube is reduced by a preset duration; when the first duration is less than the second duration, the conduction time of the clamp tube is increased by a preset duration; when the first duration is equal to the second duration, the conduction time of the clamp tube remains unchanged.

2. The adaptive zero voltage turn-on control module according to claim 1, characterized in that: The timing unit includes a timer, which starts timing from when the clamp tube is turned off, and outputs a timing end signal when the timing reaches the first time length.

3. The adaptive zero voltage turn-on control module according to claim 1, characterized in that: The duration acquisition unit includes a controller, a frequency divider and a counter; The controller receives the driving signal and the zero current detection signal of the clamp tube, triggers the timing start signal when the clamp tube is turned off, and triggers the timing end signal when the zero current detection signal is valid; The frequency divider is connected to the output end of the controller and receives the working clock. When the timing start signal is valid, the working clock is divided into two parts in sequence. i times the frequency to obtain a counting clock; wherein i=1, 2...n, n is the number of bits of the output signal of the duration acquisition unit, and is set to a natural number greater than 2; The counter is connected to the output end of the controller and the frequency divider, and performs timing based on the counting clock when the timing start signal is valid, and stops timing when the timing end signal is valid.

4. The adaptive zero voltage turn-on control module according to claim 3, characterized in that: The controller is implemented by an RS trigger, the set end of the RS trigger is connected to the driving signal of the clamp tube, the reset end is connected to the zero current detection signal, and the timing start and end control signals are output.

5. The adaptive zero voltage turn-on control module according to claim 3, characterized in that: The frequency divider includes n stages of D flip-flops cascaded in sequence, the data input end of each D flip-flop is connected to the inverting output end, and the positive output end outputs the frequency division signal; The clock end of the first-stage D flip-flop is connected to the working clock, and the clock end of the subsequent-stage D flip-flop is connected to the inverting output end of the previous-stage D flip-flop; The asynchronous reset terminal of the first-stage D flip-flop is connected to the output terminal of the controller, and the asynchronous reset terminals of the second to n-th-stage D flip-flops are connected to the inverted signal of the zero current detection signal.

6. The adaptive zero voltage turn-on control module according to claim 3, characterized in that: The counter includes n stages of D flip-flops cascaded in sequence, the asynchronous reset terminal of each D flip-flop is connected to the delayed signal of the controller output signal, and the clock terminal of the i-th stage D flip-flop is connected to 2 i A counting clock with a multiple frequency division; the data input terminal of the first-stage D flip-flop is connected to a preset voltage, and the data input terminal of the subsequent-stage D flip-flop is connected to the positive phase output terminal of the previous-stage D flip-flop; The inverting output terminal of each D flip-flop outputs the timing result.

7. The adaptive zero voltage turn-on control module according to claim 3, characterized in that: The comparison unit includes n comparison sub-units, each of which includes an XOR gate, a first NAND gate, a second NAND gate and a third NAND gate; The input ends of the XOR gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the timer; the input ends of the first NAND gate are respectively connected to the corresponding bit output signal of the timer and the output signal of the XOR gate, and output a first comparison result; the input ends of the second NAND gate are respectively connected to the output signal of the timing unit and the output signal of the XOR gate, and output a second comparison result; the input ends of the third NAND gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the timer, and output a third comparison result.

8. The adaptive zero voltage turn-on control module according to claim 7, characterized in that: The dead time adjustment unit includes a time adjustment subunit and n control subunits; Each control subunit is connected to the output end of each comparison subunit in a one-to-one correspondence, and each control subunit includes a first enabling tube, a second enabling tube, a third enabling tube, a first transistor, a second transistor and a third transistor; one end of each enabling tube is connected to a preset voltage, and the other end is connected to the control end of the corresponding transistor, and when the enable signal is invalid, each enabling tube is turned on to control each transistor to be turned off respectively; one end of the first transistor is connected to the preset voltage, and the other end generates a control signal for reducing the conduction time of the clamping tube, and the control end is connected to the corresponding first comparison result; one end of the second transistor is connected to the preset voltage, and the other end generates a control signal for increasing the conduction time of the clamping tube, and the control end is connected to the corresponding second comparison result; one end of the third transistor is connected to the preset voltage, and the other end generates a control signal for maintaining the conduction time of the clamping tube, and the control end is connected to the corresponding third comparison result; The time adjustment subunit is connected to the output end of each control subunit and receives a working clock. It uses the working clock to generate a counting time according to a control signal output by each control subunit, thereby adjusting the conduction time of the clamp tube.

9. A driving circuit, characterized in that: The driving circuit at least comprises: A logic control module, a power-on reset module and an adaptive zero voltage turn-on control module as claimed in any one of claims 1 to 8; The adaptive zero voltage turn-on control module generates and adjusts the dead time between the closing of the clamp tube and the opening of the main switch tube in the next cycle based on the driving signal of the clamp tube and the zero current detection signal; The power-on reset module is used to reset the logic control module when the active clamp converter is powered on; The logic control module is connected to the output ends of the adaptive zero voltage turn-on control module and the power-on reset module, and receives the zero voltage detection signal and the output current sampling signal of the active clamp converter, so as to generate the driving signals of the clamp tube and the main switch tube.

10. The driving circuit according to claim 9, characterized in that: The driving circuit further includes an oscillator, which provides a working clock for the driving circuit.

11. An active clamp converter, characterized in that: The active clamp converter comprises at least: An active clamping conversion circuit and a driving circuit as claimed in claim 9 or 10; The driving circuit obtains a feedback signal from the active clamping conversion circuit, and generates driving signals for the clamping tube and the main switch tube based on the feedback signal; The active clamp conversion circuit converts an input voltage into an output voltage based on control of the drive circuit.

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