Voltage transmission network

Abstract

The voltage transmission network includes a first unity gain amplifier and a second unity gain amplifier disposed in the back-to-back connection structure to receive a first voltage and a second voltage at a first node and a second node, respectively, and output a third voltage at a third node together. The voltage transmission network further comprises a first resistor inserted between the third node and the second node. And a first capacitor interposed between the second node and the DC node.

Description

Technical Field

[0001] The present invention relates generally to voltage delivery, and more particularly to voltage delivery with high accuracy and low noise. Background Art

[0002] Bias is a voltage used to establish the bias conditions of transistors to achieve a specific function. In many applications, the bias is generated by the master circuit and delivered to the slave circuit using a distribution network. The first goal of the delivery network is to have high accuracy so that the DC level of the voltage delivered to the slave circuit is nearly equal to the DC level of the bias. Another goal of the delivery network is to provide noise filtering so that the voltage delivered to the slave circuit has low noise. A common noise filtering method is to use a resistor-capacitor (RC) low-pass filter composed of a series resistor and a shunt capacitor. To ensure low noise, the corner frequency of the resistor-capacitor low-pass filter must be small, where large resistors and large capacitors are necessary. However, large resistors are prone to voltage drops called "IR drops", where a small load current from the slave circuit will cause the DC level of the voltage delivered to the slave circuit to be significantly different from the DC level of the bias. In other words, accuracy is negatively affected. Therefore, the two goals of high accuracy and low noise of the delivery network cannot generally be achieved simultaneously without trade-offs. Summary of the invention

[0003] The purpose of the present invention is to receive a first voltage and output a second voltage, so that the DC level of the second voltage is almost equal to the DC level of the first voltage, and the noise of the second voltage is much smaller than the noise of the first voltage.

[0004] One aspect of the present invention is to provide a voltage transmission network, comprising a first unit gain amplifier and a second unit gain amplifier, a first resistor and a first capacitor. The first unit gain amplifier and the second unit gain amplifier are arranged in a back-to-back connection structure (topology) to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The first resistor is inserted between the third node and the second node. The first capacitor is inserted between the second node and a DC node.

[0005] Another aspect of the present invention is to provide a voltage transmission method, comprising: combining a first unit gain amplifier and a second unit gain amplifier, configured in a back-to-back connection structure, to receive a first voltage at a first node and a second voltage at a second node respectively, and jointly output a third voltage at a third node; combining a first resistor, configured as a series resistor inserted between the third node and the second node; and combining a first capacitor, configured as a shunt capacitor inserted between the second node and the DC node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the following are the descriptions of the accompanying drawings:

[0007] Figure 1 A schematic diagram showing a voltage transmission network according to an embodiment of the present disclosure;

[0008] Figure 2 Show use Figure 1 Schematic diagram of a current source of a voltage delivery network;

[0009] Figure 3 Show use Figure 1 A schematic diagram of an output stage of a voltage-following coupled voltage regulator of a voltage delivery network; and

[0010] Figure 4 A flow chart of a voltage transmission method according to an embodiment of the present disclosure is shown.

[0011] Explanation of symbols

[0012] 100,220,340: Voltage transmission network

[0013] 101: First Node

[0014] 102: Second node

[0015] 103: The third node

[0016] 104: Fourth Node

[0017] 200: Current source

[0018] 210,320: n-channel metal oxide semiconductor transistor

[0019] 301: first gate node

[0020] 302: Second gate node

[0021] 303: Source node

[0022] 304: Drain node

[0023] 310: p-channel metal oxide semiconductor transistor

[0024] 330: Resistance

[0025] 400: Voltage delivery method

[0026] 410,420,430: Steps

[0027] C1: First capacitor

[0028] C2: Second capacitor

[0029] I O2 : Output current

[0030] OP1: First operational amplifier

[0031] OP2: Second operational amplifier

[0032] R1: First resistor

[0033] R2: Second resistor

[0034] UGA1: First unity gain amplifier

[0035] UGA2: Second unity gain amplifier

[0036] V1: first voltage

[0037] V2: Second voltage

[0038] V3: The third voltage

[0039] V4: fourth voltage

[0040] V A : Input voltage

[0041] V B : Gate voltage

[0042] V C : Reference gate voltage

[0043] V DD : Power node / first DC node

[0044] V E : Auxiliary output voltage

[0045] V F : Output voltage

[0046] V G1 : First gate voltage

[0047] V G2 : Second gate voltage

[0048] V SS : Ground node / second DC node DETAILED DESCRIPTION

[0049] The present disclosure describes a voltage delivery network. Although the specification describes several exemplary embodiments of the present disclosure that are considered to be advantageous modes of implementing the present invention, it should be understood that the present invention can be implemented in many ways and is not limited to the specific examples described below or the specific ways of implementing any features of these examples. In other cases, existing details are not shown or described to avoid obscuring parts of the present disclosure.

[0050] A person skilled in the art may understand the terms and basic concepts related to microelectronics used herein, such as "voltage", "current", "current source", "source follower", "common source amplifier", "operational amplifier (OPAMP)", "n-channel metal oxide semiconductor transistor (NMOST)", "p-channel metal oxide semiconductor transistor (PMOST)", "direct current (DC)", "power supply" and "ground", etc. Terms like these are used in the context of microelectronics, and the related concepts are obvious to a person skilled in the art, so they are not explained in detail here.

[0051] A circuit is a collection of transistors, capacitors, resistors and / or other electronic devices interconnected in a certain manner to achieve a specific function. In the present disclosure, a network is a circuit or a collection of circuits configured to achieve a specific function.

[0052] When receiving an input voltage at the gate and delivering an output voltage at the source, an n-channel MOS transistor (or a p-channel MOS transistor) is said to be configured in a source-follower configuration.

[0053] When receiving an input voltage at the gate and outputting an output voltage at the drain, an n-channel MOS transistor (or a p-channel MOS transistor) is said to be configured in a common-source amplifier configuration.

[0054] In this disclosure, “DC” stands for direct current, and “AC” stands for alternating current. A DC node is a node with a substantially fixed potential. In particular, “V DD ” is used to denote the first DC node known as the power node, and “V SS” is used to represent the second DC node, which is called the ground node. DC voltage is a voltage that is essentially fixed. AC voltage is a voltage that oscillates over time, also known as a dynamic voltage.

[0055] A unity gain amplifier is an amplifier that receives an input voltage and outputs an output voltage such that when the frequency of its input voltage is below the cutoff frequency, its output voltage is nearly equal to the input voltage.

[0056] A schematic diagram of a voltage transmission network 100 according to an embodiment of the present invention is shown in Figure 1 The voltage transmission network 100 includes a first unit gain amplifier UGA1 and a second unit gain amplifier UGA2, a first resistor R1 and a first capacitor C1. The first unit gain amplifier UGA1 and the second unit gain amplifier UGA2 are configured in a back-to-back connection structure to receive a first voltage V1 at a first node 101 and a second voltage V2 at a second node 102, respectively, and jointly output a third voltage V3 at a third node 103. The first resistor R1 is configured as a series resistor inserted between the third node 103 and the second node 102. The first capacitor C1 is configured as a series resistor inserted between the second node 102 and the ground node V SS The first unity gain amplifier UGA1 includes a first operational amplifier OP1, a second resistor R2 and a second capacitor C2. The first operational amplifier OP1 is configured to output a fourth voltage V4 at a fourth node 104 according to a difference between the first voltage V1 and the third voltage V3.

[0057] The second resistor R2 is configured as a series resistor inserted between the fourth node 104 and the third node 103 .

[0058] The second capacitor C2 is configured to be inserted between the third node 103 and the ground node V SSThe second unity gain amplifier UGA2 includes a second operational amplifier OP2 configured in a non-inverting negative feedback structure, wherein the second operational amplifier OP2 receives an input voltage (second voltage V2) as a positive input at a positive input terminal represented by "+", and feeds back an output voltage (third voltage V3) as a negative input at a negative input terminal represented by "-". The first operational amplifier OP1 is also configured in a non-inverting negative feedback structure, wherein the first operational amplifier OP1 receives an input voltage (first voltage V1) at a positive input terminal represented by "+", and feeds back an output voltage (fourth voltage V4) as a negative input at a negative input terminal represented by "-" through a second resistor R2. Due to the negative feedback of the first operational amplifier OP1, the DC level of the third voltage V3 will be almost equal to the DC level of the first voltage V1. Due to the negative feedback of the second operational amplifier OP2, the DC level of the third voltage V3 will be almost equal to the DC level of the second voltage V2. Therefore, the DC level of the second voltage V2 will be almost equal to the DC level of the first voltage V1, thereby achieving the goal of the voltage transmission network having high accuracy.

[0059] The second resistor R2 and the second capacitor C2 form a low-pass filter to effectively offset the negative feedback of the first operational amplifier OP1 in response to the high-frequency component of the first voltage V1. Therefore, the third voltage V3 will track the low-frequency component of the first voltage V1, but not its high-frequency component. In this way, the first unit gain amplifier UGA1 implements a low-pass filter, wherein the third voltage V3 is a low-pass filter version of the first voltage V1. When the corner frequency of the low-pass filter formed by the second resistor R2 and the second capacitor C2 is low enough, most of the noise of the first voltage V1 can be effectively suppressed. In one embodiment of the present invention, the second capacitor C2 is a clear circuit element. In another embodiment of the present invention, the second capacitor C2 is a parasitic capacitor that always exists in the actual circuit implementation.

[0060] The first unit gain amplifier UGA1 and the second unit gain amplifier UGA2 will both generate circuit noise, thereby generating noise of the third voltage V3. The low frequency noise of the third voltage V3 will be suppressed by the negative feedback of the first operational amplifier OP1, while the high frequency noise of the third voltage V3 still exists. However, the first resistor R1 and the first capacitor C1 form another low pass filter so that the second voltage V2 is a low pass filtered version of the third voltage V3. When the corner frequency of the low pass filter formed by the first resistor R1 and the first capacitor C1 is low enough, most of the noise of the third voltage V3 can be effectively suppressed, so even if the noise of the third voltage V3 is large, the second voltage V2 can also have lower noise.

[0061] Since the first unit gain amplifier UGA1 and the second unit gain amplifier UGA2 jointly output the third voltage V3, the first operational amplifier OP1 must have a stronger driving capability and a lower output resistance than the second operational amplifier OP2, so that the first unit gain amplifier UGA1 can dominate the second unit gain amplifier UGA2 and force the third voltage V3 to effectively track the first voltage V1. The first operational amplifier OP1 and the second operational amplifier OP2 can be implemented by known operational amplifiers in the prior art at the discretion of the circuit designer.

[0062] In an alternative embodiment, the second resistor R2 is removed and replaced by a short circuit. In this case, the first unity gain amplifier UGA1 may not be able to effectively suppress the noise of the first voltage V1 and may cause the third voltage V3 to have noise. However, as mentioned above, the low-pass filter formed by the first resistor R1 and the first capacitor C1 can still effectively suppress the noise of the third voltage V3.

[0063] In one embodiment of the present invention, the voltage delivery network 100 is used to bias a current source. Figure 2 As shown, the current source 200 includes an n-channel metal oxide semiconductor transistor 210, which is configured to be B Output current I O2 , this output current I O2 The voltage transmission network 220 is based on the input voltage V A The voltage transmission network 220 is composed of Figure 1 The voltage transmission network 100 is implemented, wherein the first voltage V1 and the second voltage V2 respectively implement the input voltage V A and gate voltage V B In an alternative embodiment, the n-channel MOS transistor 210 is replaced by a p-channel MOS transistor, and the ground node V SS By the power node V DD In any case, the gate voltage V B is the input voltage V A The output current I can be set accurately with low noise. O2 .

[0064] In one embodiment of the present invention, the voltage delivery network 100 is incorporated into the output stage of a flip-flop voltage follower voltage regulator. Figure 3As shown, the output stage of the flip-flop voltage follower voltage regulator 300 includes a p-channel metal oxide semiconductor transistor 310, an n-channel metal oxide semiconductor transistor 320, a resistor 330 and a voltage transmission network 340. The p-channel metal oxide semiconductor transistor 310 and the n-channel metal oxide semiconductor transistor 320 are both configured as source-follower structures to receive a first gate voltage V G1 (at the first gate node 301) and the second gate voltage V G2 (at the second gate node 302), and jointly output an output voltage V that can be used by a load circuit (not shown in the figure) F (at source node 303). The source, gate and drain of p-channel MOS transistor 310 are connected to source node 303, first gate node 301 and drain node 304, respectively. The source, gate and drain of n-channel MOS transistor 320 are connected to source node 303, second gate node 302 and power supply node V DD The resistor 330 is inserted between the drain node 304 and the ground node V SS between, and configured to establish the auxiliary output voltage V E The voltage delivery network 340 receives the reference gate voltage V C And output the first gate voltage V G1 , and can be obtained by Figure 1 The voltage delivery network 100 is implemented, wherein the first voltage V1 and the second voltage V2 respectively implement the reference gate voltage V C and the first gate voltage V G1 In the application of the flip voltage follower voltage regulator, the output voltage V F The DC level is determined by the first gate voltage V G1 The DC level of Figure 1 The voltage delivery network 100 is used to implement the voltage delivery network 340, the first gate voltage V G1 The DC level is almost equal to the reference gate voltage V C The DC level, while referring to the gate voltage V C The noise will be greatly suppressed. Therefore, the output voltage V F In an alternative embodiment, the n-channel metal oxide semiconductor transistor 320 is replaced by a p-channel metal oxide semiconductor transistor configured as a common source amplifier, wherein the source, gate and drain are respectively connected to the power supply node V DD , the second gate voltage V G2 and source node 303. This is an alternative embodiment of the output stage of a flip-flop voltage follower voltage regulator known in the prior art and will not be described in detail.

[0065] Flipped voltage follower voltage regulators are generally known in the art and can be implemented in various forms, one or more of which are described in the following papers: RG Carvajal et al., "The flipped voltage follower: a useful cell for low-voltage low-power circuit design," IEEE Trans. On Circuits and Systems I: Regular Paper, vol. 52, pp / 1276-1291, 2005.

[0066] like Figure 4 As shown in the flowchart, the voltage transmission method 400 according to the embodiment of the present invention includes: (step 410) combining a first unit gain amplifier and a second unit gain amplifier configured in a back-to-back connection structure to receive a first voltage at a first node and a second voltage at a second node, respectively, and jointly output a third voltage at a third node; (step 420) combining a first resistor, which is configured as a series resistor inserted between the third node and the second node; (step 430) combining a first capacitor, which is configured as a shunt capacitor inserted between the second node and the DC node.

[0067] Those skilled in the art will readily appreciate that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present disclosure. Therefore, the above disclosure should not be interpreted as being limited only by the limits of the appended claims.

Claims

1. A voltage transmission network comprising: A first unit gain amplifier and a second unit gain amplifier are arranged in a back-to-back connection structure to receive a first voltage and a second voltage at a first node and a second node respectively, and jointly output a third voltage at a third node; a first resistor, inserted between the third node and the second node; and A first capacitor is inserted between the second node and a DC node.

2. A voltage transmission network as described in claim 1, wherein the first unity gain amplifier includes a first operational amplifier configured in a non-inverting negative feedback structure, wherein the first operational amplifier receives the first voltage as a positive input and feeds back the third voltage as a negative input, the first operational amplifier outputs a fourth voltage at a fourth node based on a difference between the positive input and the negative input, and the fourth node is DC coupled to the third node.

3. The voltage delivery network of claim 2, wherein the first unity gain amplifier further comprises: A second resistor is configured as a series resistor inserted between the third node and the fourth node.

4. The voltage delivery network of claim 3, wherein the first unity gain amplifier further comprises: A second capacitor is configured as a shunt capacitor inserted between the third node and the DC node.

5. A voltage delivery network as described in claim 1, wherein the second unity gain amplifier includes a second operational amplifier configured in a non-inverting negative feedback structure, wherein the second voltage is received as a positive input, the third voltage is an output, which is fed back as a negative input, and the second operational amplifier adjusts the output based on a difference between the positive input and the negative input.

6. The voltage delivery network of claim 1 , wherein the voltage delivery network further comprises: A metal oxide semiconductor transistor is configured as a current source, wherein an output current is established according to the second voltage. 7 . The voltage delivery network of claim 6 , wherein the MOS transistor is an n-channel MOS transistor.

8. The voltage delivery network of claim 6, wherein the MOS transistor is a p-channel MOS transistor.

9. The voltage delivery network of claim 1 , wherein the voltage delivery network further comprises: An output stage of a flip-flop voltage follower voltage regulator includes a p-channel metal oxide semiconductor transistor, an n-channel metal oxide semiconductor transistor and a resistor, wherein the p-channel metal oxide semiconductor transistor and the n-channel metal oxide semiconductor transistor are both configured in a source follower structure to jointly output an output voltage according to the second voltage and a gate voltage respectively, and the resistor is inserted between a drain of the p-channel metal oxide semiconductor transistor and a ground node.

10. The voltage delivery network of claim 1, wherein the voltage delivery network further comprises: An output stage of a flip-flop voltage follower voltage regulator includes a first p-channel metal oxide semiconductor transistor, a second p-channel metal oxide semiconductor transistor and a resistor, wherein the first p-channel metal oxide semiconductor transistor and the second p-channel metal oxide semiconductor transistor are respectively configured in a source follower structure and a common source amplifier structure to jointly output an output voltage according to the second voltage and a gate voltage, respectively, and the resistor is inserted between a drain of the first p-channel metal oxide semiconductor transistor and a ground node.

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