Transformer device and drive circuit

Abstract

The invention provides a transformer device and a drive circuit. The transformer device comprises an alternating current input end, a bridge rectifier circuit, a high-voltage frequency conversion circuit, a power switch circuit, an optical coupling circuit, a zero voltage and working voltage division circuit and a primary side controller. The power switch circuit is controlled by the driving signal. The primary side controller operates according to the working voltage. The primary side controller is set to be one of a plurality of working modes according to a load detection signal provided by the optical coupling circuit and a zero voltage detection signal provided by the zero voltage and working voltage division circuit; and correspondingly adjusting the amplitude and the frequency of a pulse width modulation signal in the driving signal according to the set working mode. The working modes at least comprise a first load mode, a second load mode and a standby mode.

Description

Technical Field

[0001] The present invention relates to a voltage conversion technology for converting alternating current (AC) to direct current (DC), and in particular to a transformer device and a driving circuit for the transformer device. Background Art

[0002] As energy conservation and environmental protection become a consensus, electronic products from smartphones to home appliances need to comply with many international standard energy conservation regulations, and these energy conservation regulations have provisions for standby power consumption. The so-called "standby power consumption" is the power consumed by electronic products under very light or zero load conditions.

[0003] As technology evolves, these energy-saving standards are becoming more and more stringent. Examples of these energy-saving standards include the level 6 standard set by the U.S. Department of Energy (DoE) (standby power consumption must be less than 100mW), the Tier 2 standard set by the EU Code of Conduct (CoC) (standby power consumption must be less than 75mW), Energy Star certification, Blue Angel certification, etc.

[0004] Although various technologies have been used to reduce the standby power consumption of electronic products, the above energy-saving standards have set stricter restrictions on standby power consumption. Therefore, how to meet the above energy-saving standards in terms of standby power consumption is a major technical challenge for power supply design in electronic products. Summary of the invention

[0005] The present invention is directed to a transformer device and a driving circuit for the transformer device, which saves power consumption by adjusting a driving signal for controlling a power switch.

[0006] According to an embodiment of the present invention, a transformer device includes an AC input terminal, a bridge rectifier circuit, a high-voltage frequency conversion circuit, a power switch circuit, an optical coupling circuit, a zero voltage and working voltage voltage divider circuit, and a primary-side controller. The AC input terminal provides an AC voltage. The bridge rectifier circuit converts the AC voltage into a first voltage. The high-voltage frequency conversion circuit includes a primary side winding, a secondary side winding, and an auxiliary winding. The power switch circuit is coupled to the primary side winding. The power switch circuit is controlled by a drive signal. The high-voltage frequency conversion circuit converts the first voltage into a DC voltage based on the primary side winding, the secondary side winding, and the power switch circuit. The optical coupling circuit generates a load detection signal based on the DC voltage. The zero voltage and working voltage voltage divider circuit maps a working voltage proportional to the output voltage based on the auxiliary winding to provide a zero voltage detection signal. The primary-side controller couples the optical coupling circuit and the power switch circuit. The primary side controller operates according to the working voltage, and the primary side controller sets the primary side controller to one of a plurality of working modes according to the load detection signal and the zero voltage detection signal, and correspondingly adjusts the amplitude and frequency of a pulse width modulation (PWM) signal in the driving signal according to the set working mode. The working modes include at least a first load mode, a second load mode and a standby mode.

[0007] According to an embodiment of the present invention, a driving circuit is used to drive a transformer device. The driving circuit includes a load detection terminal, a zero voltage detection terminal, an operating voltage mapping terminal, a mode selection circuit, a mode-type undervoltage lockout circuit, a driving amplitude adjustment circuit, a driving frequency adjustment circuit, and a buffer. The load detection terminal obtains a load detection signal. The zero voltage detection terminal obtains a zero voltage detection signal. The operating voltage mapping terminal obtains an operating voltage, wherein the driving circuit operates according to the operating voltage. The mode selection circuit compares the load detection signal with a load threshold to generate a first detection signal, compares the zero voltage detection signal with a system power threshold to generate a second detection signal, and generates a mode selection signal according to the first detection signal and the second detection signal. The mode-type undervoltage lockout circuit is coupled to the mode selection circuit. The mode-type undervoltage lockout circuit selects one of a plurality of first reference voltages to be selected as a first reference voltage according to the mode selection signal, and compares the first reference voltage with a voltage-divided signal corresponding to the operating voltage to generate an undervoltage lockout signal. The driving amplitude adjustment circuit is coupled to the mode selection circuit. The driving amplitude adjustment circuit selects one of the second reference voltages to be selected as the second reference voltage according to the mode selection signal, and determines the amplitude of the PWM signal in the driving signal according to the second reference voltage and the working voltage, and the driving signal is used to drive the power switch in the transformer device. The driving frequency adjustment circuit is coupled to the mode-type undervoltage lockout circuit. The driving frequency adjustment circuit determines the frequency of the PWM signal in the driving signal according to the load detection signal, the zero voltage detection signal and the undervoltage lockout signal. The power supply end of the buffer is coupled to the output end of the driving amplitude adjustment circuit. The input end of the buffer is coupled to the output end of the driving frequency adjustment circuit. The buffer is used to generate the PWM signal in the driving signal.

[0008] Based on the above, the transformer device and the driving circuit for the transformer device described in the embodiment of the present invention use the load detection signal and the zero voltage detection signal to determine whether the current working mode of the driving circuit is a heavy load mode, a light load mode or a standby mode, and then adjust the amplitude and frequency of the PWM signal in the driving signal accordingly according to these working modes. In detail, in the heavy load mode, the amplitude and frequency of the PWM signal in the driving signal are normal, and the working voltage of the driving circuit is not adjusted. In the light load mode, the amplitude of the PWM signal in the driving signal will be lowered, and the frequency of the PWM signal can also be reduced to reduce the switching loss of the power switch. In addition, the working voltage of the driving circuit can also be slightly lowered in the light load mode, thereby reducing the static power consumption of the driving circuit. In the standby mode, in addition to the working voltage of the driving circuit being reduced, the amplitude of the PWM signal in the driving signal is also lowered, and the PWM signal in the driving signal is stopped according to the load detection signal to avoid the switching loss of the power switch. Thereby, the transformer device and the driving circuit of the present embodiment can further save power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a transformer device according to a first embodiment of the present invention.

[0010] Figure 2 yes Figure 1 Schematic diagram of the load detection signal and the PWM signal frequency in the drive signal in the transformer device.

[0011] Figure 3 yes Figure 1 Waveform diagram of the load detection signal and the drive signal in the transformer device.

[0012] Figure 4 yes Figure 1 Schematic diagram of the waveforms of the operating voltage, drive signal and time of the primary side controller in the transformer device.

[0013] Figure 5 is a schematic diagram of a transformer device according to a second embodiment of the present invention.

[0014] Figure 6 yes Figure 5 Detailed circuit diagram of the primary side controller.

[0015] Figure 7 yes Figure 5 Schematic diagram of the waveforms of the operating voltage, drive signal and time of the primary side controller in the transformer device.

[0016] Figure 8 Detailed circuit diagram of the primary side controller according to the third embodiment of the present invention.

[0017] Description of Reference Numerals

[0018] 100, 500: Transformer device;

[0019] 110: Bridge rectifier circuit;

[0020] 120: high frequency transformer circuit;

[0021] 130: Optical coupling circuit;

[0022] 140, 540, 840: primary side controller;

[0023] 150: power switch circuit;

[0024] 160: shock absorbing circuit;

[0025] 170: output rectifier circuit;

[0026] 500: Transformer device;

[0027] 505: electromagnetic interference filter;

[0028] 515: voltage start circuit;

[0029] 531: Optocoupler;

[0030] 532: voltage divider circuit;

[0031] 540: primary side controller;

[0032] 542: mode selection circuit;

[0033] 544: Mode type undervoltage lockout circuit;

[0034] 546: driving amplitude adjustment circuit;

[0035] 548: driving frequency adjustment circuit;

[0036] 549, 860: buffer;

[0037] 580: Auxiliary winding voltage stabilizing circuit;

[0038] 590: Zero voltage and working voltage divider circuit;

[0039] 595: current detection circuit;

[0040] 610: timer;

[0041] 620: sample and hold circuit;

[0042] 630: first detector;

[0043] 640: second detector;

[0044] 641: second multiplexer;

[0045] 642: second amplifier;

[0046] 650: first AND gate;

[0047] 660: first comparator;

[0048] 661: first multiplexer;

[0049] 662: first voltage divider circuit;

[0050] 670, 830: valley detection circuit;

[0051] 680, 840: On-time control circuit;

[0052] 685, 850: Set reset trigger;

[0053] 695: Second AND gate;

[0054] 810, 820: comparator;

[0055] UVLOB: undervoltage lockout signal;

[0056] AC: alternating current voltage terminal;

[0057] DCVout: DC output terminal;

[0058] CL1: primary side winding;

[0059] CL2: Secondary winding;

[0060] CL3: auxiliary winding;

[0061] P3: endpoint;

[0062] HV: high voltage signal terminal;

[0063] VCC: working voltage mapping terminal;

[0064] Vcc, VCC1: operating voltage;

[0065] DRV: driving voltage terminal;

[0066] drv: driving signal;

[0067] CS: current detection terminal;

[0068] ZCD: zero voltage detection terminal;

[0069] Zcd: zero voltage detection signal;

[0070] COMP: load detection terminal;

[0071] comp: load detection signal;

[0072] MSS: mode selection signal;

[0073] R1, RP1, RP2, RD1, RD2, RO1: resistors;

[0074] C1~C3, CD1, CO1, CO2: capacitors;

[0075] ZD1: voltage regulator;

[0076] D1, D2: diodes;

[0077] Vskip, VCChold: voltage;

[0078] UVLO, UVLO_H, HVLO_L: minimum voltage;

[0079] Tskip, Ts1, Ts2: time / output pulse burst period;

[0080] MP: P-type transistor;

[0081] Vth1: load threshold;

[0082] Vth2: system power threshold;

[0083] VrefA, VrefB: first reference voltage to be selected;

[0084] Vref1, Vref2: second reference voltage to be selected;

[0085] Zcdsh: sample-and-hold signal;

[0086] SD1, SD2: first and second detection signals. DETAILED DESCRIPTION

[0087] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0088] Figure 1 1 is a schematic diagram of a transformer device 100 according to a first embodiment of the present invention. The transformer device 100 mainly includes a bridge rectifier circuit 110, a high-frequency voltage conversion circuit 120, an optical coupling circuit 130, a primary controller 140 and a power switch circuit 150. The transformer device 100 also includes a buffer circuit 160 and an output rectifier circuit 170. The primary controller 140 can also be called a driving circuit of the transformer device 100. The primary controller 140 can be implemented in the form of a chip.

[0089] The AC voltage is provided to the bridge rectifier circuit 110 through the AC input terminal AC. The bridge rectifier circuit 110 uses a diode bridge and a capacitor C1 to convert the AC voltage into a voltage (first voltage) at the terminal P1. The terminal P0 is delayed in oscillation by the capacitor C2, the resistor R1 and the diode D1 in the buffer circuit 160.

[0090] The high-frequency transformer circuit 120 mainly includes a primary winding CL1 and a secondary winding CL2. The output rectifier circuit 170 includes a diode D2 and a capacitor C3. The high-frequency transformer circuit 120 converts the voltage at the terminal P1 into a DC voltage at the terminal P2 by the relationship between the number of coils between the two windings CL1 and CL2 and the opening frequency of the power switch in the power switch circuit 150. The opening frequency of the power switch in the power switch circuit 150 is controlled by the drive signal drv. The voltage at the terminal P2 is also affected by the output rectifier circuit 170 to stabilize its voltage, thereby generating a voltage at the DC output terminal DCVout.

[0091] The optical coupling circuit 130 generates a load detection signal comp according to the DC voltage on the DC output terminal DCVout. The load detection signal comp is used to detect the severity of the load on the DC output terminal DCVout. When the voltage value of the load detection signal comp is higher, it indicates that the load of the transformer device 100 is heavier; when the voltage value of the load detection signal comp is lower, it indicates that the load of the transformer device 100 is lighter. The primary side controller 140 determines the severity of the load on the DC output terminal DCVout of the transformer device 100 according to the load detection signal comp to adjust the drive signal drv on the drive voltage terminal DRV. The drive signal drv of this embodiment is a pulse width modulation (PWM) signal. For the convenience of explanation, this embodiment divides the severity of the load on the DC output terminal DCVout into four states: the aforementioned heavy load is called a heavy load state; the aforementioned medium load is called a medium load state; the aforementioned light load is called a light load state; the aforementioned very light load or even zero load is called a no-load state.

[0092] In this embodiment, the primary controller 140 can reduce standby power consumption by reducing its own operating voltage and reducing the switching frequency of the switch in the driving signal drv used to control the power switch circuit 150. The reason is that when the transformer device 100 is lightly loaded or in standby mode, the main factors affecting power consumption are the static power consumption of the primary controller 140 (that is, the power value obtained by multiplying the operating voltage of the primary controller 140 by the static current) and the switching loss of the power switch circuit 150 caused by controlling the switching of the power switch in the power switch circuit 150 through the driving signal drv.

[0093] Figure 2 yes Figure 1 A schematic diagram of the load detection signal comp and the PWM signal frequency in the driving signal drv in the transformer device 100 . Figure 3 yes Figure 1 The waveform diagram of the load detection signal comp and the drive signal drv in the transformer device 100. Please also refer to Figures 1 to 3 , when the load of the transformer device 100 is adjusted from a heavy load state to a light load state, the primary controller 140 can be aware of the change in the load in the transformer device 100 based on the load detection signal comp. For example, when the voltage value of the load detection signal comp drops below a predetermined voltage (e.g., voltage Vskip), the primary controller 140 will enter the skip mode and make the PWM signal frequency in the drive signal drv zero during the time Tskip, thereby stopping the switching of the power switch in the power switch circuit 150, thereby reducing the switching loss; when the voltage of the load detection signal comp rises and makes it greater than the predetermined voltage (e.g., voltage Vskip), this situation may be Figure 1 If the energy of the DC output terminal DCVout is insufficient or the load is increased, the primary side controller 140 will continue to generate the driving signal drv to continue switching the power switch in the power switch circuit 150 .

[0094] Each power switch still causes power loss. Therefore, in addition to reducing the number of switching times of the power switch by controlling the drive signal drv, the embodiment of the present invention can also reduce the ability of the primary side controller 140 to drive the power switch (for example, reducing the voltage of the drive signal drv) to reduce standby power consumption, that is, reduce switching losses.

[0095] On the other hand, see Figure 4 , Figure 4 yes Figure 1Schematic diagram of the waveforms of the working voltage, driving signal DRV and time of the primary controller 140 in the transformer device 100. Since the conduction loss of the primary controller 140 under medium and heavy loads needs to be taken into consideration, the primary controller 140 will be set to operate at a voltage VCChold slightly higher than the minimum voltage UVLO, so that the working voltage of the primary controller 140 must be maintained at least above the minimum voltage UVLO to maintain the voltage value of the driving signal drv that drives the power switch. As long as the working voltage of the primary controller 140 is lower than the voltage VCChold, this embodiment will increase the working voltage of the primary controller 140 to prevent the working voltage of the primary controller 140 from being lower than the minimum voltage UVLO and causing the primary controller 140 to be shut down and unable to operate. However, this means that it is difficult to further reduce the static power consumption of the primary controller 140 itself by reducing the working voltage of the primary controller 140. On the other hand, Figure 4 The time Ts1 represents the period of the output pulse burst of the driving signal drv. The longer the period of the output pulse burst of the driving signal drv is, the longer the period of the overall system stoppage of the transformer device 100 is, and the lower the switching loss is.

[0096] In order to balance the conduction loss in medium load and heavy load state with the switching loss in light load and no-load state, the present invention proposes another embodiment (second embodiment) to adjust the minimum working voltage of the primary controller 140 and the voltage value of the driving signal drv to normal values ​​through the primary controller 140 in medium load and heavy load state. In addition, in light load and no-load state, the primary controller 140 can reduce the static power consumption by reducing its own working voltage, and synchronously reduce the amplitude and frequency of the PWM signal in the driving signal drv to reduce the switching loss.

[0097] Figure 5 is a schematic diagram of a transformer device 500 according to a second embodiment of the present invention. Figure 5 Transformer device 500 and Figure 1 Some circuits in the transformer device 100 are the same and are marked with the same reference numerals and the description thereof is omitted. Figure 5 The transformer device 500 further includes an electromagnetic interference (EMI) filter 505 , a voltage startup circuit 515 , an auxiliary winding CL3 , an auxiliary winding voltage regulator circuit 580 , a zero voltage and working voltage divider circuit 590 , and a current detection circuit 595 . Figure 5 The primary side controller 540, the power switch circuit 150 and the optical coupling circuit 130 in the transformer device 500 have detailed circuit structures. The primary side controller 540 can be implemented in a chip form.

[0098] The primary side controller 540 outputs a driving signal drv to control whether the power switch circuit 150 is turned on and the time of the conduction. The driving signal drv is a PWM signal mode. After the primary side controller 540 is activated, it first generates a mode selection signal MSS according to the load detection signal comp from the optical coupling circuit 130 and the zero voltage detection signal zcd from the zero voltage and working voltage divider circuit 590. Then, the primary side controller 540 adjusts the amplitude (that is, the voltage size) of the driving signal drv according to the mode selection signal MSS, and adjusts the frequency or conduction time of the driving signal drv according to the current working voltage of the primary side controller 540.

[0099] The electromagnetic interference filter 505 is used to perform electromagnetic interference filtering on the AC voltage obtained from the AC voltage source AC. The voltage start-up circuit 515 (here implemented as a resistor) provides a high-voltage start-up current and a detection signal to the high-voltage signal terminal HV of the primary controller 540. The primary controller 540 knows whether the current output DC voltage DCVout is high voltage or low voltage through the high-voltage start-up current and the detection signal received by the high-voltage signal terminal HV. When the primary controller 540 determines that the output DC voltage DCVout voltage value is too high or too low, the primary controller 540 immediately stops the overall operation of the transformer device 500 to prevent the transformer device 500 itself and the load from being damaged due to excessively high or low voltage.

[0100] The auxiliary winding CL3 supplies power to the primary controller 540 through the high-frequency voltage conversion circuit 120 to generate a voltage at the terminal P3. The auxiliary winding voltage stabilization circuit 580 stabilizes the voltage at the terminal P3 through a diode, a resistor and a capacitor, and provides this voltage to the working voltage mapping terminal VCC of the primary controller 540 as the working voltage of the primary controller 540. The input terminal (i.e., the terminal P3) of the zero voltage and working voltage divider circuit 590 is coupled to the output terminal of the auxiliary winding CL3. The zero voltage and working voltage divider circuit 590 divides the voltage at the terminal P3 to generate a zero voltage detection signal zcd, and provides it to the zero voltage detection terminal ZCD of the primary controller 540.

[0101] The optical coupling circuit 130 includes an optical coupler 531, a voltage divider circuit 532, a resistor RO1, capacitors CO1, CO2 and a voltage regulator ZD1. The voltage divider circuit 532 divides the voltage on the DC output terminal DCVout and provides the divided voltage to one end of the capacitor CO1. One end of the resistor RO1 is coupled to the DC output terminal DCVout, and the other end of the resistor RO1 is coupled to one end of the light-emitting component in the optical coupler 531. The other end of the light-emitting component in the optical coupler 531 is coupled to the other end of the capacitor CO1 and one end of the voltage regulator ZD1. The other end of the voltage regulator ZD1 is grounded. The two ends of the capacitor CO2 are respectively coupled to the sensor in the optical coupler 531 (here implemented as a photosensitive transistor). One end of the capacitor CO2 is also coupled to the load detection terminal COMP of the primary side controller 540 to provide a load detection signal comp. When the voltage on the DC output terminal DCVout increases or decreases, the voltage value of the load detection signal comp will increase or decrease accordingly.

[0102] The power switch circuit 150 includes a power switch SWP, resistors RP1 and RP2. One end of the resistor RP1 is coupled to the driving voltage terminal DRV of the primary side controller 540 to receive the driving signal drv. The control terminal of the power switch SWP receives the driving signal drv through the resistor RP1, so the power switch SWP is controlled by the driving signal drv. One end of the resistor RP2 is coupled to the other end of the resistor RP2 and the control end of the power switch SWP, and the other end of the resistor RP2 is grounded.

[0103] The current detection circuit 595 includes resistors RD1, RD2 and a capacitor CD1. One end of the resistor RD1 is coupled to one end of the resistor RD2 and one end of the power switch SWP. The other end of the resistor RD1 is grounded. The other end of the resistor RD2 is coupled to one end of the capacitor CD1 and a current detection terminal CS of the primary controller 540. The current detection circuit 595 provides a voltage detection signal corresponding to the current flowing through the power switch SWP from one end of the capacitor CD1 to the primary controller 540.

[0104] The primary side controller 540 is coupled to the optical coupling circuit 130 and the power switch circuit 150. The primary side controller 540 operates according to the working voltage vcc received by the working voltage mapping terminal VCC. The primary side controller 540 sets the primary side controller 540 to one of a plurality of working modes according to the load detection signal comp and the zero voltage detection signal zcd, and adjusts the amplitude and frequency of the pulse width modulation signal in the driving signal drv accordingly according to the set working mode. The aforementioned working modes at least include a first load mode (e.g., a heavy load mode), a second load mode (e.g., a light load mode) and a standby mode. When the set working mode is the standby mode, the frequency and amplitude of the PWM signal generated by the primary side controller 540 are lower than those in the first load mode (heavy load mode) and the second load mode (light load mode). The amplitude of the adjusted PWM signal corresponding to the first load mode (heavy load mode) is greater than the amplitude of the adjusted PWM signal corresponding to the second load mode (light load mode), and the frequency of the adjusted PWM signal corresponding to the first load mode (heavy load mode) is higher than or equal to the frequency of the adjusted PWM signal corresponding to the second load mode (light load mode), thereby further distinguishing the heavy load and light load modes in the load mode in more detail, and thus further reducing the power consumption of the transformer device 500 in the light load mode and the standby mode.

[0105] Figure 5 The primary side controller 540 includes a load detection terminal COMP, a zero voltage detection terminal ZCD, a working voltage mapping terminal VCC, a mode selection circuit 542 , a mode-type undervoltage lockout circuit 544 , a driving amplitude adjustment circuit 546 , a driving frequency adjustment circuit 548 and a buffer 549 . Figure 5 The primary side controller 540 is also referred to as a driving circuit of the transformer device 500. Figure 6 Detailed description Figure 5 Detailed circuit diagram of each component in the primary side controller 540.

[0106] Figure 6 yes Figure 5 Detailed circuit diagram of the primary side controller 540. The load detection terminal COMP receives a load detection signal comp. The zero voltage detection terminal ZCD receives a zero voltage detection signal zcd. The working voltage mapping terminal VCC receives a working voltage vcc.

[0107] The mode selection circuit 542 includes a timer 610, a sample and hold circuit 620, a first detector 630, a second detector 640 and an AND gate 650. A first input terminal of the first detector 630 receives a load detection signal comp. A second input terminal of the first detector 630 receives a load threshold Vth1. An output terminal of the first detector 630 generates a first detection signal SD1.

[0108] The load threshold Vth1 is a threshold used to determine whether the current transformer device 500 is in the heavy load mode or the light load mode. In this embodiment, when the transformer device 500 is in the heavy load mode, the load detection signal comp should be greater than the load threshold Vth1, and the first detection signal SD1 is logic "0"; when the transformer device 500 is not in the heavy load mode, the load detection signal comp should be less than or equal to the load threshold Vth1, and the first detection signal SD1 is logic "1".

[0109] The timer 610 is coupled to the sample and hold circuit 620. An input terminal of the sample and hold circuit 620 is coupled to the zero voltage detection terminal ZCD to receive the zero voltage detection signal zcd. The sample and hold circuit 620 receives and maintains the zero voltage detection signal zcd according to the signal of the timer 542 to generate a sampled and held signal zcdsh.

[0110] A first input terminal of the second detector 640 receives the sample-and-hold signal zcdsh. A second input terminal of the second detector 640 receives the system power supply threshold Vth2. An output terminal of the second detector 640 generates a second detection signal SD2.

[0111] The system power threshold Vth2 is used to determine whether the output voltage of the current transformer device 500 is in the system standby voltage. In this embodiment, the entire system power is 10V in normal operation, and the primary controller 540 also operates normally between its operating voltage of 10V and 5V. In this embodiment, the value of the system power threshold Vth2 is set at the threshold when the output voltage of the transformer device 500 is 5V, and at this time, the operating voltage of the primary controller 540 is close to the minimum voltage UVLO. When the output voltage of the transformer device 500 is high, the zero voltage detection signal zcd should be greater than the system power threshold Vth2, and the second detection signal SD2 is logic "0"; when the output voltage of the transformer device 500 is low and may even be lower than the minimum voltage UVLO, the zero voltage detection signal zcd should be less than or equal to the load threshold Vth2, and the second detection signal SD2 is logic "1". The first input terminal of the first AND gate 650 receives the first detection signal SD1, the second input terminal of the first AND gate 650 receives the second detection signal SD2, and the output terminal of the first AND gate 650 generates the mode selection signal MSS. Therefore, the mode selection circuit 542 compares the load detection signal comp with the load threshold Vth1 to generate the first detection signal SD1, compares the zero voltage detection signal zcd with the system power threshold Vth2 to generate the second detection signal SD2, and generates the mode selection signal MSS according to the first detection signal SD1 and the second detection signal SD2. In this embodiment, when the mode selection signal MSS is logic "1", it means that the first detection signal SD1 is logic "1" (i.e., the transformer device 500 is in a light load or standby state), and the second detection signal SD2 is logic "1" (i.e., the output voltage of the transformer device 500 is equal to 5V or lower than 5V). In contrast, when the mode selection signal MSS is logic "0", it means that the transformer device 500 is in a heavy load or medium load mode and the output voltage of the transformer device 500 is above 5V.

[0112] The mode-type undervoltage lockout circuit 544 is coupled to the mode selection circuit 542. The mode-type undervoltage lockout circuit 544 includes a first multiplexer 661, a first voltage divider circuit 662, and a first comparator 660. Multiple input terminals of the first multiplexer 661 receive multiple first reference voltages to be selected, respectively. The control terminal of the first multiplexer 661 receives the mode selection signal MSS, and the output terminal of the first multiplexer 661 provides a first reference voltage selected from the aforementioned first reference voltages to be selected. The first multiplexer 661 of this embodiment takes two input terminals as an example, and receives the first reference voltages to be selected VrefA and VrefB, respectively. The first reference voltage to be selected VrefA is used to distinguish the voltage value of the transformer device 500 in the heavy load mode or the medium-light load mode; the second reference voltage to be selected VrefB is used to distinguish the voltage value of the transformer device 500 in the light load mode or the standby state (i.e., the no-load mode). When the mode selection signal MSS is logic "1", the first multiplexer 661 is controlled by the mode selection signal MSS to use the second selected reference voltage VrefB as the first reference voltage; when the mode selection signal MSS is logic "0", the first multiplexer 661 is controlled by the mode selection signal MSS to use the first selected reference voltage VrefA as the first reference voltage.

[0113] The input terminal of the first voltage divider circuit 662 is coupled to the working voltage mapping terminal VCC to receive the working voltage vcc. The output terminal of the first voltage divider circuit 662 generates a divided voltage signal and is coupled to the non-inverting input terminal of the first comparator 660. The inverting input terminal of the first comparator 660 is coupled to the output terminal of the first multiplexer 661 to receive the first reference voltage. The output terminal of the first comparator 661 provides an under-voltage lockout signal UVLOB. In this embodiment, when the mode selection signal MSS is logic "0" (heavy load or medium load mode), the mode-type under-voltage lockout circuit 544 compares the first selected reference voltage VrefA with the divided voltage signal corresponding to the working voltage vcc, thereby generating an enabled under-voltage lockout signal UVLOB when the divided voltage signal is less than the first selected reference voltage VrefA. On the other hand, when the mode selection signal MSS is logic "1" (light load or standby state), the mode type under-voltage lockout circuit 544 compares the second selected reference voltage VrefB with the voltage-divided signal corresponding to the working voltage vcc, thereby generating an enabled under-voltage lockout signal UVLOB when the voltage-divided signal is less than the first selected reference voltage VrefB. In this embodiment, the voltage value of the first selected reference voltage VrefA is greater than the voltage value of the second selected reference voltage VrefB.

[0114] The driving amplitude adjustment circuit 546 is coupled to the mode selection circuit 542. The driving amplitude adjustment circuit 546 selects one of the second reference voltages (e.g., Vref1, Vref2) as the second reference voltage according to the mode selection signal MSS, and determines the amplitude of the PWM signal in the driving signal drv according to the second reference voltage and the working voltage vcc. In detail, the driving amplitude adjustment circuit 546 includes a second multiplexer 641, a second amplifier 642, a P-type transistor MP, a first resistor R11, and a second resistor R12. The input terminals of the second multiplexer 641 receive the plurality of second reference voltages to be selected respectively. The control terminal of the second multiplexer 641 receives the mode selection signal MSS, and the output terminal of the second multiplexer 641 provides a second reference voltage selected from the aforementioned second reference voltages to be selected. The second multiplexer 641 of this embodiment takes two input terminals as an example, and receives the second reference voltages to be selected Vref1 and Vref2 respectively, and the second reference voltage is one of the second reference voltages to be selected Vref1 and Vref2.

[0115] The inverting input terminal of the second amplifier 642 is coupled to the output terminal of the second multiplexer 641 to receive the second reference voltage. The control terminal of the P-type transistor MP is coupled to the output terminal of the second amplifier 642, the first terminal of the P-type transistor MP receives the working voltage vcc, and the second terminal of the P-type transistor serves as the output terminal of the driving amplitude adjustment circuit 546. The first terminal of the first resistor R11 is coupled to the second terminal of the P-type transistor MP, and the second terminal of the first resistor R11 is coupled to the non-inverting input terminal of the second amplifier 642. The first terminal of the second resistor R12 is coupled to the second terminal of the first resistor R11 and the non-inverting input terminal of the second amplifier 642. The second terminal of the first resistor R12 is grounded.

[0116] The output terminal of the driving amplitude adjustment circuit 546 is coupled to the power supply terminal of the buffer 549, so the voltage value of the output terminal of the driving amplitude adjustment circuit 546 is the maximum amplitude of the signal output by the buffer 549. The user of this embodiment can set the voltage values ​​of the second reference voltages Vref1 and Vref2 according to their needs, so that when the mode selection signal MSS is logic "0" (heavy load and medium load mode), the amplitude of the PWM signal in the driving signal drv is normal; when the mode selection signal MSS is logic "1" (light load and standby mode), the amplitude of the PWM signal in the driving signal drv is slightly lower than the normal amplitude, thereby reducing switching loss.

[0117] The driving frequency adjustment circuit 548 is coupled to the mode-type undervoltage lockout circuit 544. The driving frequency adjustment circuit 548 determines the frequency of the PWM signal in the driving signal drv according to the load detection signal comp, the zero voltage detection signal zcd and the undervoltage lockout signal UVLOB. In the present embodiment, the driving frequency adjustment circuit 548 also determines the frequency of the PWM signal in the driving signal drv according to the voltage detection signal cs combined with the aforementioned signals.

[0118] Figure 6 The driving frequency adjustment circuit 548 includes a valley detection circuit 670, an on-time control circuit 680, a set reset trigger 685 and a second AND gate 695. The input end of the valley detection circuit 670 receives a zero voltage detection signal zcd. The first input end of the on-time control circuit 680 receives a load detection signal comp, and the second input end of the on-time control circuit 680 receives a voltage detection signal cs. The set end S of the set reset trigger 685 is coupled to the output end of the valley detection circuit 670, and the reset end R of the set reset trigger 685 is coupled to the output end of the on-time control circuit 680. The output end of the set reset trigger 685 is coupled to the first input end of the second AND gate 695, and the second input end of the second AND gate 695 receives the undervoltage lockout signal UVLOB. The output end of the second AND gate 695 generates the waveform of the PWM signal in the driving signal drv. Figure 6 In the circuit structure of the driving frequency adjustment circuit 548, when the under-voltage lockout signal UVLOB is enabled (logic "0"), the output end of the second AND gate 695 will only maintain at logic "0" and will not generate the driving signal drv; when the under-voltage lockout signal UVLOB is disabled (logic "1"), the second AND gate 695 will generate the waveform of the PWM signal according to the mutual operation of the valley detection circuit 670, the on-time control circuit 680, and the setting reset trigger 685, and the output end of the second AND gate 695 provides the waveform of the PWM signal to the input end of the buffer 549. In addition, the amplitude of the PWM signal will be determined based on the voltage on the power supply end of the buffer 549. The power supply end of the buffer 549 is coupled to the output end of the driving amplitude adjustment circuit 546, and the input end of the buffer 549 is coupled to the output end of the driving frequency adjustment circuit 548 to generate the PWM signal in the driving signal drv.

[0119] Figure 7 yes Figure 5 A schematic diagram of the waveforms of the working voltage, driving signal drv and time of the primary controller 540 in the transformer device 500. Figure 5The transformer device 500 can make the working voltage of the primary controller 540 reciprocate between the minimum voltage UVLO_H and UVLO_L to reduce the static power consumption of the primary controller 540. The drive amplitude adjustment circuit 546 in the primary controller 540 can reduce the amplitude of the PWM signal in the drive signal drv to the level of the second reference voltage Vref2 to be selected, thereby reducing the switching power consumption of the drive signal drv for the power switch. On the other hand, Figure 7 The time Ts2 represents the period of the output pulse burst of the driving signal drv. Figure 4 and Figure 7 , Figure 4 The output pulse period Ts1 is significantly shorter than Figure 7 The output pulse burst period Ts2 is shorter, so it means Figure 7 The overall system stop time period of the transformer device 500 of the second embodiment is longer, and the switching loss is lower than that of the first embodiment.

[0120] Figure 4 The time Ts1 represents the period of the output pulse burst of the driving signal drv. The longer the period of the output pulse burst of the driving signal drv is, the longer the period of the overall system stoppage of the transformer device 100 is, and the lower the switching loss is.

[0121] Figure 8 840 is a detailed circuit diagram of the primary side controller 840 according to the third embodiment of the present invention. Figure 5 The difference between the second embodiment and the second embodiment is that the circuit structures of the primary side controllers 540 and 840 are different. Figure 8 The primary side controller 840 includes comparators 810 and 820, a valley detection circuit 830, a conduction time control circuit 840, a set reset trigger 850 and a buffer 860. The non-inverting input terminal of the comparator 810 is coupled to the middle node of the two resistors as a voltage divider circuit, one end of the voltage divider circuit is coupled to the working voltage mapping terminal VCC of the primary side controller 840 to receive the working voltage, and the other end of the voltage divider circuit is grounded. The inverting input terminal of the comparator 810 receives the reference voltage VrefA. The output terminal of the comparator 810 generates an undervoltage lockout signal UVLOB. The non-inverting input terminal of the comparator 820 receives the reference voltage Vref1. The coupling relationship and functions of the comparators 810 and 820, the P-type transistors MP, the resistors R11 and R12, the valley detection circuit 830, the conduction time control circuit 840, the set reset trigger 850 and the buffer 860 are as follows: Figure 6 The corresponding circuit structures are similar.

[0122] In the third embodiment, in the standby mode, the transformer coil outside the primary controller 840 will naturally make the working voltage vcc of the primary controller 840 fall to a lower voltage value, so the working voltage of the primary controller 840 itself will naturally drop, and the primary controller 840 of this embodiment can still work normally when the voltage value of its working voltage drops below the minimum voltage UVLO, thereby causing the voltage value of the driving signal drv generated by the primary controller 840 to naturally decrease. In this way, this embodiment can be implemented without the mode selection circuit 542 and the mode-type undervoltage lockout circuit 544 and the driving amplitude adjustment circuit 546 in the second embodiment. The selection circuit for multiple reference voltages can also be implemented.

[0123] In summary, the transformer device and the driving circuit for the transformer device described in the embodiment of the present invention use the load detection signal and the zero voltage detection signal to determine whether the current working mode of the driving circuit is a heavy load mode, a light load mode or a standby mode, and then adjust the amplitude and frequency of the PWM signal in the driving signal accordingly according to these working modes. In detail, in the heavy load mode, the amplitude and frequency of the PWM signal in the driving signal are normal, and the working voltage of the driving circuit is not adjusted. In the light load mode, the amplitude of the PWM signal in the driving signal will be lowered, and the frequency of the PWM signal can also be reduced to reduce the switching loss of the power switch. In addition, the working voltage of the driving circuit can also be slightly lowered in the light load mode, thereby reducing the static power consumption of the driving circuit. In the standby mode, in addition to the working voltage of the driving circuit being reduced, the PWM signal in the driving signal is also stopped to avoid the switching loss of the power switch. Thereby, the transformer device and the driving circuit of the present embodiment can further save power consumption.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transformer device, characterized in that: include: AC input terminal, providing AC voltage; A bridge rectifier circuit converts the AC voltage into a first voltage; A high-voltage frequency conversion circuit includes a primary winding, a secondary winding and an auxiliary winding; A power switch circuit coupled to the primary winding, wherein the power switch circuit is controlled by a driving signal, and the high-voltage frequency conversion circuit converts the first voltage into a DC voltage according to the primary winding, the secondary winding and the power switch circuit; An optical coupling circuit generates a load detection signal according to the DC voltage; A zero voltage and working voltage divider circuit provides a zero voltage detection signal according to the auxiliary winding mapping a working voltage proportional to the output voltage; as well as A primary side controller is coupled to the optical coupling circuit and the power switch circuit, the primary side controller operates according to the operating voltage, and The primary side controller sets the primary side controller to one of a plurality of working modes according to the load detection signal and the zero voltage detection signal, and correspondingly adjusts the amplitude and frequency of the pulse width modulation signal in the driving signal according to the set working mode. The working modes at least include a first load mode, a second load mode and a standby mode.

2. The transformer device according to claim 1, wherein when the set working mode is the standby mode, the frequency and amplitude of the pulse width modulation signal generated by the primary controller are lower than those of the first load mode and the second load mode, The amplitude of the adjusted pulse width modulated signal corresponding to the first load mode is greater than the amplitude of the adjusted pulse width modulated signal corresponding to the second load mode, and the frequency of the adjusted pulse width modulated signal corresponding to the first load mode is higher than or equal to the frequency of the adjusted pulse width modulated signal corresponding to the second load mode.

3. The transformer device according to claim 1, wherein the primary side controller comprises: A load detection terminal, receiving the load detection signal; A zero voltage detection terminal, receiving the zero voltage detection signal; A working voltage mapping terminal, receiving the working voltage; a mode selection circuit, which compares the load detection signal with a load threshold to generate a first detection signal, compares the zero voltage detection signal with a system power threshold to generate a second detection signal, and generates a mode selection signal according to the first detection signal and the second detection signal; a mode-type undervoltage lockout circuit, coupled to the mode selection circuit, selecting one of a plurality of first reference voltages to be selected as a first reference voltage according to the mode selection signal, and comparing the first reference voltage with a voltage-divided signal corresponding to the working voltage to generate an undervoltage lockout signal; a driving amplitude adjustment circuit coupled to the mode selection circuit, selecting one of a plurality of second reference voltages to be selected as a second reference voltage according to the mode selection signal, and determining the amplitude of the pulse width modulation signal in the driving signal according to the second reference voltage and the working voltage; A driving frequency adjustment circuit is coupled to the mode-type under-voltage lockout circuit, and determines the frequency of the pulse width modulation signal in the driving signal according to the load detection signal, the zero voltage detection signal and the under-voltage lockout signal; as well as A buffer, wherein a power supply terminal of the buffer is coupled to the output terminal of the driving amplitude adjustment circuit, and an input terminal of the buffer is coupled to the output terminal of the driving frequency adjustment circuit, for generating the pulse width modulation signal.

4. The transformer device according to claim 3, wherein the primary side controller further comprises: a current detection terminal, used to obtain a voltage detection signal generated by detecting the current flowing through the power switch in the power switch circuit from the current detection circuit, The driving frequency adjustment circuit determines the frequency of the pulse width modulation signal in the driving signal according to the load detection signal, the zero voltage detection signal, the under-voltage lockout signal and the voltage detection signal.

5. The transformer device according to claim 3, wherein the mode selection circuit comprises: a first detector, wherein a first input terminal of the first detector receives the load detection signal, a second input terminal of the first detector receives the load threshold, and an output terminal of the first detector generates the first detection signal; Sample and hold circuit; A timer coupled to the sample-and-hold circuit, wherein the sample-and-hold circuit receives and maintains the zero voltage detection signal according to a signal of the timer to generate a sampled-and-held signal; a second detector, wherein a first input terminal of the second detector receives the sample-and-hold signal, a second input terminal of the second detector receives the system power threshold, and an output terminal of the second detector generates the second detection signal; as well as A first AND gate, wherein a first input terminal of the first AND gate receives the first detection signal, a second input terminal of the first AND gate receives the second detection signal, and an output terminal of the first AND gate generates the mode selection signal.

6. The transformer device according to claim 3, wherein the mode-type undervoltage lockout circuit comprises: A first multiplexer, wherein an input terminal of the first multiplexer receives the first reference voltage to be selected respectively, a control terminal of the first multiplexer receives the mode selection signal, and an output terminal of the first multiplexer provides the first reference voltage; a first voltage divider circuit, wherein an input terminal of the first voltage divider circuit is coupled to the working voltage, and an output terminal of the first voltage divider circuit generates the divided voltage signal; as well as A first comparator, a non-inverting input terminal of the first comparator receives the divided voltage signal, an inverting input terminal of the first comparator is coupled to the output terminal of the first multiplexer to receive the first reference voltage, and an output terminal of the first comparator provides the undervoltage lockout signal.

7. The transformer device according to claim 3, wherein the drive amplitude adjustment circuit comprises: a second multiplexer, wherein the input terminals of the second multiplexer respectively receive the second reference voltage to be selected, the control terminal of the second multiplexer receives the mode selection signal, and the output terminal of the second multiplexer provides the second reference voltage; a second amplifier, wherein an inverting input terminal of the second amplifier is coupled to the output terminal of the second multiplexer to receive the second reference voltage; A P-type transistor, a control end of the P-type transistor is coupled to the output end of the second amplifier, a first end of the P-type transistor receives the working voltage, and a second end of the P-type transistor serves as the output end of the driving amplitude adjustment circuit; a first resistor, wherein a first end of the first resistor is coupled to the second end of the P-type transistor, and a second end of the first resistor is coupled to a non-inverting input end of the second amplifier; as well as A second resistor, wherein a first end of the second resistor is coupled to the second end of the first resistor and the non-inverting input end of the second amplifier, and a second end of the second resistor is grounded.

8. The transformer device according to claim 4, wherein the driving frequency adjustment circuit comprises: A valley detection circuit, wherein an input end of the valley detection circuit receives the zero voltage detection signal; A conduction time control circuit, wherein a first input terminal of the conduction time control circuit receives the load detection signal, and a second input terminal of the conduction time control circuit receives the voltage detection signal; A set reset trigger, wherein a set terminal of the set reset trigger is coupled to the output terminal of the valley detection circuit, and a reset terminal of the set reset trigger is coupled to the output terminal of the on-time control circuit; as well as A second AND gate, wherein a first input terminal of the second AND gate is coupled to the output terminal of the set reset trigger, a second input terminal of the second AND gate receives the undervoltage lockout signal, and an output terminal of the second AND gate generates a waveform of the pulse width modulation signal in the driving signal.

9. The transformer device according to claim 1, wherein the output end of the auxiliary winding is coupled to the working voltage mapping end of the primary controller, and the auxiliary winding provides the working voltage to the working voltage mapping end of the primary controller through the high-frequency voltage transformation circuit. The input end of the zero voltage and working voltage voltage divider circuit is coupled to the output end of the auxiliary winding.

10. A driving circuit for driving a transformer device, characterized in that: The driving circuit comprises: A load detection terminal obtains a load detection signal; A zero voltage detection terminal for obtaining a zero voltage detection signal; A working voltage mapping terminal for obtaining a working voltage, wherein the driving circuit operates according to the working voltage; a mode selection circuit, which compares the load detection signal with a load threshold to generate a first detection signal, compares the zero voltage detection signal with a system power threshold to generate a second detection signal, and generates a mode selection signal according to the first detection signal and the second detection signal; a mode-type undervoltage lockout circuit, coupled to the mode selection circuit, selecting one of a plurality of first reference voltages to be selected as a first reference voltage according to the mode selection signal, and comparing the first reference voltage with a voltage-divided signal corresponding to the working voltage to generate an undervoltage lockout signal; a driving amplitude adjustment circuit coupled to the mode selection circuit, selecting one of a plurality of second reference voltages to be selected as a second reference voltage according to the mode selection signal, and determining an amplitude of a pulse width modulation signal in a driving signal according to the second reference voltage and the working voltage, wherein the driving signal is used to drive a power switch in the transformer device; a driving frequency adjustment circuit coupled to the mode-type under-voltage lockout circuit, and determining the frequency of the pulse width modulation signal in the driving signal according to the load detection signal, the zero voltage detection signal and the under-voltage lockout signal; and A buffer, wherein a power supply end of the buffer is coupled to the output end of the driving amplitude adjustment circuit, an input end of the buffer is coupled to the output end of the driving frequency adjustment circuit, and the buffer is used to generate the pulse width modulation signal in the driving signal.

11. The driving circuit according to claim 10, further comprising: a current detection terminal, used to obtain a voltage detection signal generated by detecting the current flowing through the power switch, The driving frequency adjustment circuit determines the frequency of the pulse width modulation signal in the driving signal according to the load detection signal, the zero voltage detection signal, the under-voltage lockout signal and the voltage detection signal.

12. The driving circuit according to claim 10, wherein the mode selection circuit comprises: a first detector, wherein a first input terminal of the first detector receives the load detection signal, a second input terminal of the first detector receives the load threshold, and an output terminal of the first detector generates the first detection signal; Sample and hold circuit; A timer coupled to the sample-and-hold circuit, wherein the sample-and-hold circuit receives and maintains the zero voltage detection signal according to a signal of the timer to generate a sampled-and-held signal; a second detector, wherein a first input terminal of the second detector receives the sample-and-hold signal, a second input terminal of the first detector receives the system power threshold, and an output terminal of the second detector generates the second detection signal; as well as A first AND gate, wherein a first input terminal of the first AND gate receives the first detection signal, a second input terminal of the first AND gate receives the second detection signal, and an output terminal of the first AND gate generates the mode selection signal.

13. The driving circuit according to claim 10, wherein the mode-type under-voltage lockout circuit comprises: A first multiplexer, wherein an input terminal of the first multiplexer receives the first reference voltage to be selected respectively, a control terminal of the first multiplexer receives the mode selection signal, and an output terminal of the first multiplexer provides the first reference voltage; a first voltage divider circuit, wherein an input terminal of the first voltage divider circuit is coupled to the working voltage, and an output terminal of the first voltage divider circuit generates the divided voltage signal; as well as A first comparator, a non-inverting input terminal of the first comparator receives the divided voltage signal, an inverting input terminal of the first comparator is coupled to the output terminal of the first multiplexer to receive the first reference voltage, and an output terminal of the first comparator provides the undervoltage lockout signal.

14. The driving circuit according to claim 10, wherein the driving amplitude adjustment circuit comprises: a second multiplexer, wherein the input terminals of the second multiplexer respectively receive the second reference voltage to be selected, the control terminal of the second multiplexer receives the mode selection signal, and the output terminal of the second multiplexer provides the second reference voltage; a second amplifier, wherein an inverting input terminal of the second amplifier is coupled to the output terminal of the second multiplexer to receive the second reference voltage; A P-type transistor, a control end of the P-type transistor is coupled to the output end of the second amplifier, a first end of the P-type transistor receives the working voltage, and a second end of the P-type transistor serves as the output end of the driving amplitude adjustment circuit; a first resistor, wherein a first end of the first resistor is coupled to the second end of the P-type transistor, and a second end of the first resistor is coupled to a non-inverting input end of the second amplifier; as well as A second resistor, wherein a first end of the second resistor is coupled to the second end of the first resistor and the non-inverting input end of the second amplifier, and a second end of the first resistor is grounded.

15. The driving circuit according to claim 10, wherein the driving frequency adjustment circuit comprises: A valley detection circuit, wherein an input end of the valley detection circuit receives the zero voltage detection signal; A conduction time control circuit, wherein a first input terminal of the conduction time control circuit receives the load detection signal, and a second input terminal of the conduction time control circuit receives the voltage detection signal; A set reset trigger, wherein a set terminal of the set reset trigger is coupled to the output terminal of the valley detection circuit, and a reset terminal of the set reset trigger is coupled to the output terminal of the on-time control circuit; as well as A second AND gate, wherein a first input terminal of the second AND gate is coupled to the output terminal of the set reset trigger, a second input terminal of the second AND gate receives the undervoltage lockout signal, and an output terminal of the second AND gate generates a waveform of the pulse width modulation signal in the driving signal.

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