Dead-time adjustment method, adaptive zvs control method and switching power supply

Abstract

The application provides a dead time adjusting method, an adaptive ZVS control method and a switching power supply, comprising the following steps: 11) obtaining a first time length, collecting a second time length of a current period, and comparing the first time length with the second time length; 12) if the first time length is greater than the second time length, reducing the conduction time of a clamping tube by a preset time length in the next period; if the first time length is less than the second time length, increasing the conduction time of the clamping tube by the preset time length in the next period; if the first time length is equal to the second time length, keeping the conduction time of the clamping tube in the next period; and 13) returning to step 11) to adjust the dead time between the clamping tube and the main switch in each period. The application can accurately realize adaptive control of the dead time between the upper clamping tube and the main switch tube in a full load range, has high safety, small loss of the main switch tube, high system efficiency, and wide application range.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a dead time adjusting method, an adaptive ZVS control method and a switching power supply. BACKGROUND

[0002] In a transformer-based switching power supply, due to the existence of transformer leakage inductance, the drain end of the primary side power switch tube bears a large switching stress. Therefore, in engineering, a leakage inductance absorption circuit is often used to recover the energy in the leakage inductance and reduce the switching stress borne by the drain end of the power switch tube. Commonly used leakage inductance recovery circuits mainly include RCD (resistor, capacitor, diode) clamping circuits, LCD (inductor, capacitor, diode) clamping circuits and active clamping circuits, etc. Among them, the active clamping circuit uses active elements to have a lower on-resistance and better switching characteristics, recovers the leakage energy, reduces the stress of the main power tube, and further reduces the loss of the clamping circuit. Therefore, compared with passive clamping switching power supplies, active clamping switching power supplies can achieve higher efficiency and higher switching frequency; since the energy in the leakage inductance is absorbed, there is no leakage inductance spike during the opening of the main power tube, the input voltage range is wider, and the EMI noise is smaller; in addition, the wide application of third-generation GaN semiconductor power devices also promotes the ACF switching power supply to develop in the direction of smaller size and higher power density.

[0003] However, the dead time between the early clamping tube and the main switch tube is fixed and has no adjustability, which can easily cause the system to fail to achieve ZVS (zero voltage start) control in the full load range, resulting in energy loss of the switch tube. For this, the existing technology adjusts and calculates the dead time according to the input and output voltages and parasitic capacitances. Due to the particularity and complexity of the parasitic capacitances, the specific capacitance value cannot be accurately obtained, so the calculated dead time is not very accurate, and there is a risk of simultaneous conduction of the clamping tube and the main switch tube.

[0004] Therefore, how to reduce the energy loss of the switch tube and improve the accuracy of zero voltage start control has become one of the problems to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide a dead time adjusting method, an adaptive ZVS control method and a switching power supply, which are used to solve the problems in the prior art that the dead time cannot be accurately controlled, the adjustable range of the dead time is too narrow, the ZVS on control cannot be realized in the full load range, the main switch tube loss is more with the increase of the system working frequency, the system efficiency cannot reach the ideal value, and the development of the active clamp zero voltage switching is restricted.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a dead time adjusting method applied to an active clamp converter, which at least comprises:

[0008] Step 11) obtaining the calculated first duration and collecting the second duration of the current cycle, and comparing the first duration with the second duration; the first duration is a preset dead time duration from the turn-off of the clamp tube in the active clamp converter to the turn-on of the main switch tube, and the second duration is a duration from the turn-off of the clamp tube to the complete release of the transformer secondary side inductor current;

[0009] Step 12) if the first duration is greater than the second duration, reducing the turn-on time of the clamp tube by a preset duration in the next cycle; if the first duration is less than the second duration, increasing the turn-on time of the clamp tube by a preset duration in the next cycle; if the first duration is equal to the second duration, maintaining the turn-on time of the clamp tube in the next cycle;

[0010] Step 13) returning to step 11) to adjust the dead time between the clamp tube and the main switch in each cycle.

[0011] Optionally, the turn-off time of the clamp tube is obtained based on the driving signal of the clamp tube, and a first timing end signal is triggered when the turn-off duration of the clamp tube reaches the first duration.

[0012] Optionally, the turn-off time of the clamp tube is obtained based on the driving signal of the clamp tube, and a first timing end signal is triggered when the turn-off duration of the clamp tube reaches the first duration.

[0013] More optionally, the order of arrival of the first timing end signal and the second timing end signal is judged to determine the size relationship between the first duration and the second duration.

[0014] To achieve the above-mentioned purpose and other related purposes, the present application further provides an adaptive ZVS control method, which at least comprises:

[0015] Step 21) circuit soft start, the on-off of the main switch tube and the clamping tube is controlled based on the feedback signal of the active clamping converter, the main switch tube and the clamping tube are complementary conduction;

[0016] Step 22) after the soft start, the on time of the clamping tube is adjusted based on the above dead time adjustment method, and then the first time length is adaptively adjusted, adaptive zero voltage opening control is realized, wherein the main switch tube is turned on after the off time of the clamping tube in the current period reaches the set first time length and the zero voltage detection signal is valid.

[0017] Optionally, when the output voltage of the active clamping converter is stable, it is determined that the soft start is completed.

[0018] Optionally, when the output current of the active clamping converter reaches a limited threshold, the main switch tube is turned off.

[0019] More optionally, after the main switch tube is turned off for a set time length, the clamping tube is turned on.

[0020] To achieve the above object and other related objects, the application further provides a switching power supply, which comprises an active clamping converter, and the active clamping converter realizes adaptive zero voltage opening control by using the above dead time adjustment method.

[0021] Optionally, the active clamping converter is a flyback topology structure or a forward topology structure.

[0022] As described above, the dead time adjustment method, the adaptive ZVS control method and the switching power supply of the application have the following beneficial effects:

[0023] 1) The dead time adjustment method, the adaptive ZVS control method and the switching power supply of the application can accurately realize adaptive control of the dead time between the clamping tube and the main switch tube, so that the main switch tube can realize adaptive ZVS control, the dead time has a wider adjustable range, the adaptive adjustment of ZVS in the full load range of the system is realized, the safety is high, the loss of the main switch tube is small, and the system efficiency is high.

[0024] 2) The dead time adjustment method and the adaptive ZVS control method of the application are suitable for flyback and forward active clamping converters, and have a wide application range. DETAILED DESCRIPTION

[0025] Figure 1 The structure schematic diagram of the active clamping flyback converter is shown.

[0026] Figure 2 The control working waveform diagram of the active clamping flyback converter is shown.

[0027] Figure 3 A flow chart showing the dead-time adjusting method of the present application.

[0028] Figure 4 A structure diagram showing the adaptive zero-voltage turn-on control module of the present application.

[0029] Figure 5 A specific circuit diagram showing the adaptive zero-voltage turn-on control module of the present application.

[0030] Figure 6 A flow chart showing the adaptive ZVS control method of the present application.

[0031] Figure 7 A key node waveform diagram showing the adaptive ZVS control method of the present application.

[0032] Figure 8 A structure diagram showing the driving circuit of the present application.

[0033] Element number explanation

[0034] 1 active clamp flyback converter

[0035] 2 driving circuit

[0036] 21 adaptive zero-voltage turn-on control module

[0037] 211 timing unit

[0038] 212 time length collecting unit

[0039] 212a controller

[0040] 212b frequency divider

[0041] 212c counter

[0042] 213 comparison unit

[0043] 213a comparison subunit

[0044] 214 dead-time adjusting unit

[0045] 214a adjusting subunit

[0046] 22 power-on reset module

[0047] 23 logic control module

[0048] 24 oscillator DETAILED DESCRIPTION

[0049] Following, the embodiments of the present application will be described in details by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of this specification. The present application can also be implemented or applied by other different embodiments, and the details in this specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0050] Please refer to Figures 1-8 . It is to be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complicated.

[0051] As shown in Figure 1 , it is a schematic diagram of an active clamp flyback converter 1, in which Nc is a clamp tube, N0 is a main switch tube, R1 is a clamp resistor, C RD is a clamp capacitor, T is a transformer, Rs is a sampling resistor, Do is a secondary rectifier diode, R L is a load, Co is an output capacitor, Ceq is a drain-source equivalent capacitor of the main switch tube, Coss is a parasitic capacitor of the main switch tube, and C3 is a parasitic capacitor of the clamp tube. In order to achieve ZVS control, a control mode of complementary conduction of the main switch tube N0 and the clamp tube Nc is usually adopted, as shown in Figure 2 , it is a control working waveform diagram of the active clamp flyback converter 1. In the active clamp flyback converter, the main switch tube N0 can be controlled to be turned on and turned off according to its drain-source voltage V DS and output power. After the main switch tube N0 is turned on, the transformer primary inductor current i m flows through the main switch tube N0 (denoted as I P ), showing a linear increasing trend. When the output current sampling signal reaches a preset reference value (which can be adjusted and corresponds to different values in different stages), the control system turns off the main switch tube N0. The energy stored in the transformer primary inductor L M is coupled to the secondary side at once, and the clamp tube Nc is turned on after a delay TDP_C after the main switch tube N0 is turned off (at this time, the drain-source voltage V DS of the main switch tube N0 is Vin+mVo, where Vin is the input voltage, Vo is the output voltage, and m is the turns ratio of the primary winding to the secondary winding in the transformer). After the clamp tube Nc is turned on, the energy in the drain inductor can be recovered through the clamp resistor R1 and the clamp capacitor C RD . The current of the transformer primary inductor L M flows through the clamp tube Nc, and at this time the transformer primary inductor current is denoted as i clampBecause the clamping transistor Nc is open, the transformer primary inductor current i m The voltage drops momentarily, but due to the parasitic capacitance between the drain and source of the main switch N0, the transformer capacitance, and the capacitance of the secondary rectifier diode Do, the primary inductor current i of the transformer is reduced. m There will be an increasing process. Based on the above analysis, in order to achieve ZVS control, the following zero-voltage turn-on conditions need to be met:

[0052]

[0053] Among them, i clamp- direction and i clamp The specified currents are opposite in direction and equal in magnitude; i m- direction and i m The specified currents are in opposite directions but equal in magnitude; due to leakage inductance L K The leakage inductance is very small, and some of the leakage inductance energy has already been recovered, so formula (1) no longer considers the leakage inductance energy. From the above formulas, it can be seen that the equivalent capacitance Ceq of the drain-source of the main switch N0 and the clamping capacitance C are needed. RD And the parasitic capacitance between the drain and source of the clamping transistor Nc needs to be discharged until the ZVS signal is detected. Therefore, in order to achieve ZVS control, the clamping transistor Nc needs to be... C The turn-on time is continuously and adaptively adjusted to adjust the dead time between the clamping transistor being turned off and the main switch being turned on (other active clamping converters also have the above problem).

[0054] like Figure 3 As shown, this invention provides a dead-time adjustment method applied to an active clamp converter, used to adjust the dead time between the clamping transistor and the main switching transistor. The dead-time adjustment method includes:

[0055] Step 11) Obtain the calculated first duration T1 and collect the second duration t2 of the current cycle, and compare the first duration T1 with the second duration t2. Wherein, the first duration T1 is the duration from the clamping transistor N in the active clamp converter. C The preset dead time between the shutdown and the start of the main switch N0, and the second time t2 is the time from the start of the clamping switch N0. C The time from when the transformer is turned off until the inductor current on the secondary side is completely released.

[0056] Step 12) If the first duration T1 is greater than the second duration t2, then in the next cycle, the conduction time T of the clamping transistor Nc will be reduced. H_ON Reduce the preset duration Δt. If the first duration T1 is less than the second duration t2, then reduce the conduction time T of the clamping transistor Nc in the next cycle. H_ONincreasing the preset time length Δt. If the first time length T1 is equal to the second time length t2, the on time T of the clamp tube Nc is maintained in the next cycle H_ON .

[0057] Step 13) returning to step 11) adjusting the dead time between the clamp tube Nc and the main switch N0 in each cycle in turn.

[0058] Specifically, the first time length T1 of the current cycle is calculated before the clamp tube Nc is turned off in the current cycle, and the actual dead time length of the current cycle needs to be greater than the calculated first time length T1 (i.e. the preset dead time length). As an example, in the initial state, the first time length T1 is determined according to the actual dead time of the previous cycle, and in each subsequent cycle, the first time length T1 (i.e. the preset dead time length) corresponding to each cycle is continuously adjusted through step 2). In this embodiment, the turn-off time of the clamp tube Nc is obtained based on the drive signal PWM_C of the clamp tube Nc, i.e. when the drive signal PWM_C of the clamp tube Nc jumps to low level, a timing start signal is triggered to start timing the first time length T1; when the turn-off time of the clamp tube Nc reaches the (preset) first time length T1, a first timing end signal is triggered.

[0059] Specifically, the second time length t2 of the current cycle is obtained in real time by the acquisition circuit. In this embodiment, the turn-off time of the clamp tube Nc is obtained based on the drive signal of the clamp tube Nc, as above, when the drive signal PWM_C of the clamp tube Nc jumps to low level, a timing start signal is triggered to start timing the second time length t2; when the zero current detection signal ZCD is valid, it is determined that the secondary side inductance current of the transformer is completely released, and a second timing end signal is triggered. The zero current detection signal ZCD can be obtained by detecting the voltage on the auxiliary winding (not shown in the figure); details are not described here. Figure 1

[0060] It should be noted that any method (signal basis) that can obtain the first time length and the second time length is applicable to the present application, and is not limited to this embodiment; including but not limited to, converting the time signal into a voltage signal, and indicating the length of time by the amplitude of the voltage, which is not described here.

[0061] ​Specifically, in the embodiment, the order of arrival of the first timing end signal and the second timing end signal is determined to determine the size relationship between the first time length T1 and the second time length t2. If the first timing end signal arrives earlier than the second timing end signal, it indicates that the first time length T1 is less than the second time length t2; if the first timing end signal arrives later than the second timing end signal, it indicates that the first time length T1 is greater than the second time length t2; if the first timing end signal and the second timing end signal arrive at the same time, it indicates that the first time length T1 is equal to the second time length t2. In actual use, any way that can determine the size relationship between the first time length T1 and the second time length t2 is applicable, which will not be described here. If the zero current detection signal ZCD is sampled to be valid within the first time length T1, it is determined that the first time length T1 is greater than the second time length t2; if the zero current detection signal ZCD is not sampled to be valid within the first time length T1, it is determined that the first time length T1 is less than the second time length t2; if the zero current detection signal ZCD is sampled to be valid at the end of the first time length T1, it is determined that the first time length T1 is equal to the second time length t2.

[0062] Specifically, the on-time T of the clamping tube in the next period is adjusted based on the comparison result of the current period H_ON , and the following relationship is satisfied:

[0063]

[0064] wherein, T H_ON (n+1) is the on-time of the clamping tube in the (n+1)th period, T H_ON (n) is the on-time of the clamping tube in the nth period. It should be noted that the preset time length Δt is not greater than the on-time of the clamping tube. If the accuracy of the adjustment is to be improved, the preset time length Δt is set to a smaller value; if the efficiency of the adjustment is to be improved, the preset time length Δt is set to a larger value. The specific value of the preset time length Δt is set according to actual design needs, as long as the adaptive change of the dead time in each period can be realized. As an example, the preset time length Δt is configured as n working clock periods, and n is a natural number greater than or equal to 1, including but not limited to 1-10.

[0065] As shown in Figure 4 , in the embodiment, the dead time adjustment method of the application is implemented based on an adaptive zero-voltage opening control module 21, and the adaptive zero-voltage opening control module 21 comprises:

[0066] a timing unit 211, a time length acquisition unit 212, a comparison unit 213, and a dead time adjustment unit 214.

[0067] As shown in Figure 4As shown, the timing unit 211 is connected to the output terminal of the dead time adjustment unit 214 and performs timing on the first duration T1 provided by the dead time adjustment unit 214.

[0068] Specifically, in the initial state, the timing unit 211 acquires the first duration T1 based on the zero-voltage detection signal ZVS. At this time, the first duration T1 is the duration from the clamping transistor being turned off to the main switch being turned on (actual measured value). Subsequently, the timing unit 211 acquires the continuously updated first duration T1 (calculated preset value) based on the dead-time adjustment unit 214. In this embodiment, the timing unit 211 is implemented using a timer. The count value of the timer is set based on the first duration T1. The timer starts counting from the time the clamping transistor is turned off. When the count value is reached, it is determined that the first duration T1 has ended, and a corresponding count end signal is output (for example, high level is active). As the dead-time adjustment unit 214 continuously adjusts the first duration T1, the set count value of the timer is also continuously updated.

[0069] It should be noted that any circuit structure capable of timing the first duration T1 and outputting a corresponding signal is applicable to the present invention, and is not limited to this embodiment.

[0070] like Figure 4 As shown, the duration acquisition unit 212 acquires the duration from the turn-off of the clamping transistor in the active clamping converter to the complete release of the transformer secondary inductor current, thus obtaining the second duration t2. Figure 5 As shown, in this embodiment, the duration acquisition unit 212 includes a controller 212a, a frequency divider 212b, and a counter 212c.

[0071] Specifically, such as Figure 5 As shown, in this embodiment, the controller 212a receives the drive signal PWM_C of the clamping transistor and the zero-current detection signal ZCD. When the clamping transistor is turned off, a timing start signal is triggered; when the zero-current detection signal ZCD is valid, a timing end signal is triggered. As an example, the controller 212a is implemented using an RS flip-flop. The set terminal s of the RS flip-flop is connected to the drive signal PWM_C of the clamping transistor, and the reset terminal is connected to the zero-current detection signal ZCD. It outputs control signals for timing start and end. When the drive signal PWM_C of the clamping transistor goes low, the output signal CTR of the RS flip-flop goes high (i.e., the timing start signal); when the zero-current detection signal ZCD is valid at a high level, the output signal CTR of the RS flip-flop goes low (i.e., the timing end signal). In practical use, any circuit structure that satisfies the above logic is applicable to this invention and is not limited to this embodiment.

[0072] Specifically, such as Figure 5 As shown, in this embodiment, the frequency divider 212b is connected to the output terminal of the controller 212a and receives the working clock OSC. When the timing start signal is valid, the working clock OSC is sequentially processed by 2... i The frequency is divided by a factor of 2 to obtain the counting clock; where i = 1, 2...n, and n is the number of bits in the output signal of the duration acquisition unit 212, set to a natural number greater than 2, and can be set to the appropriate value as needed in actual use. As an example, the frequency divider 212b includes n cascaded D flip-flops, the data input terminal D of each D flip-flop is connected to the inverting output terminal Q-, and the non-inverting output terminal Q+ outputs the frequency division signal, wherein the first stage D flip-flop outputs a frequency division signal of 2clk by 2, the second stage D flip-flop outputs a frequency division signal of 4clk by 4, and so on, with the nth stage D flip-flop outputting 2clk by 4clk. n Frequency division signal 2 n clk; The clock input clk of the first-stage D flip-flop is connected to the operating clock OSC, and the clock input clk of the subsequent-stage D flip-flop is connected to the inverted output Q- of the preceding-stage D flip-flop; The asynchronous reset input Clr of the first-stage D flip-flop is connected to the output of the controller 212a, and the asynchronous reset input Clr of the second to nth-stage D flip-flops is connected to the inverted signal ZCD_N of the zero-current detection signal; When the output signal CTR of the RS flip-flop jumps to a high level and the inverted signal ZCD_N of the zero-current detection signal is high, the frequency divider 212b starts frequency division; When the output signal CTR of the RS flip-flop jumps to a low level and the inverted signal ZCD_N of the zero-current detection signal is low, the frequency divider 212b is reset; In practical use, any circuit structure that can satisfy the above logic is applicable to this invention, and is not limited to this embodiment.

[0073] Specifically, such as Figure 5 As shown, in this embodiment, the counter 212c is connected to the output terminals of the controller 212a and the frequency divider 212b. When the timing start signal is valid, timing begins based on the counting clock; when the timing end signal is valid, timing stops. As an example, the counter 212c includes n cascaded D flip-flops. The asynchronous reset terminal Clr of each D flip-flop is connected to the delayed signal CTR_D of the controller output signal, and the clock terminal of the i-th D flip-flop is connected to the 2... i The counting clock is divided by a factor of two (i.e., the clock input of the first-stage D flip-flop receives a frequency divided by two, 2clk; the clock input of the second-stage D flip-flop receives a frequency divided by four, 4clk; and so on, with the clock input of the nth-stage D flip-flop receiving 2clk). n Frequency division signal 2 nclk); the data input end D of the first-stage D flip-flop is connected with the preset voltage LV, and the data input end D of the rear-stage D flip-flop is connected with the positive-phase output end Q+ of the front-stage D flip-flop; the inverted-phase output end Q- of each D flip-flop outputs the timing result, and each D flip-flop outputs one bit signal (t 2_DET1 , t 2_DET2 …t 2_DETn ), and n-bit signals constitute the timing result (as an example, high level is valid); when the delay signal CTR_D of the controller output signal jumps to high level and the corresponding counting clock is received, the counter 212c starts counting; when the delay signal CTR_D of the controller output signal jumps to low level or the corresponding counting clock is not received, the counter 212c stops working; in actual use, any circuit structure meeting the above logic is applicable to the present application, and the present embodiment is not limited.

[0074] As shown in Figure 4 , the comparison unit 213 is connected to the output ends of the timing unit 211 and the time length acquisition unit 212, and compares the first time length T1 with the second time length t2.

[0075] Specifically, as shown in Figure 5 , in the present embodiment, the comparison unit 213 includes n comparison sub-units 213a, and each comparison sub-unit 213a includes an exclusive OR gate XOR, a first NAND gate nand1, a second NAND gate nand2 and a third NAND gate nand3. The input ends of the exclusive OR gate XOR are respectively connected with the output signal of the timing unit 211 and the corresponding bit output signal (respectively denoted as t 2_DET1 , t 2_DET2 …t 2_DETn), the input end of the first NAND gate nand1 is connected with the corresponding bit output signal of the timer 212c and the output signal of the XOR gate respectively, and outputs the first comparison result (P11, P12…P1n respectively); the input end of the second NAND gate nand2 is connected with the output signal of the timing unit 211 and the output signal of the XOR gate respectively, and outputs the second comparison result (P21, P22…P2n respectively); the input end of the third NAND gate nand3 is connected with the output signal of the timing unit 211 and the corresponding bit output signal of the timer respectively, and outputs the third comparison result (P31, P32…P3n respectively); wherein, when the time length represented by the corresponding bit output signal of the timer 212c is less than the first time length T1, the first comparison result of the corresponding comparison subunit 213a jumps to low level; when the time length represented by the corresponding bit output signal of the timer 212c is greater than the first time length T1, the second comparison result of the corresponding comparison subunit 213a jumps to low level; when the time length represented by the corresponding bit output signal of the timer 212c is equal to the first time length T1, the third comparison result of the corresponding comparison subunit 213a jumps to low level; in this example, taking the nth comparison unit 213a as an example, the first time length T1 and the nth bit output signal t 2_DETn Who is high level, that is, who comes first, and then the time is short; the first time length T1 and the second time length t2 which one is long and which one is short can be known by comprehensively considering the comparison results P11, P12…P1n, P21, P22…P2n, P31, P32…P3n. The corresponding truth table is as follows:

[0076] T1 [CAT 2_DETn ]] XOR output P1n P2n P3n 0 0 0 1 1 1 0 1 1 0 1 1 [T1 > t 2_DETn ]] 1 0 1 1 0 1 T1 < t 2DETn ]] 1 1 0 0 0 1 T1 = t 2DETn ]]>

[0077] In actual use, any circuit structure capable of comparing two signals representing time lengths and obtaining comparison results is applicable to the present application, and is not limited to the embodiment.

[0078] As Figure 4 shown, the dead time adjustment unit 214 is connected to the output end of the comparison unit 213, adjusts the conduction time of the clamping tube and the first time length in the next period based on the comparison result of the current period, and further realizes adaptive zero-voltage opening control.

[0079] Specifically, as Figure 5As shown in the embodiment, the dead time adjusting unit 214 includes a time adjusting subunit 214b and n control subunits 214a, each of which is connected to the output end of each comparison subunit 213a. Each control subunit 214a includes a first enable tube M1, a second enable tube M2, a third enable tube M3, a first transistor M4, a second transistor M5, and a third transistor M6. One end of each enable tube is connected to a preset voltage LV, and the other end is connected to the control end of each transistor. When the enable signal T SSE is invalid, each enable tube is turned on to control the turn-off of each transistor, respectively. For example, each enable tube and transistor is a PMOS tube. The first enable tube M1 is connected to the control end of the first transistor M4, the second enable tube M2 is connected to the control end of the second transistor M5, and the third enable tube M3 is connected to the control end of the third transistor M6. When the enable signal T SSE is low (invalid), each enable tube is turned on, and the control end of each transistor is connected to the preset voltage LV (high) to turn off. At this time, the dead time adjusting unit 214 does not work. When the enable signal T SSE is high (valid), each enable tube is turned off, and the control end of each transistor is connected to the corresponding comparison result. At this time, the dead time adjusting unit 214 is in a working state. One end of the first transistor M4 is connected to the preset voltage LV, the control end is connected to the corresponding first comparison result, and the other end generates a control signal for reducing the turn-on time T H_ON of the clamping tube. One end of the second transistor M5 is connected to the preset voltage LV, the control end is connected to the corresponding second comparison result, and the other end generates a control signal for increasing the turn-on time T H_ON of the clamping tube. One end of the third transistor M6 is connected to the preset voltage LV, the control end is connected to the corresponding third comparison result, and the other end generates a control signal for maintaining the turn-on time T H_ON of the clamping tube. When the corresponding comparison result jumps to low, the corresponding transistor is turned on to output the control signal for adjusting the turn-on time of the clamping tube. The time adjusting subunit 214b is connected to the output end of each control subunit 214a and receives the working clock OSC. According to the control signal output by each control subunit 214a, the time adjusting subunit 214b generates a count time using the working clock OSC to adjust the turn-on time T H_ON of the clamping tube.

[0080] It should be noted that, in the embodiment, when the circuit is in a starting stage, the enable signal T SSE is invalid, and the adaptive zero-voltage start control module 21 does not work. When the circuit is started, the enable signal T SSEThe jump is valid, and the adaptive zero-voltage start control module 21 starts to work. In addition, any circuit structure capable of adjusting the conduction time of the clamping tube and the first time length based on the output signal of the comparison unit 213 is applicable to the present application, and is not limited to the present embodiment.

[0081] As shown in Figure 6 The present application also provides an adaptive ZVS control method, which comprises the following steps:

[0082] Step 21) Circuit soft start, control the on-off of the main switch tube and the clamping tube based on the feedback signal of the active clamping converter. The main switch tube and the clamping tube are complementary conduction.

[0083] Specifically, the circuit (i.e. active clamping converter) is powered on, and the conduction and turn-off time of the main switch tube and the clamping tube is adjusted based on the real-time collected feedback signal. In the present embodiment, the feedback signal includes but is not limited to the current sampling signal Vcs of the main switch tube and the zero-voltage detection signal ZVS; wherein the main switch tube N0 is turned on based on the zero-voltage detection signal ZVS; as the circuit starts, the current sampling signal Vcs of the main switch tube gradually increases, the turn-on time of the main switch tube is gradually adjusted based on the comparison result of the current sampling signal Vcs of the main switch tube and the preset value (as an example, the preset value is set as the overcurrent protection point OCP), and the clamping tube Nc is turned on after the main switch tube N0 is turned off for a fixed time. In actual use, any signal and control logic capable of reflecting the working state of the active clamping converter and controlling the complementary conduction of the main switch tube and the clamping tube through feedback is applicable to the present application, and is not limited to the present embodiment. It should be noted that the complementary conduction referred to in the present application means that the main switch tube and the clamping tube are not conduction at the same time, and there is a dead time.

[0084] Specifically, in the present embodiment, when the output voltage of the active clamping converter is stable, it is determined that the soft start is completed; in actual use, any method capable of reflecting the completion of power-on of the active clamping converter can be used to determine the end of soft start.

[0085] Step 22) After the soft start is completed, the conduction time T H_ON of the clamping tube Nc is adjusted based on the dead time adjustment method, and then the first time length T1 is adaptively adjusted, so as to realize adaptive zero-voltage start control; wherein the main switch tube N0 is turned on after the turn-off time of the clamping tube Nc in the current period reaches the set first time length T1 and the zero-voltage detection signal ZVS is valid.

[0086] Specifically, as shown in Figure 7As shown in the figure, in the present embodiment, the main switch tube N0 is turned on when the clamping tube Nc reaches the set first time length T1 at the off time of the current period and the zero voltage detection signal ZVS is valid; if the zero voltage detection signal ZVS is detected within the first time length T1, the main switch tube N0 can be turned on only after the first time length T1; if the zero voltage detection signal ZVS is not detected within the first time length T1, the main switch tube N0 is turned on after the zero voltage detection signal ZVS is detected; if the zero voltage detection signal ZVS is detected at the end of the first time length T1, the main switch tube N0 is turned on when both conditions are met. When the output current of the active clamping converter reaches a limited threshold value (for example, in the circuit start-up stage, the output current is determined to reach the limited threshold value when the output current sampling signal Vcs reaches the overcurrent protection point; after the circuit starts, the output current is determined to reach the limited threshold value when the output current sampling signal Vcs reaches the preset reference value, at which time the output current sampling signal Vcs reaches the maximum value Vcsmax; the values of the limited threshold values in the two stages are different and are set as required), the main switch tube N0 is turned off. After the main switch tube N0 is turned off for a set time length, the clamping tube Nc is turned on. When the on time of the clamping tube Nc reaches the time length obtained by the dead time adjustment method of the present application, the clamping tube Nc is turned off. The first time length T1 and the second time length t2 are counted at the falling edge of the clamping tube Nc being turned off, wherein the first time length T1 is determined based on the on time of the clamping tube Nc in the last period, that is, for the current period, the first time length T1 corresponds to the set value, and the first counting end signal T1_end is obtained by counting to the set value; the second time length t2 is a real-time collected signal, and the second time length t2 is counted to an end when the zero current detection signal ZCD (equivalent to the second counting end signal) is valid in the current period. The on time of the clamping tube Nc in the next period is adjusted based on the comparison result of the first time length T1 and the second time length t2, and the first time length T1 corresponding to the next period is also adjusted accordingly, thereby realizing adaptive zero voltage turn-on control of the main switch tube, and the specific adjustment relationship is described above and will not be described here. In the present example, it is assumed that the zero voltage detection signal ZVS, the zero current detection signal ZCD and the first counting end signal T1_end are all high-level valid, and in actual use, they can also be set to low-level valid, which is not limited by the present embodiment.

[0087] As Figure 8 shown in the figure, in the present embodiment, the adaptive ZVS control method of the present application is realized based on the driving circuit 2 of the present application, which comprises an adaptive zero voltage turn-on control module 21, a power-on reset module 22 and a logic control module 23.

[0088] AsFigure 8 As shown in the figure, the adaptive zero-voltage turn-on control module 21 generates an adjustment of the dead time between the turn-off of the clamping tube and the turn-on of the main switch tube in the next cycle based on the drive signal PWM_C of the clamping tube and the zero-current detection signal ZCD. The structure and working principle of the adaptive zero-voltage turn-on control module 21 are described above and will not be repeated here.

[0089] As shown in the figure, the power-on reset module 22 is used to reset the logic control module 23 when the active clamping converter is powered on. Figure 8

[0090] As shown in the figure, the logic control module 23 is connected to the output terminals of the adaptive zero-voltage turn-on control module 21 and the power-on reset module 22, and receives the zero-voltage detection signal ZVS and the output current sampling signal Vcs of the active clamping converter, for generating the drive signal PWM_C of the clamping tube and the drive signal PWM_P of the main switch tube. The logic control module 23 can switch control the clamping tube and the main switch tube according to different strategies combined with the feedback signals of the active clamping converter, which will not be repeated here. Figure 8

[0091] As shown in the figure, as another implementation manner of the present application, the drive circuit 2 further includes an oscillator 24, which provides a working clock (including at least one frequency clock, different frequency clocks can meet the needs of different circuits) for the drive circuit 2. The purposes of the working clock include but are not limited to counting, adjusting the conduction time of the clamping tube, and adjusting the first time length. The required clock signals in the drive circuit 2 can be provided by the oscillator 24, which will not be repeated here. Figure 8

[0092] The present application also provides a switching power supply, and the active clamping flyback converter adopts the dead time adjustment method of the present application to realize adaptive zero-voltage turn-on control. The active clamping converter includes but is not limited to a flyback topology structure, a forward topology structure, and any active clamping converter structure is applicable, which will not be repeated here. As an example, when the active clamping converter is a flyback topology structure, the circuit structure shown in the figure can be used. Figure 1

[0093] ​​​​In summary, the application provides a dead time adjusting method, an adaptive ZVS control method and a switching power supply, comprising: step 11) obtaining a calculated first time length, collecting a second time length of a current period, and comparing the first time length with the second time length; the first time length is a preset dead time length from the turn-off of a clamping tube in the active clamping converter to the turn-on of a main switch tube, and the second time length is a time length from the turn-off of the clamping tube to the complete release of a transformer secondary side inductor current; step 12) if the first time length is greater than the second time length, reducing the turn-on time of the clamping tube by a preset time length in the next period; if the first time length is less than the second time length, increasing the turn-on time of the clamping tube by a preset time length in the next period; and if the first time length is equal to the second time length, maintaining the turn-on time of the clamping tube in the next period; step 13) returning to step 11) to adjust the dead time between the clamping tube and the main switch in each period. The dead time adjusting method, the adaptive ZVS control method and the switching power supply can accurately realize adaptive control of the dead time between the upper clamping tube and the main switch tube, so that the main switch tube can realize adaptive ZVS control, the dead time has a wider adjustable range, realizes adaptive adjustment of ZVS of the system in the full load range, has high safety, small main switch tube loss and high system efficiency; and the dead time adjusting method and the adaptive ZVS control method are suitable for flyback and forward active clamping converters, and have a wide application range. Therefore, the application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A dead-time adjustment method applied to an active clamp converter, characterized in that, The dead time adjusting method at least comprises: Step 11) obtaining the calculated first time length, collecting the second time length of the current period, and comparing the first time length with the second time length; the first time length is the preset dead time length from the turn-off of the clamping tube to the turn-on of the main switch tube, and the second time length is the time length from the turn-off of the clamping tube to the complete release of the transformer secondary side inductor current; Step 12) if the first time length is greater than the second time length, the turn-on time of the clamping tube is reduced by a preset time length in the next period; if the first time length is less than the second time length, the turn-on time of the clamping tube is increased by a preset time length in the next period; if the first time length is equal to the second time length, the turn-on time of the clamping tube is kept in the next period; Step 13) returning to step 11) to adjust the dead time between the clamping tube and the main switch in each period.

2. The dead-time adjustment method of claim 1, wherein: The turn-off time of the clamping tube is obtained based on the driving signal of the clamping tube, and a first timing end signal is triggered when the turn-off time of the clamping tube reaches the first time length.

3. The dead time adjustment method of claim 2, wherein: The turn-off time of the clamping tube is obtained based on the driving signal of the clamping tube, and a second timing end signal is triggered when the transformer secondary side inductor current is completely released when the zero current detection signal is valid.

4. The dead time adjustment method of claim 3, wherein: The first timing end signal and the second timing end signal are judged according to the order of arrival to determine the size relationship between the first time length and the second time length.

5. A method of adaptive ZVS control, characterized by, The adaptive ZVS control method at least comprises: Step 21) circuit soft start, the turn-on and turn-off of the main switch tube and the clamping tube are controlled based on the feedback signal of the active clamping converter, and the main switch tube and the clamping tube are complementary turned on; Step 22) after the soft start is completed, the turn-on time of the clamping tube is adjusted based on the dead time adjusting method according to any one of claims 1-4, and the first time length is adaptively adjusted to realize adaptive zero voltage opening control; wherein the main switch tube is turned on after the turn-off time of the clamping tube in the current period reaches the set first time length and the zero voltage detection signal is valid.

6. The adaptive ZVS control method of claim 5, wherein: When the output voltage of the active clamping converter is stable, it is determined that the soft start is completed.

7. The adaptive ZVS control method of claim 5, wherein: When the output current of the active clamping converter reaches a limited threshold, the main switch tube is turned off.

8. The adaptive ZVS control method of claim 5 or 7, wherein: After the main switch tube is turned off for a set time length, the clamping tube is turned on.

9. A switching power supply, characterized by The switching power supply comprises an active clamping converter, and the active clamping converter realizes adaptive zero voltage opening control by using the dead time adjusting method according to any one of claims 1-4.

10. The switching power supply of claim 9, wherein: The active clamping converter is a flyback topology structure or a forward topology structure.

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