H-bridge control circuit, loudspeaker drive circuit and pulse oscillation test equipment

Abstract

The embodiment of the invention belongs to the technical field of electronic circuits, and relates to an H-bridge control circuit which comprises a microcontroller, a first phase inverter, a second phase inverter, a third phase inverter and an exclusive-OR gate. The microcontroller is used for generating fundamental frequency square wave pulse signals, and the output end of the microcontroller is connected with the first interface, the first input end of the exclusive-OR gate, the input end of the first phase inverter and the input end of the second phase inverter. The output end of the first phase inverter is respectively connected with the second interface, the input end of the third phase inverter and the second input end of the exclusive-OR gate; the output end of the second phase inverter and the output end of the exclusive-OR gate are connected in parallel and then are connected with the third interface; the output end of the third phase inverter and the output end of the exclusive-OR gate are connected in parallel and then connected with the fourth interface, and the first interface, the second interface, the third interface and the fourth interface are control interfaces of the lower right bridge, the lower left bridge, the upper right bridge and the upper left bridge of the H bridge respectively. According to the technical scheme provided by the invention, the control complexity of the H-bridge circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and more specifically, to an H-bridge control circuit, a speaker driving circuit and a pulse oscillation testing device. Background Art

[0002] The impulse oscillometry (IOS) test is an active lung function test technology based on the forced oscillation technique (FOT). It sends a series of low-frequency sound wave pulses to the subject's respiratory tract, and then analyzes the changes in gas pressure and flow after these pulses pass through the respiratory system, thereby obtaining relevant information about the elasticity, inertia and viscous resistance of the respiratory tract and lung tissue. The main advantage of IOS is that it is easy to operate, non-invasive, and fast, and does not require patients to perform complex breathing movements. Therefore, it is particularly suitable for children, the elderly, or patients who cannot cooperate to complete complex breathing tasks.

[0003] When using iOS technology to measure respiratory resistance, it is usually necessary to measure under multiple frequency excitation. This requires the generation and measurement of multiple single-frequency sine waves, which makes the test process time-consuming. After Fourier transform, the square wave can be decomposed into a combination of multiple single-frequency components. Therefore, if the square wave is used to generate pulse pressure, the test time and number will be significantly reduced. To achieve this, an H-bridge circuit can be used to drive the pulse oscillator generator to generate a square wave signal.

[0004] Among them, the H-bridge circuit is an electronic circuit used to control the direction and speed of motors (such as DC motors and stepper motors). Figure 1 , which shows a schematic diagram of a common H-bridge circuit. The name of the H-bridge circuit comes from the fact that the circuit layout resembles the shape of the letter "H". The H-bridge circuit is usually composed of four switches (which can be transistors, field effect transistors, or mechanical switches), which are connected in a specific way to achieve bidirectional control of the motor. However, the current H-bridge circuit requires four control signals, which leads to the problem of complex control logic. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present application is how to reduce the control logic of the H-bridge circuit. In order to solve the above technical problems, the first aspect of the embodiment of the present application provides an H-bridge control circuit, which adopts the following technical solution: A microcontroller, a first inverter, a second inverter, a third inverter and an XOR gate; The microcontroller is used to generate a baseband square wave pulse signal, and the output end of the microcontroller is respectively connected to a first interface, a first input end of the XOR gate, and input ends of the first inverter and the second inverter, wherein the first interface is a control interface of the lower right bridge of the H-bridge; The output end of the first inverter is connected to the second interface, the input end of the third inverter and the second input end of the XOR gate respectively, and the second interface is the control interface of the lower left bridge of the H bridge; After the output end of the second inverter and the output end of the XOR gate are connected in parallel, they are connected to a third interface, and the third interface is a control interface of the upper right bridge of the H bridge; After the output end of the third inverter and the output end of the XOR gate are connected in parallel, they are connected to a fourth interface, and the fourth interface is a control interface of the upper left bridge of the H bridge.

[0006] In some possible implementations, the H-bridge control circuit further includes: A first buffer, wherein the input end of the first buffer is connected to the output end of the microcontroller, and the output end of the first buffer is respectively connected to the first interface, the first input end of the XOR gate, and the input ends of the first inverter and the second inverter.

[0007] In some possible implementations, the H-bridge control circuit further includes: A pulse width modulation module, a fourth inverter and a fifth inverter; The input end of the pulse width modulation module is connected to the first buffer, and the output end is connected to the input ends of the four inverters and the fifth inverter respectively; The output end of the fourth inverter is connected in parallel with the output end of the second inverter and the output end of the XOR gate, and then connected to the third interface; The output end of the fifth inverter is connected in parallel with the output end of the third inverter and the output end of the XOR gate, and then connected to the fourth interface.

[0008] In some possible implementations, the H-bridge control circuit further includes: a sixth inverter, a seventh inverter, and an eighth inverter; The input end of the sixth inverter is connected to the output end of the XOR gate, and the output end is connected to the input ends of the seventh inverter and the eighth inverter; The output end of the seventh inverter is connected in parallel with the output end of the second inverter and the output end of the fourth inverter, and then connected to the third interface; The output end of the eighth inverter is connected in parallel with the output end of the third inverter and the output end of the fifth inverter, and then connected to the fourth interface.

[0009] In some possible implementations, the H-bridge control circuit further includes: A second buffer is provided between an output terminal of the first buffer and a first input terminal of the XOR gate.

[0010] In some possible implementations, the second buffer includes a first RC buffer circuit.

[0011] In some possible implementations, the second buffer also includes a ninth inverter and a tenth inverter, the first RC buffer circuit, the ninth inverter and the tenth inverter are connected in series in sequence, the input end of the first RC buffer circuit is connected to the output end of the first buffer, and the output end of the tenth inverter is connected to the second input end of the XOR gate.

[0012] In order to solve the above technical problems, the second aspect of the embodiment of the present application further provides a speaker driving circuit, wherein the speaker driving circuit comprises an H-bridge control circuit and an H-bridge circuit as described in the above first aspect and any possible implementation of the first aspect, and the driving interface of the H-bridge circuit is used to connect a speaker.

[0013] In some possible implementations, the speaker driving circuit further includes a second RC buffer circuit, and the second RC buffer circuit is arranged between the control switch of the H-bridge circuit and the driving interface of the H-bridge circuit.

[0014] In order to solve the above technical problems, the third aspect of the embodiment of the present application further provides a pulse oscillation test device, wherein the pulse oscillation test device includes an air circuit component, a respiratory parameter measurement component, a speaker, and a speaker driving circuit as described in the above second aspect and any possible implementation of the second aspect.

[0015] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The H-bridge control circuit of the present application includes a microcontroller, a first inverter, a second inverter, a third inverter and an XOR gate. Specifically, a baseband square wave signal of one channel can be generated by the microcontroller as a control signal of the first interface, and then another three-channel timing is obtained by pure hardware circuit processing of the first inverter, the second inverter and the third inverter, as the control signal of the other three interfaces, and the switching of us level can be realized. Thus, the control of the H-bridge circuit by a single pulse signal can be realized, and the control efficiency is high, simplifying the control logic of the H-bridge circuit. In addition, an XOR gate design is also introduced in the H-bridge control circuit, which further avoids the occurrence of the situation of burning the H-bridge switch caused by the upper and lower bridges on the same side of the H-bridge circuit being turned on in extreme cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the solutions in the present application or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a schematic diagram of an existing H-bridge circuit; Figure 2 A hardware schematic diagram of an embodiment of an H-bridge control circuit of the present application is shown; Figure 3 A hardware schematic diagram of another embodiment of an H-bridge control circuit of the present application is shown; Figure 4 A hardware schematic diagram of another embodiment of an H-bridge control circuit of the present application is shown; Figure 5 A schematic diagram of a specific embodiment of an H-bridge control circuit of the present application is shown; Figure 6 A circuit diagram showing the connection of an H-bridge circuit to a speaker. DETAILED DESCRIPTION

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of this application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0019] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0020] The following is a brief description of some concepts involved in this application.

[0021] Inverter, also known as NOT gate, is a logic gate that implements logical NOT in digital logic. Its main function is to invert the logic state of the input signal. If the input signal is high (usually indicating logic 1), the output signal is low (logic 0); vice versa. In actual digital circuit design, it can be used for signal inversion, timing control, noise suppression, etc.

[0022] ‌Exclusive-OR gate is a digital logic circuit with two inputs and one output, which is used to implement logical exclusive-OR operation. When the levels of the two inputs are different, the output is high level 1; when the levels of the two inputs are the same, the output is low level 0. In other words, if the two inputs are different, the exclusive-OR gate outputs a high level 1; if the two inputs are the same, the output is a low level 0.

[0023] A buffer is a basic electronic component that is mainly used to isolate two parts of a circuit while maintaining signal integrity. The main function of a buffer is to improve the driving capability of the circuit and reduce the impact of the load on the signal source, thereby preventing signal attenuation or distortion. In simple terms, a buffer can be regarded as a "passive" amplifier that does not change the logic value of the signal, but only enhances the driving capability of the signal.

[0024] A microcontroller is a small computer system that integrates a central processing unit (CPU), memory (RAM and ROM), timer, input and output interface (I / O) and other peripherals on a single chip. Microcontrollers are widely used in various embedded systems, such as home appliances, automobiles, industrial automation equipment, consumer electronics, etc.

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0026] In order to solve the above-mentioned technical problems, the present application embodiment provides an H-bridge control circuit. Figure 2 , Figure 2 The hardware principle diagram of an embodiment of an H-bridge control circuit of the present application is shown. The H-bridge control circuit includes: A microcontroller, a first inverter, a second inverter, a third inverter and an XOR gate; The microcontroller is used to generate a baseband square wave pulse signal, and the output end of the microcontroller is respectively connected to a first interface, a first input end of the XOR gate, and input ends of the first inverter and the second inverter, wherein the first interface is a control interface of the lower right bridge of the H-bridge; The output end of the first inverter is connected to the second interface, the input end of the third inverter and the second input end of the XOR gate respectively, and the second interface is the control interface of the lower left bridge of the H bridge; After the output end of the second inverter and the output end of the XOR gate are connected in parallel, they are connected to a third interface, and the third interface is a control interface of the upper right bridge of the H bridge; After the output end of the third inverter and the output end of the XOR gate are connected in parallel, they are connected to a fourth interface, and the fourth interface is a control interface of the upper left bridge of the H bridge.

[0027] In this embodiment, the first interface, the second interface, the third interface and the fourth interface are control interfaces of the control switches of the right lower bridge, the left lower bridge, the right upper bridge and the left upper bridge of the H bridge respectively. Figure 1 As shown, they correspond to Figure 1 The P1, P2, P3 and P4 interfaces are shown.

[0028] The microcontroller can be controlled to generate a baseband square wave pulse signal of a set frequency, and the baseband square wave signal can be used as a control signal of the first interface, and the baseband square wave pulse signal is processed by the first inverter, the second inverter and the third inverter to obtain control signals of the other four interfaces. After being processed by the first inverter, the second inverter and the third inverter, the control signal potentials of the right lower bridge switch and the left upper bridge switch of the H-bridge circuit can be consistent, and the control signal potentials of the left lower bridge switch and the right upper bridge switch can be consistent, thereby realizing the control of the H-bridge circuit by a single pulse signal through the microcontroller.

[0029] In addition, the H-bridge control circuit of this embodiment also adds an XOR gate design to deal with the possible situation where the upper and lower bridge control switches on the same side of the H-bridge circuit are turned on, resulting in a short circuit of the H-bridge.

[0030] Due to the differences of electronic components, in some extreme cases, if at a certain time, the baseband square wave signal and the level signal at the output of the first inverter are both high, and the pulse control signal loaded by the third interface and the fourth interface at that moment is also at a high level, then there will be a risk of the upper and lower bridges on the same side of the H-bridge controlling the switch to be turned on. In this case, after the high levels of the baseband square wave signal and the output of the first inverter are processed by the XOR gate, the output of the XOR gate outputs a low level, and the levels of the third interface and the fourth interface are placed in a low state, thereby avoiding the situation where the upper and lower bridges on the same side are turned on at a high level at the same time, burning the H-bridge switch.

[0031] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The H-bridge control circuit of the present application includes a microcontroller, a first inverter, a second inverter, a third inverter and an XOR gate. Specifically, a baseband square wave signal of one channel can be generated by the microcontroller as a control signal of the first interface, and then another three-channel timing is obtained by pure hardware circuit processing of the first inverter, the second inverter and the third inverter, as the control signal of the other three interfaces, and ns-level switching can be achieved. Thus, the control of the H-bridge circuit by a single pulse signal can be achieved, and the control efficiency is high, simplifying the control logic of the H-bridge circuit. In addition, an XOR gate design is also introduced in the H-bridge control circuit, which further avoids the occurrence of the situation of burning the H-bridge switch caused by the upper and lower bridges on the same side of the H-bridge circuit being turned on in extreme cases.

[0032] In some possible implementations, refer to Figure 2 , the H-bridge control circuit further includes: A first buffer, wherein the input end of the first buffer is connected to the output end of the microcontroller, and the output end of the first buffer is respectively connected to the first interface, the first input end of the XOR gate, and the input ends of the first inverter and the second inverter.

[0033] In this embodiment, since the baseband pulse signal output by the microcontroller may be weak, a first buffer circuit may be introduced to further enhance the driving capability of the baseband pulse signal.

[0034] In some possible implementations, specific reference is made to Figure 3 , Figure 3 The hardware principle diagram of another embodiment of an H-bridge control circuit of the present application is shown. The H-bridge control circuit further includes: A pulse width modulation module, a fourth inverter and a fifth inverter; The input end of the pulse width modulation module is connected to the first buffer, and the output end is connected to the input ends of the four inverters and the fifth inverter respectively; The output end of the fourth inverter is connected in parallel with the output end of the second inverter and the output end of the XOR gate, and then connected to the third interface; The output end of the fifth inverter is connected in parallel with the output end of the third inverter and the output end of the XOR gate, and then connected to the fourth interface.

[0035] In this embodiment, the pulse width modulation module can be composed of a timer chip, and the timer chip, the fourth inverter and the fifth inverter can form a pulse generating circuit, and the pulse width modulation signal output by the timer chip can be loaded on the third interface and the fourth interface, thereby modulating the loop waveform after the first interface and the fourth interface are connected, and modulating the pulse width of the echo waveform after the second interface and the third interface are connected.

[0036] In some possible implementations, specific reference is made to Figure 4 , Figure 4 The hardware principle diagram of another embodiment of an H-bridge control circuit of the present application is shown. The H-bridge control circuit further includes: a sixth inverter, a seventh inverter, and an eighth inverter; The input end of the sixth inverter is connected to the output end of the XOR gate, and the output end is connected to the input ends of the seventh inverter and the eighth inverter; The output end of the seventh inverter is connected in parallel with the output end of the second inverter and the output end of the fourth inverter, and then connected to the third interface; The output end of the eighth inverter is connected in parallel with the output end of the third inverter and the output end of the fifth inverter, and then connected to the fourth interface.

[0037] In this embodiment, the signal at the output end of the XOR gate is loaded onto the third interface and the fourth interface respectively via two inverters connected in series, wherein the two inverters connected in series can enhance the signal and further improve the pulse signal strength outputted by the output end of the XOR gate.

[0038] In some possible implementations, the H-bridge control circuit further includes: A second buffer is provided between an output terminal of the first buffer and a first input terminal of the XOR gate.

[0039] In this embodiment, due to the differences in electronic devices, it is possible that the width of the high-level pulse of the pulse control signal of the third interface and the fourth interface is greater than or delayed than that of the first interface and the second interface. This will cause the upper and lower bridge control switches on the same side of the H-bridge circuit to be turned on when the driving direction of the H-bridge circuit changes.

[0040] For example, assuming that the high-frequency pulse width of the left upper bridge interface control signal is greater than the high-frequency pulse width of the right lower bridge interface control signal, then in the process of switching from the "right lower bridge-left upper bridge" path to the "left lower bridge-right upper bridge" path, the right lower bridge control switch will be closed first and the left upper bridge control switch will not be closed synchronously. If at this time, the left lower bridge control switch can be opened synchronously with the closing of the right lower bridge control switch, then in a short period of time, the left lower bridge control switch and the left upper bridge control switch will both be turned on. This will cause the upper and lower bridges on the left side of the H bridge to be turned on, causing the H bridge circuit to short-circuit, and the excessive current will also cause the control switches of the upper and lower bridges on the left side of the H bridge to burn out.

[0041] Therefore, in this embodiment, a second buffer is also provided between the output end of the first buffer and the first input end of the XOR gate, and the second buffer can delay and buffer the sudden change of the high and low level of the pulse square wave signal output by the first buffer, so that the width of the high level signal becomes relatively wide. In this way, after passing through the XOR gate, the pulse signal output by the output end of the XOR gate becomes narrower than the high level width of the pulse signal of the output end of the second inverter and the third inverter, so that the high level of the pulse square wave signal of the third interface and the fourth interface is narrower than the high level of the pulse square wave signal of the first interface and the second interface. In this way, when the driving direction of the H-bridge is switched, the above situation can be avoided.

[0042] In some possible implementations, the second buffer includes a first RC buffer circuit.

[0043] In this embodiment, the first RC buffer circuit is a simple circuit composed of a resistor (R) and a capacitor (C), which can be used to smooth the baseband square wave signal.

[0044] In some possible implementations, the second buffer also includes a ninth inverter and a tenth inverter, the first RC buffer circuit, the ninth inverter and the tenth inverter are connected in series in sequence, the input end of the first RC buffer circuit is connected to the output end of the first buffer, and the output end of the tenth inverter is connected to the second input end of the XOR gate.

[0045] In this embodiment, the ninth inverter and the tenth inverter connected in series can further enhance the output signal of the second buffer.

[0046] In order to solve the above technical problems, the embodiment of the present application further provides a speaker driving circuit. The speaker driving circuit includes: Figure 2-Figure 4 The H-bridge control circuit and the H-bridge circuit described in the illustrated embodiment and any possible implementation of the above embodiments, the driving interface of the H-bridge circuit is used to connect a speaker.

[0047] In some possible implementations, the speaker driving circuit further includes a second RC buffer circuit, and the second RC buffer circuit is arranged between the control switch of the H-bridge circuit and the driving interface of the H-bridge circuit.

[0048] In order to solve the above technical problems, the embodiment of the present application further provides a pulse oscillation test device, wherein the pulse oscillation test device comprises an air circuit component, a respiratory parameter measurement component, a speaker, and a speaker driving circuit as described in the above embodiment and any possible implementation.

[0049] For example, refer to Figure 5 , Figure 5A schematic diagram of a specific embodiment of an H-bridge control circuit of the present application is shown.

[0050] Among them, Figure 5 As shown, P_DRIVE is the original base frequency square wave signal sent by the microcontroller, which is used as the original driving signal. P_DRIVE1, P_DRIVE2, P_DRIVE3 and P_DRIVE4 correspond to the control signals of the lower right bridge, lower left bridge, upper right bridge and upper left bridge of the H bridge respectively.

[0051] Taking driving the speaker as an example, assuming that the P_DRIVE signal is at a low level, after passing through the U14A inverter, P_DRIVE1 is obtained, which is a high level; after passing through the U14A inverter and the U14B inverter, P_DRIVE2 is obtained, and the signal is a low level; after passing through the U14A inverter and the U15A inverter, P_DRIVE3 is obtained, which is a low level; after passing through the U14A inverter, the U14B inverter, and the U15D inverter, P_DRIVE4 is obtained, which is a high level; at this time, PDRIVE_1 / 4 are turned on at the same time, driving the speaker in one direction.

[0052] Assuming that the P_DRIVE signal is high, after passing through the U14A inverter, P_DRIVE1 is obtained, which is a low level; after passing through U14A and U14B, P_DRIVE2 is obtained, and the signal is high; after passing through U14A and U15A, P_DRIVE3 is obtained, which is a high level; after passing through U14A, U14B, and U15D, P_DRIVE4 is obtained, which is a high-low level; at this time, PDRIVE_2 / 3 are turned on at the same time, driving the speaker in another direction.

[0053] In the figure, R106 and U14A form a first buffer circuit to strengthen the original baseband square wave signal sent by the microcontroller.

[0054] The pulse modulation circuit composed of U16A or gate and U17 timer in the figure can accurately change the pulse width of P_DRIVE3 / 4 as needed, drive the rear-end speaker to generate pressure of different amplitudes, and provide differentiated amplitude-frequency characteristics for the algorithm after being collected by the sensor and transformed through Fourier transform.

[0055] Furthermore, R107 and C134 in the figure form an RC buffer circuit, i.e., the second buffer, with the purpose of generating a delay, which is reversed with another normal input of U16B after two stages of inversion and has a slight timing difference, causing U16B to output a periodic very narrow low pulse. This low level forms a relationship with the high level of P_DRIVE3 and 4 after two stages of inversion, making the final P_DRIVE3 and 4 signals slightly narrower than P_DRIVE1 / 2. This amplitude can be adjusted according to different component models and requirements of the back-end. Therefore, when P_DRIVE2 / 3 or P_DRIVE1 / 4 are both high and drive the MOS tube, ensure that the pulse of the upper bridge must be narrower than the pulse of the lower bridge on the same side. When switching to another group, the two upper bridge MOS tubes can always be turned off first, so the MOS tubes corresponding to P_DRIVE1 / 3 or P_DRIVE2 / 4 on the same side are basically impossible to be turned on at the same time when switching. In extreme cases, when the two corresponding H-bridge lower bridges of P_DRIVE1 / 2 are at a high level at the same time, the XOR gate of U16B in the circuit will produce a low level, which will directly pull down P_DRIVE3 / 4 after two-stage reversal, avoiding the situation where the upper and lower bridges on the same side are turned on at the same time and the MOS tube is burned.

[0056] Further references Figure 6 , Figure 6 The schematic diagram of a specific embodiment of the connection between the H-bridge circuit and the speaker is shown. The main purpose of the circuit composed of R122 / C156 and R121 / C155 in the figure is to limit the current and absorb the instantaneous reverse electromotive force generated by the speaker during the H-bridge switching process, and at the same time generate a certain buffer, so that the rising and falling edges of the signal driving the speaker are smoother, eliminating the impact of the speaker when working and reducing the loudness.

[0057] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. An H-bridge control circuit, characterized in that: include: A microcontroller, a first inverter, a second inverter, a third inverter and an XOR gate; The microcontroller is used to generate a baseband square wave pulse signal, and the output end of the microcontroller is respectively connected to a first interface, a first input end of the XOR gate, and input ends of the first inverter and the second inverter, wherein the first interface is a control interface of the lower right bridge of the H-bridge; The output end of the first inverter is connected to the second interface, the input end of the third inverter and the second input end of the XOR gate respectively, and the second interface is the control interface of the lower left bridge of the H bridge; After the output end of the second inverter and the output end of the XOR gate are connected in parallel, they are connected to a third interface, and the third interface is a control interface of the upper right bridge of the H bridge; After the output end of the third inverter and the output end of the XOR gate are connected in parallel, they are connected to a fourth interface, and the fourth interface is a control interface of the upper left bridge of the H bridge.

2. The H-bridge control circuit according to claim 1, characterized in that: The H-bridge control circuit also includes: A first buffer, wherein the input end of the first buffer is connected to the output end of the microcontroller, and the output end of the first buffer is respectively connected to the first interface, the first input end of the XOR gate, and the input ends of the first inverter and the second inverter.

3. The H-bridge control circuit according to claim 2, characterized in that: The H-bridge control circuit also includes: A pulse width modulation module, a fourth inverter and a fifth inverter; The input end of the pulse width modulation module is connected to the first buffer, and the output end is connected to the input ends of the four inverters and the fifth inverter respectively; The output end of the fourth inverter is connected in parallel with the output end of the second inverter and the output end of the XOR gate, and then connected to the third interface; The output end of the fifth inverter is connected in parallel with the output end of the third inverter and the output end of the XOR gate, and then connected to the fourth interface.

4. The H-bridge control circuit according to claim 3, characterized in that: The H-bridge control circuit also includes: a sixth inverter, a seventh inverter, and an eighth inverter; The input end of the sixth inverter is connected to the output end of the XOR gate, and the output end is connected to the input ends of the seventh inverter and the eighth inverter; The output end of the seventh inverter is connected in parallel with the output end of the second inverter and the output end of the fourth inverter, and then connected to the third interface; The output end of the eighth inverter is connected in parallel with the output end of the third inverter and the output end of the fifth inverter, and then connected to the fourth interface.

5. The H-bridge control circuit according to any one of claims 2 to 4, characterized in that: The H-bridge control circuit also includes: A second buffer is provided between an output terminal of the first buffer and a first input terminal of the XOR gate.

6. The H-bridge control circuit according to claim 5, characterized in that: The second buffer includes a first RC buffer circuit.

7. The H-bridge control circuit according to claim 6, characterized in that: The second buffer also includes a ninth inverter and a tenth inverter. The first RC buffer circuit, the ninth inverter and the tenth inverter are connected in series in sequence. The input end of the first RC buffer circuit is connected to the output end of the first buffer. The output end of the tenth inverter is connected to the second input end of the XOR gate.

8. A speaker driving circuit, characterized in that: include: The H-bridge control circuit and the H-bridge circuit as described in any one of claims 1 to 8, wherein the driving interface of the H-bridge circuit is used to connect a speaker.

9. The speaker driving circuit according to claim 8, characterized in that: The speaker driving circuit further includes a second RC buffer circuit, which is arranged between the control switch of the H-bridge circuit and the driving interface of the H-bridge circuit.

10. A pulse oscillation test device, characterized in that: It includes an air circuit component, a respiratory parameter measurement component, a speaker, and a speaker driving circuit as described in claims 8 and 9.

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