Power-on power supply and enable circuit in motor driving system
By designing a power-on power supply and enable circuit including a power-on bias module, a real-time voltage and current verification module and an output control module, the problem of difficulty in starting the motor drive system in a timely manner when the voltage of the external power supply power supply fluctuates greatly, and a stable and reasonable power supply and timely power-on and boot of the system are achieved.
Patent Information
- Application Number
- CN202411961049.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-11
AI Technical Summary
In the motor drive system, the voltage value of the external power supply fluctuates greatly, which makes it difficult for the motor drive system to start up in time and operate normally when the real-time power supply voltage changes greatly.
A power-on power supply and enable circuit including a power-on bias module, a real-time voltage and current verification module and an output control module are designed. This circuit monitors the power supply consumption of the internal control unit of the motor drive system in real time, shields unnecessary high-voltage components in the external power supply, and forms a stable and reasonable power supply, ensuring that the motor drive system is powered on and turned on in a timely manner.
When the voltage of the external power supply power supply fluctuates greatly, ensure that the internal control unit of the motor drive system obtains stable and reasonable power supply, ensure that the system can be powered on and turned on in time, and improve the reliability and stability of the system.
Smart Images
Figure CN119813886A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of motor drive systems, and in particular to a power-on, power supply and enabling circuit in a motor drive system. Background Art
[0002] In the design and application of motor drive systems, it is crucial to ensure that the internal control unit obtains stable and reasonable power supply. This is not only related to whether the entire system can start and operate normally, but also directly affects its performance and service life.
[0003] However, in actual application scenarios, the external power supply of the application system is often not a constant voltage source under ideal conditions. Its voltage value will change according to different application scenarios, and the influence of factors such as the motor drive system's own inductance commutation and power tube switching must also be considered.
[0004] It can be seen that the actual motor drive system external power supply model is equivalent to a voltage source with a large voltage amplitude fluctuation. Therefore, in order to enable the motor drive system to start up in time and operate normally when the real-time power supply voltage value changes greatly, it is crucial to design a reasonable and effective power supply and enabling circuit for its internal control unit. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides a power-on power supply and enabling circuit in a motor drive system, characterized in that it includes a power-on bias module, a real-time voltage and current detection module and an output control module, wherein: The real-time voltage and current detection module is used to monitor the power consumption of the control unit inside the motor drive system; The power-on bias module is used to shield the high-voltage component of the power supply signal of the external power supply; The output control module is used to form a stable and reasonable power supply required by the internal control unit of the motor drive system, and the real-time voltage and current detection module can synchronously output a valid power-on enable signal to ensure that the motor drive system is powered on and started in time.
[0006] Furthermore, the power-on bias module includes a self-bias current source circuit and a common-gate circuit.
[0007] Furthermore, the self-bias current source circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2 and a third PMOS transistor P3, wherein: The first resistor R1, the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the gate of the third PMOS transistor P3; The source of the first PMOS transistor P1 , the source of the second PMOS transistor P2 , and the source of the third PMOS transistor P3 are all connected to the port VDD.
[0008] Furthermore, the common-gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3, wherein: The drain of the second PMOS transistor P2, the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3, and the gate of the second NMOS transistor N2 are all connected to the gate of the first NMOS transistor N1; The drain of the third PMOS tube P3 is connected to the drain of the second NMOS tube N2; The source of the third NMOS tube N3 is connected to the port V1; The source of the second NMOS tube N2 is connected to the port V2; The source of the first NMOS transistor N1 is connected to the port V3.
[0009] Furthermore, the real-time voltage and current detection module includes a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit and a current amplitude detection circuit.
[0010] Furthermore, the conversion circuit and the reference level generation and voltage upper limit clamping circuit are simultaneously formed by a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7 connected in series.
[0011] Further, the voltage comparison output circuit includes an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10 and an eleventh NMOS tube N11, wherein: The drain of the seventh NMOS tube N7, the gate of the seventh NMOS tube N7, the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9, the gate of the tenth NMOS tube N10, and the gate of the eleventh NMOS tube N11 are all connected to the source of the sixth NMOS tube N6; The source of the seventh NMOS tube N7, the source of the eighth NMOS tube N8, the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10, the source of the eleventh NMOS tube N11, the source of the fifteenth NMOS tube N15, and the source of the sixteenth NMOS tube N16 are all connected to the port GND.
[0012] Further, the waveform shaping circuit includes a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, the fifteenth NMOS tube N15, the sixteenth NMOS tube N16, a fourth PMOS tube P4, a fifth PMOS tube P5 and a first capacitor C1, wherein: The drain of the tenth NMOS tube N10 and the drain of the eleventh NMOS tube N11 are both connected to the source of the twelfth NMOS tube N12; The source of the thirteenth NMOS tube N13 and the source of the fourteenth NMOS tube N14 are both connected to the drain of the fifteenth NMOS tube N15; The drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9, the drain of the twelfth NMOS tube N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS tube N13, the gate of the fifteenth NMOS tube N15, and the gate of the fourth PMOS tube P4 are all connected to the port V2; The upper end of the first capacitor C1, the source of the fourth PMOS transistor P4, the drain of the fourteenth NMOS transistor N14, and the source of the fifth PMOS transistor P5 are all connected to the port V3; The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to the port V4; The drain of the fourth PMOS tube P4, the drain of the thirteenth NMOS tube N13, the gate of the fourteenth NMOS tube N14, the gate of the fifth PMOS tube P5, the gate of the sixteenth NMOS tube N16, and the gate of the twelfth NMOS tube N12 are all connected to the port VEN.
[0013] Furthermore, the current amplitude detection circuit includes a first diode D1 , and the first diode D1 is connected to the port V3 .
[0014] Furthermore, the output control module includes a sixth PMOS transistor P6, wherein: The source of the sixth PMOS tube P6 is connected to the port V3; The gate of the sixth PMOS tube P6 is connected to the port V4; The drain of the sixth PMOS transistor P6 is connected to the port VOUT.
[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: When the real-time power supply voltage value of the external power supply of the motor drive system changes greatly, the real-time voltage and current detection module is used to monitor the power consumption of the internal control unit of the motor drive system, and the power-on bias module is used to shield the unnecessary high-voltage components in the power supply signal of the external power supply of the motor drive system, and finally the output control module forms a stable and reasonable power supply required by the internal control unit of the motor drive system; at the same time, the real-time voltage and current detection module will also synchronously output a valid power-on enable signal to ensure that the motor drive system can be powered on and started in time. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 It is a principle block diagram disclosed in an embodiment of the present invention; Figure 2 The schematic diagram of the circuit disclosed in the embodiment of the present invention.
[0018] In the figure: 10. Power-on bias module; 20. Real-time voltage and current detection module; 30. Output control module. DETAILED DESCRIPTION
[0019] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0020] The present invention aims to provide a power-on supply and enabling circuit in a motor drive system, which can ensure the stable and reasonable power supply required by the internal control unit of the motor drive system when the real-time power supply voltage value of the external power supply of the motor drive system changes greatly, and output an effective power-on enabling signal to ensure that the motor drive system can be powered on and started in time.
[0021] Please refer to Figure 1 The power-on supply and enabling circuit in the motor drive system provided by the present invention mainly includes a power-on bias module 10 , a real-time voltage and current detection module 20 and an output control module 30 .
[0022] The power-on bias module 10 is connected to the port VDD and the port GND and is used to shield the high voltage component of the power supply signal of the external power supply.
[0023] The real-time voltage and current test module 20 is connected to the power-on bias module 10, and the real-time voltage and current test module 20 is connected to the port VEN and the port GND. The real-time voltage and current test module 20 is used to monitor the power consumption of the control unit inside the motor drive system; and the real-time voltage and current test module 20 can synchronously output a valid power-on enable signal to ensure that the motor drive system is powered on in time.
[0024] The input end of the output control module 30 is connected to the startup bias module 10 and the real-time voltage and current detection module 20; the output end of the output control module 30 is connected to the port VOUT. The output control module 30 is used to form a stable and reasonable power supply required by the internal control unit of the motor drive system.
[0025] Among them, port GND is the reference ground; port VDD is the external power supply port; port VOUT is used to output a stable and reasonable power supply signal to the internal control unit of the motor drive system; port VEN is used to output a timely and effective power-on enable signal.
[0026] Port V1 , port V2 , port V3 and port V4 are communication ports between the startup bias module 10 , the real-time voltage and current detection module 20 and the output control module 30 , respectively.
[0027] First, the startup bias module 10 in this embodiment is described.
[0028] See also Figure 2 The startup bias module 10 includes a self-bias current source circuit and a common-gate circuit.
[0029] The self-bias current source circuit includes a first resistor R1 , a first PMOS transistor P1 , a second PMOS transistor P2 , and a third PMOS transistor P3 .
[0030] Among them, the first resistor R1, the drain of the first PMOS tube P1, the gate of the first PMOS tube P1, and the gate of the second PMOS tube P2 are all connected to the gate of the third PMOS tube P3; the source of the first PMOS tube P1, the source of the second PMOS tube P2, and the source of the third PMOS tube P3 are all connected to the port VDD.
[0031] The common-gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3.
[0032] Among them, the drain of the second PMOS tube P2, the gate of the third NMOS tube N3, the drain of the third NMOS tube N3, and the gate of the second NMOS tube N2 are all connected to the gate of the first NMOS tube N1; the drain of the third PMOS tube P3 is connected to the drain of the second NMOS tube N2; the source of the third NMOS tube N3 is connected to the port V1; the source of the second NMOS tube N2 is connected to the port V2; and the source of the first NMOS tube N1 is connected to the port V3.
[0033] Then, the real-time voltage and current checking module 20 in this embodiment is described.
[0034] See also Figure 2 The real-time voltage and current inspection module 20 includes a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit and a current amplitude detection circuit.
[0035] The current-to-voltage conversion circuit and the reference level generation and voltage upper limit clamping circuit are simultaneously formed by the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 connected in series.
[0036] The voltage comparison output circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10 and an eleventh NMOS transistor N11.
[0037] Among them, the drain of the seventh NMOS tube N7, the gate of the seventh NMOS tube N7, the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9, the gate of the tenth NMOS tube N10, and the gate of the eleventh NMOS tube N11 are all connected to the source of the sixth NMOS tube N6; the source of the seventh NMOS tube N7, the source of the eighth NMOS tube N8, the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10, the source of the eleventh NMOS tube N11, the source of the fifteenth NMOS tube N15, and the source of the sixteenth NMOS tube N16 are all connected to the port GND.
[0038] The waveform shaping circuit includes a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a fourth PMOS transistor P4, a fifth PMOS transistor P5 and a first capacitor C1.
[0039] Among them, the drain of the tenth NMOS tube N10 and the drain of the eleventh NMOS tube N11 are both connected to the source of the twelfth NMOS tube N12; the source of the thirteenth NMOS tube N13 and the source of the fourteenth NMOS tube N14 are both connected to the drain of the fifteenth NMOS tube N15; the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9, the drain of the twelfth NMOS tube N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS tube N13, the gate of the fifteenth NMOS tube N15, and the gate of the fourth PMOS tube P4 are all connected to the port V2.
[0040] The upper end of the first capacitor C1 , the source of the fourth PMOS transistor P4 , the drain of the fourteenth NMOS transistor N14 , and the source of the fifth PMOS transistor P5 are all connected to the port V3 .
[0041] The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to the port V4.
[0042] The drain of the fourth PMOS transistor P4, the drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, the gate of the fifth PMOS transistor P5, the gate of the sixteenth NMOS transistor N16, and the gate of the twelfth NMOS transistor N12 are all connected to the port VEN.
[0043] The current amplitude detection circuit includes a first diode D1 connected to the port V3.
[0044] Finally, the output control module 30 in this embodiment is described.
[0045] See also Figure 2 , the output control module 30 includes a sixth PMOS tube P6.
[0046] The source of the sixth PMOS transistor P6 is connected to the port V3; the gate of the sixth PMOS transistor P6 is connected to the port V4; and the drain of the sixth PMOS transistor P6 is connected to the port VOUT.
[0047] In a further embodiment of the present invention: When an external power source with a fluctuating voltage amplitude supplies power to the motor drive system end, the startup bias module 10 will detect whether the voltage amplitude meets the minimum requirements for the operation of this unit. When the voltage amplitude of the external power supply is greater than the minimum operating voltage amplitude requirement of the startup bias module 10, the self-biased current source circuit composed of the first resistor R1, the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 starts to operate, and automatically turns on the common-gate circuit composed of the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1. At this time, the clamping property of the common-gate circuit realizes the shielding of the startup bias module 10 against the unnecessary high-voltage components in the external power supply signal. Subsequently, the power-on bias module 10 allows its ports V1 and V2 to generate current signals that can reflect the external power supply information in real time, and transmits them to the real-time voltage and current detection module 20 for processing. At the same time, the power-on bias module 10 also allows the first NMOS tube N1 to generate a pull-up current at its port V3, and the current intensity is jointly determined by the real-time voltage and current detection unit communicating with port V3 and the output control unit.
[0048] In a further embodiment of the present invention: After the real-time voltage and current detection module 20 obtains the current signal reflecting the power supply information of the external power source from the port V1, it converts the current signal into a voltage signal through a conversion circuit at the port V1 and processes the voltage signal.
[0049] When the converted voltage signal amplitude is less than the reference voltage, the reference level generation and voltage upper limit clamping circuit cancels the clamping effect, indicating that the external power supply voltage amplitude does not meet the output power supply condition at this time; the voltage comparison output circuit outputs high impedance. According to Ohm's law, the current signal from the power-on bias module 10 is automatically converted into a high-level voltage signal at port V2, and then output after the shaping of the waveform shaping circuit. On the one hand, the port VEN signal is made low-level, indicating that the motor drive system is not allowed to be powered on at this time; on the other hand, the port V4 is made high-level to control the gate of the sixth PMOS tube P6 in the output control module 30 to form a turn-off state. At this time, the port VOUT will not output the power supply voltage to the internal control unit of the motor drive system.
[0050] When the converted voltage signal amplitude is large enough and can make the reference level generation and voltage upper limit clamping circuit have a clamping effect, the voltage signal is clamped at the reference voltage amplitude level, indicating that the external power supply voltage amplitude has met the output power supply conditions, that is, it has met the requirements for the normal operation of the internal control unit of the motor drive system. The voltage comparison output circuit pulls down and absorbs all current signals from the power-on bias unit at port V2, so that port V2 is automatically converted into a low-level voltage signal; and after the waveform shaping output of the waveform shaping circuit, on the one hand, port V4 is made low-level, and the gate of the sixth PMOS tube P6 in the output control module 30 is turned on; on the other hand, the port VEN signal is made high-level, indicating that the motor drive system is immediately allowed to power on and start up at this time to inform the outside.
[0051] During the shaping output process of the waveform shaping circuit, a stable delay time is formed through the charging and discharging characteristics of the first capacitor C1, ensuring that the port VEN signal has a minimum low-level duration, which is conducive to timely and effective sampling of the signal by the external related system.
[0052] After the output control module 30 forms the open state control, through the port VOUT, the drain of the sixth PMOS tube P6 in the output control module 30 can output a stable and reasonable power supply voltage to the internal control unit of the motor drive system. At the same time, the output control module 30 synchronously feeds back the power supply current information to the port V3, and judges it through the current amplitude detection circuit inside the real-time voltage and current detection module 20. When the power supply current exceeds the normal range, the first diode D1 will turn on and force the amplitude of the port V1 voltage signal to be reduced, making it less than the reference voltage, causing the output of the voltage comparison output circuit inside the real-time voltage and current detection module 20 to become high impedance, and finally making the port VEN signal low level, and the port V4 high level, that is, notifying the outside that the motor drive system is not allowed to power on at this time, and the output control module 30 forms a shutdown state, and the port VOUT no longer outputs power to the internal control unit of the motor drive system. Through this process, the normal range of the power supply current is defined, and the current intensity of the power supply circuit is also indirectly defined, ensuring the reasonable effectiveness of the power consumption of the internal control unit of the motor drive system.
[0053] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A power supply and enabling circuit in a motor drive system, characterized in that: It comprises a power-on bias module (10), a real-time voltage and current detection module (20) and an output control module (30), wherein: The real-time voltage and current detection module (20) is used to monitor the power consumption of the control unit inside the motor drive system; The power-on bias module (10) is used to shield the high-voltage component of the power supply signal of the external power supply; The output control module (30) is used to form a stable and reasonable power supply required by the internal control unit of the motor drive system, and the real-time voltage and current detection module (20) can synchronously output an effective power-on enable signal to ensure that the motor drive system is powered on and started in time.
2. The power-on supply and enabling circuit in the motor drive system according to claim 1, characterized in that: The power-on bias module (10) comprises a self-bias current source circuit and a common-gate circuit.
3. The power supply and enabling circuit in the motor drive system according to claim 2, characterized in that: The self-bias current source circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2 and a third PMOS transistor P3, wherein: The first resistor R1, the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the gate of the third PMOS transistor P3; The source of the first PMOS transistor P1 , the source of the second PMOS transistor P2 , and the source of the third PMOS transistor P3 are all connected to the port VDD.
4. The power-on supply and enabling circuit in the motor drive system according to claim 3, characterized in that: The common-gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3, wherein: The drain of the second PMOS transistor P2, the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3, and the gate of the second NMOS transistor N2 are all connected to the gate of the first NMOS transistor N1; The drain of the third PMOS tube P3 is connected to the drain of the second NMOS tube N2; The source of the third NMOS tube N3 is connected to the port V1; The source of the second NMOS tube N2 is connected to the port V2; The source of the first NMOS transistor N1 is connected to the port V3.
5. The power-on supply and enabling circuit in the motor drive system according to claim 1, characterized in that: The real-time voltage and current inspection module (20) comprises a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit and a current amplitude detection circuit.
6. The power-on supply and enabling circuit in the motor drive system according to claim 5, characterized in that: The conversion circuit and the reference level generation and voltage upper limit clamping circuit are simultaneously formed by a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7 connected in series.
7. The power-on supply and enabling circuit in the motor drive system according to claim 6, characterized in that: The voltage comparison output circuit includes an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10 and an eleventh NMOS tube N11, wherein: The drain of the seventh NMOS tube N7, the gate of the seventh NMOS tube N7, the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9, the gate of the tenth NMOS tube N10, and the gate of the eleventh NMOS tube N11 are all connected to the source of the sixth NMOS tube N6; The source of the seventh NMOS tube N7, the source of the eighth NMOS tube N8, the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10, the source of the eleventh NMOS tube N11, the source of the fifteenth NMOS tube N15, and the source of the sixteenth NMOS tube N16 are all connected to the port GND.
8. The power-on supply and enabling circuit in the motor drive system according to claim 7, characterized in that: The waveform shaping circuit includes a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, the fifteenth NMOS tube N15, the sixteenth NMOS tube N16, a fourth PMOS tube P4, a fifth PMOS tube P5 and a first capacitor C1, wherein: The drain of the tenth NMOS tube N10 and the drain of the eleventh NMOS tube N11 are both connected to the source of the twelfth NMOS tube N12; The source of the thirteenth NMOS tube N13 and the source of the fourteenth NMOS tube N14 are both connected to the drain of the fifteenth NMOS tube N15; The drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9, the drain of the twelfth NMOS tube N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS tube N13, the gate of the fifteenth NMOS tube N15, and the gate of the fourth PMOS tube P4 are all connected to the port V2; The upper end of the first capacitor C1, the source of the fourth PMOS transistor P4, the drain of the fourteenth NMOS transistor N14, and the source of the fifth PMOS transistor P5 are all connected to the port V3; The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to the port V4; The drain of the fourth PMOS tube P4, the drain of the thirteenth NMOS tube N13, the gate of the fourteenth NMOS tube N14, the gate of the fifth PMOS tube P5, the gate of the sixteenth NMOS tube N16, and the gate of the twelfth NMOS tube N12 are all connected to the port VEN.
9. The power-on supply and enabling circuit in the motor drive system according to claim 5, characterized in that: The current amplitude detection circuit includes a first diode D1 connected to a port V3 .
10. The power-on supply and enabling circuit in the motor drive system according to claim 1, characterized in that: The output control module (30) comprises a sixth PMOS tube P6, wherein: The source of the sixth PMOS tube P6 is connected to the port V3; The gate of the sixth PMOS tube P6 is connected to the port V4; The drain of the sixth PMOS transistor P6 is connected to the port VOUT.