Ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator

Abstract

The invention discloses an ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator. The ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator is composed of a transformer T1, a transformer T2, a transformer T3, a transformer T4, a head oscillator HR1, a head oscillator HR2, a head oscillator HR3, a head oscillator HR4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a plurality of decoupling capacitors Cecap. According to the voltage-controlled oscillator, noise is prevented from being converted into phase noise by means of second and third harmonic impedance broadening, inductance loss reduction, reduction of the sensitive time of the resonant cavity to the noise and the like, the phase noise generated by the voltage-controlled oscillator can be effectively reduced, and excellent noise performance is obtained.

Description

Technical Field

[0001] The invention relates to microwave monolithic integrated circuits and microelectronics technology, and in particular to an ultra-low phase noise harmonic quad-core voltage-controlled oscillator. Background Art

[0002] Voltage controlled oscillators play an important role in frequency synthesis, modulation and demodulation, signal generation, etc. With the continuous development of wireless communication technology, the application of voltage controlled oscillators in RF and microwave systems has become particularly critical, especially in modern cellular communications, satellite communications, and wireless local area networks. Since these applications require higher frequencies, lower phase noise, and more stable frequency outputs, the design of voltage controlled oscillators faces increasingly higher requirements. Therefore, improving its performance, especially reducing phase noise and improving frequency stability, has become an important research direction in the current electronic engineering and communication engineering fields. However, as the operating frequency increases, the quality factor of the passive and active devices in the oscillator is rapidly deteriorating, resulting in the deterioration of phase noise.

[0003] In order to optimize the performance of voltage-controlled oscillators at high frequencies, multi-core oscillators have been proposed, which can continue to improve the phase noise performance based on single-core oscillators. By making trade-offs between power consumption, area, and phase noise, theoretically, a quad-core oscillator can reduce phase noise by 6 dB without changing the FOM value. However, the existing multi-core voltage-controlled oscillators have many shortcomings: they only use a fixed tail inductor to filter the secondary noise current, and they do not consider a clear secondary current path, which makes it impossible to reduce the phase noise at low frequency offsets in the full frequency band; there is no harmonic input impedance broadening, which causes multiple sets of tuning capacitor arrays to deteriorate the phase noise.

[0004] In the high frequency band, the phase noise can be further reduced and the overall performance can be optimized by utilizing the advantages of low noise sensitivity of harmonic oscillators and the phase noise reduction technology of multi-core structures. Summary of the invention

[0005] The object of the present invention is to provide an ultra-low phase noise harmonic quad-core voltage-controlled oscillator.

[0006] The technical solution to realize the present invention is: an ultra-low phase noise harmonic quad-core voltage-controlled oscillator, including NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, gate capacitor C G1 , gate capacitance C G2 , gate capacitance C G3 , gate capacitance C G4 , drain capacitance C D1 , drain capacitance C D2 , drain capacitance CD3 , drain capacitance C D4 , floating coil capacitance C T1 , floating coil capacitance C T2 , floating coil capacitance C T3 , floating coil capacitance C T4 , three mutually coupled inductors L D1 , L G1 , L T1 The transformer T1, three mutually coupled inductors L D2 , L G2 , L T2 The transformer T2, three mutually coupled inductors L D3 , L G3 , L T3 The transformer T3, three mutually coupled inductors L D4 , L G4 , L T4 The transformer T4 and the tail inductor L S1 , tail inductance L S2 , tail inductance L S3 , tail inductance L S4 , tail inductance L S5 , tail inductance L S6 , tail inductance L S7 , tail inductance L S8 , capacitor C CM1 The inductance L coupled to each other CM1 , L CM2 The head oscillator HR1, capacitor C CM2 The inductance L coupled to each other CM3 , L CM4 The head oscillator HR2, capacitor C CM3 The inductance L coupled to each other CM5 , L CM6 The head oscillator HR3, capacitor C CM4 The inductance L coupled to each other C M7 , L CM8 The head oscillator HR4, resistor R1, resistor R2, resistor R3, resistor R4, multiple decoupling capacitors C decap ,in:

[0007] The source of NMOS tube M1 and the source of NMOS tube M2 are connected to the inductor L S1 and inductor L S8 One end, inductor L S1 and inductor L S8 The other end is connected to 0 potential VSS; the drain of NMOS tube M1 and the inductor L D4 The positive and drain capacitance CD1 The gate of NMOS tube M1 is connected to the inductor L G1 The negative electrode and gate capacitance C G1 connected; the drain of NMOS tube M2 and the inductor L D1 The negative electrode and drain capacitance C D1 The other end of the NM OS tube M2 is connected to the gate capacitor C G1 The other end, inductor L G4 The positive electrode is connected to the floating coil capacitor C T1 One end of the inductor L is connected T4 The positive terminal of the floating coil capacitor C T1 The other end of the inductor L T1 The negative terminal of the inductor L D1 Center tap connected to inductor L CM1 , L CM2 One end, L CM1 The other end is connected to the power supply VDD potential, L CM2 The other end is connected to capacitor C CM1 One end of the capacitor C CM1 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G1 The center tap is connected to resistor R1, and the other end of resistor R1 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M1 and NMOS tube M4;

[0008] The source of NMOS tube M3 and the source of NMOS tube M4 are connected to the inductor L S2 and inductor L S3 One end, inductor L S2 and inductor L S3 The other end is connected to 0 potential VSS; the drain of NMOS tube M3 and the inductor L D1 The positive and drain capacitance C D2 The gate of NMOS tube M3 is connected to the inductor L G2 The negative electrode and gate capacitance C G2 connected; the drain of NMOS tube M4 and the inductor L D2 The negative electrode and drain capacitance C D2 The other end of the NM OS tube M4 is connected to the gate capacitor C G2 The other end, inductor L G1 The positive electrode is connected to the floating coil capacitor C T2 One end of the inductor L is connected T1 The positive terminal of the floating coil capacitor C T2 The other end of the inductor L T2 The negative terminal of the inductor L D2 Center tap connected to inductor L CM3 , LCM4 One end, L CM3 The other end is connected to VDD potential, L CM4 The other end is connected to capacitor C CM2 One end of the capacitor C CM2 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G2 The center tap is connected to resistor R2, and the other end of resistor R2 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M3 and NMOS tube M6;

[0009] The source of NMOS tube M5 and the source of NMOS tube M6 are connected to the inductor L S4 and inductor L S5 One end, inductor L S4 and inductor L S5 The other end is connected to 0 potential VSS; the drain of NMOS tube M5 and the inductor L D2 The positive and drain capacitance C D3 The gate of NMOS tube M5 is connected to the inductor L G3 The negative electrode and gate capacitance C G3 connected; the drain of NMOS tube M6 and the inductor L D3 The negative electrode and drain capacitance C D3 The other end of the NM OS tube M6 is connected to the gate capacitor C G3 The other end, inductor L G2 The positive electrode is connected to the floating coil capacitor C T3 One end of the inductor L is connected T2 The positive terminal of the floating coil capacitor C T3 The other end of the inductor L T3 The negative terminal of the inductor L D3 Center tap connected to inductor L CM5 , L CM6 One end, L CM5 The other end is connected to VDD potential, L CM6 The other end is connected to capacitor C CM3 One end of the capacitor C CM3 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G3 The center tap is connected to resistor R3, and the other end of resistor R3 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M5 and NMOS tube M8;

[0010] The source of NMOS tube M7 and the source of NMOS tube M8 are connected to the inductor L S6 and inductor L S7 One end, inductor L S6 and inductor LS7 The other end is connected to 0 potential VSS; the drain of NMOS tube M7 and inductor L D3 The positive and drain capacitance C D4 The gate of NMOS tube M7 is connected to the inductor L G4 The negative electrode and gate capacitance C G4 connected; the drain of NMOS tube M8 and the inductor L D4 The negative electrode and drain capacitance C D4 The other end of the NM OS tube M8 is connected to the gate capacitor C G4 The other end, inductor L G3 The positive electrode is connected to the floating coil capacitor C T4 One end of the inductor L is connected T3 The positive terminal of the floating coil capacitor C T4 The other end of the inductor L T4 The negative terminal of the inductor L D4 Center tap connected to inductor L CM7 , L CM8 One end, L CM7 The other end is connected to VDD potential, L CM8 The other end is connected to capacitor C CM4 One end of the capacitor C CM4 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G4 The center tap is connected to resistor R4, and the other end of resistor R4 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M7 and NMOS tube M2, between all VDD potential and VSS potential in the oscillator, using C decap are connected.

[0011] Furthermore, the four transformers T1, T2, T3, and T4 are completely identical, and the inductance L D1 , L D2 , L D3 , L D4 The inductance value is equal to L D , inductance L T1 , L T2 , L T3 , L T4 The inductance value is equal to L T , inductance L G1 , L G2 , L G3 , L G4 The inductance value is equal to L G , capacitor C D1 , C D2 , C D3 , C D4 The capacitance value is equal to C D , capacitor CG1 , C G2 , C G3 , C G4 The capacitance value is equal to C G , capacitor C T1 , C T2 , C T3 , C T4 The capacitance value is equal to C T , inductance L D1 With inductance L G1 、Inductance L D2 With inductance L G2 、Inductance L D3 With inductance L G3 、Inductance L D4 With inductance L G4 The coupling coefficient between them is equal to K DG , inductance L G1 With inductance L T1 、Inductance L G2 With inductance L T2 、Inductance L G3 With inductance L T3 、Inductance L G4 With inductance L T4 The coupling coefficient between them is equal to K GT , inductance L D1 With inductance L T1 、Inductance L D2 With inductance L T2 、Inductance L D3 With inductance L T3 、Inductance L D4 With inductance L T4 The coupling coefficient between them is equal to K DT ; Inductance L CM1 With inductance L CM2 、Inductance L CM3 With inductance L CM4 、Inductance L CM5 With inductance L CM6 、Inductance L CM7 With inductance L CM8 The coupling coefficient between them is equal to K CM .

[0012] Furthermore, the gate capacitance C G1 , C G2 , C G3 , C G4 , drain capacitance C D1 , C D2 , C D3 , C D4 , floating coil capacitance C T1 , C T2 , C T3, C T4 And transformers T1, T2, T3, T4 form the differential mode resonant cavity of the oscillator; inductor L D1 , L D2 , L D3 , L D4 、Inductance L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 , head oscillator HR1, head oscillator HR2, head oscillator HR3, and head oscillator HR4 constitute a common-mode resonant cavity of the oscillator.

[0013] Furthermore, in the design of the differential mode resonant cavity, the first resonance point of the differential mode resonant cavity is designed at the fundamental frequency of the oscillator oscillation, and the second and third resonance points of the differential mode resonant cavity are designed near the third harmonic of the oscillator oscillation, that is, the input impedance has an impedance peak near the first harmonic, and the input impedance has a broadened double-peak impedance near the third harmonic.

[0014] Furthermore, in the design of the common-mode resonant cavity, the two resonance points of the common-mode resonant cavity are designed near the second harmonic frequency of the oscillator, that is, there is a broadened double-peak input impedance near the second harmonic, so that the entire oscillator works in Class-F 23 under the oscillation state.

[0015] Furthermore, four 1 / 4 ring-shaped inductors L are used. D1 , L D2 , L D3 , L D4 A toroidal inductor is formed.

[0016] Furthermore, four 1 / 4 ring-shaped inductors L are used. T1 , L T2 , L T3 , L T4 A toroidal inductor is formed.

[0017] Furthermore, four 1 / 4 ring-shaped inductors L are used. G1 , L G2 , L G3 , L G4 A toroidal inductor is formed.

[0018] Furthermore, the inductor L CM1 , L CM2 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D1 Tap point; inductance L CM3 , L CM4Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D2 Tap point; L CM5 , L CM6 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D3 Tap point; inductance L CM7 , L CM8 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D4 Tap point.

[0019] Compared with the prior art, the present invention has the following significant advantages: (1) a Class-F 23 Multi-core oscillator, by reducing the sensitivity of the resonant cavity noise and reducing the conversion of noise to phase noise; (2) through transformers T1, T2, T3, T4, gate capacitor C G1 , C G2 , C G3 , C G4 , drain capacitance C D1 , C D2 , C D3 , C D4 , floating coil capacitance C T1 , C T2 , C T3 , C T4 The high-order resonant cavity formed realizes the Class-F oscillator structure and generates a wide input impedance peak near the third frequency, realizing the tuning-free broadening of the third harmonic. It can tune only the fundamental frequency within a larger frequency tuning range while still maintaining a larger third component amplitude, realizing Class-F3 operation, thereby reducing the sensitivity of the resonant cavity to noise and reducing the conversion of noise into phase noise caused by the additional capacitor tuning array; (3) through the inductor L D1 , L D2 , L D3 , L D4 、Inductance L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8The common-mode resonant cavity composed of the head oscillator HR1, the head oscillator HR2, the head oscillator HR3, and the head oscillator HR4 can also generate a high-order resonant cavity, generate a wide input impedance peak near the secondary frequency, realize the tuning-free broadening of the second harmonic, and can only tune the fundamental frequency within a larger frequency tuning range while still maintaining a larger secondary component amplitude to achieve Class-F2, so as to reduce the degradation of the flicker noise to the phase noise; (4) Due to the use of a toroidal inductor structure, the inductor loss is reduced. Compared with the traditional octagonal inductor, it has a high quality factor. The quality factor can be increased to twice that of the traditional inductor, which greatly improves the overall noise and power consumption performance; (5) The resonant cavity based on transformers T1, T2, T3, and T4 has a larger passive gain than the resonant cavity based on inductors. The increase in oscillation amplitude ultimately improves the phase noise; (6) The use of the figure-eight common-mode inductor L CM1 , L CM2 , L CM3 , L CM4 , L CM5 , L CM6 , L CM7 , L CM8 , reduce the tap inductance to the inductance L D The coupling is achieved to avoid the mismatch between the left and right sides of the tap caused by the coupling affecting the phase noise performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 1 is a schematic diagram of the overall circuit structure of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention, and the dotted line frame is divided into four single-core CORE parts of the oscillator;

[0021] Figure 2 It is an equivalent circuit of a differential mode resonant cavity of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention;

[0022] Figure 3 It is an equivalent circuit of a common-mode resonant cavity of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of an inductor structure provided by an embodiment of the present invention;

[0024] Figure 5 is a simulation result of the differential mode input impedance of the resonant cavity provided in an embodiment of the present invention;

[0025] Figure 6 is a simulation result of the common-mode input impedance of the resonant cavity provided by an embodiment of the present invention;

[0026] Figure 7 is the tapped inductor L provided in the embodiment of the present invention CM1 and inductor LCM2 Structural diagram, inductance L C M3 and inductor L CM4 、Inductance L CM5 and inductor L CM6 、Inductance L CM7 and inductor L CM8 The structure is consistent with that shown in the figure;

[0027] Figure 8 It is a complete schematic diagram of a single-core CORE circuit of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention;

[0028] Fig. 9 It is a frequency adjustment range curve of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention;

[0029] Fig.10 Phase noise versus frequency curves of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by an embodiment of the present invention at 100KHz, 1MHz, and 10MHz frequency offsets;

[0030] Fig.11 The figure shows the pulse sensitivity function, noise modulation function, and effective pulse sensitivity function diagram of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention.

[0031] Fig.12 The chip layout of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] An ultra-low phase noise harmonic quad-core voltage-controlled oscillator, comprising an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, a gate capacitor C G1 , gate capacitance C G2 , gate capacitance C G3 , gate capacitance C G4 , drain capacitance C D1 , drain capacitance C D2 , drain capacitance C D3 , drain capacitance C D4 , floating coil capacitance C T1 , floating coil capacitance C T2 , floating coil capacitance CT3 , floating coil capacitance C T4 , three mutually coupled inductors L D1 , L G1 , L T1 The transformer T1, three mutually coupled inductors L D2 , L G2 , L T2 The transformer T2, three mutually coupled inductors L D3 , L G3 , L T3 The transformer T3, three mutually coupled inductors L D4 , L G4 , L T4 The transformer T4 and the tail inductor L S1 , tail inductance L S2 , tail inductance L S3 , tail inductance L S4 , tail inductance L S5 , tail inductance L S6 , tail inductance L S7 , tail inductance L S8 , capacitor C CM1 The inductance L coupled to each other CM1 , L CM2 The head oscillator HR1, capacitor C CM2 The inductance L coupled to each other CM3 , L CM4 The head oscillator HR2, capacitor C CM3 The inductance L coupled to each other CM5 , L CM6 The head oscillator HR3, capacitor C CM4 The inductance L coupled to each other CM7 , L CM8 The head oscillator HR4, resistor R1, resistor R2, resistor R3, resistor R4, multiple decoupling capacitors C deca ;

[0034] The source of NMOS tube M1 and the source of NMOS tube M2 are connected to the inductor L S1 and inductor L S8 One end, inductor L S1 and inductor L S8 The other end is connected to 0 potential VSS; the drain of NMOS tube M1 and the inductor L D4 The positive and drain capacitance C D1 The gate of NMOS tube M1 is connected to the inductor L G1 The negative electrode and gate capacitance C G1 connected; the drain of NMOS tube M2 and the inductor L D1The negative electrode and drain capacitance C D1 The other end of the NM OS tube M2 is connected to the gate capacitor C G1 The other end, inductor L G4 The positive electrode is connected to the floating coil capacitor C T1 One end of the inductor L is connected T4 The positive terminal of the floating coil capacitor C T1 The other end of the inductor L T1 The negative terminal of the inductor L D1 Center tap connected to inductor L CM1 , L CM2 One end, L CM1 The other end is connected to the power supply VDD potential, L CM2 The other end is connected to capacitor C CM1 One end of the capacitor C CM1 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G1 The center tap is connected to resistor R1, and the other end of resistor R1 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M1 and the NMOS tube M4.

[0035] The source of NMOS tube M3 and the source of NMOS tube M4 are connected to the inductor L S2 and inductor L S3 One end, inductor L S2 and inductor L S3 The other end is connected to 0 potential VSS; the drain of NMOS tube M3 and the inductor L D1 The positive and drain capacitance C D2 The gate of NMOS tube M3 is connected to the inductor L G2 The negative electrode and gate capacitance C G2 connected; the drain of NMOS tube M4 and the inductor L D2 The negative electrode and drain capacitance C D2 The other end of the NM OS tube M4 is connected to the gate capacitor C G2 The other end, inductor L G1 The positive electrode is connected to the floating coil capacitor C T2 One end of the inductor L is connected T1 The positive terminal of the floating coil capacitor C T2 The other end of the inductor L T2 The negative terminal of the inductor L D2 Center tap connected to inductor L CM3 , L CM4 One end, L CM3 The other end is connected to VDD potential, L CM4 The other end is connected to capacitor C CM2 One end of the capacitor C CM2The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G2 The center tap is connected to resistor R2, and the other end of resistor R2 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M3 and the NMOS tube M6.

[0036] The source of NMOS tube M5 and the source of NMOS tube M6 are connected to the inductor L S4 and inductor L S5 One end, inductor L S4 and inductor L S5 The other end is connected to 0 potential VSS; the drain of NMOS tube M5 and the inductor L D2 The positive and drain capacitance C D3 The gate of NMOS tube M5 is connected to the inductor L G3 The negative electrode and gate capacitance C G3 connected; the drain of NMOS tube M6 and the inductor L D3 The negative electrode and drain capacitance C D3 The other end of the NM OS tube M6 is connected to the gate capacitor C G3 The other end, inductor L G2 The positive electrode is connected to the floating coil capacitor C T3 One end of the inductor L is connected T2 The positive terminal of the floating coil capacitor C T3 The other end of the inductor L T3 The negative terminal of the inductor L D3 Center tap connected to inductor L CM5 , L CM6 One end, L CM5 The other end is connected to VDD potential, L CM6 The other end is connected to capacitor C CM3 One end of the capacitor C CM3 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G3 The center tap is connected to resistor R3, and the other end of resistor R3 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M5 and the NMOS tube M8.

[0037] The source of NMOS tube M7 and the source of NMOS tube M8 are connected to the inductor L S6 and inductor L S7 One end, inductor L S6 and inductor L S7 The other end is connected to 0 potential VSS; the drain of NMOS tube M7 and inductor L D3 The positive and drain capacitance C D4 The gate of NMOS tube M7 is connected to the inductor L G4The negative electrode and gate capacitance C G4 connected; the drain of NMOS tube M8 and the inductor L D4 The negative electrode and drain capacitance C D4 The other end of the NM OS tube M8 is connected to the gate capacitor C G4 The other end, inductor L G3 The positive electrode is connected to the floating coil capacitor C T4 One end of the inductor L is connected T3 The positive terminal of the floating coil capacitor C T4 The other end of the inductor L T4 The negative terminal of the inductor L D4 Center tap connected to inductor L CM7 , L CM8 One end, L CM7 The other end is connected to VDD potential, L CM8 The other end is connected to capacitor C CM4 One end of the capacitor C CM4 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G4 The center tap is connected to resistor R4, and the other end of resistor R4 is connected to V B The potential provides a gate DC voltage bias for NMOS tube M7 and NMOS tube M2. All VDD potentials and VSS potentials in the oscillator are connected by C decap are connected.

[0038] Furthermore, the four transformers T1, T2, T3, and T4 are completely identical. D , L T , L G Capacitance is represented by C D , C G , C T It can be considered that L D The inductance value is equal to L D1 , L D2 , L D3 , L D4 , L G The inductance value is equal to L G1 , L G2 , L G3 , L G4 , L T The inductance value is equal to L T1 , L T2 , L T3 , L T4 Capacitor C D The capacitance value is equal to C D1 , C D2 , C D3 , C D4 , capacitor CG The capacitance value is equal to C G1 , C G2 , C G3 , C G4 , capacitor C T The capacitance value is equal to C T1 , C T2 , C T3 , C T4 Inductance L D1 With inductance L G1 、Inductance L D2 With inductance L G2 、Inductance L D3 With inductance L G3 、Inductance L D4 With inductance L G4 The coupling coefficient between DG , inductance L G1 With inductance L T1 、Inductance L G2 With inductance L T2 、Inductance L G3 With inductance L T3 、Inductance L G4 With inductance L T4 The coupling coefficient between GT , inductance L D1 With inductance L T1 、Inductance L D2 With inductance L T2 、Inductance L D3 With inductance L T3 、Inductance L D4 With inductance L T4 The coupling coefficient between DT ; Inductance L CM1 With inductance L CM2 、Inductance L CM3 With inductance L CM4 、Inductance L CM5 With inductance L CM6 、Inductance L CM7 With inductance L CM8 The coupling coefficient between CM .

[0039] Furthermore, the NMOS tubes M1 and M2 of the oscillator adopt an inductor based on L G1 With inductance L D1 Coupling, inductance L G4 With inductance L D4 The oscillator's NMOS tube M3 and NMOS tube M4 are connected in a cross-coupling manner based on the inductor L G1 With inductance L D1 Coupling, inductance L G2With inductance L D2 The oscillator's NMOS tube M5 and NMOS tube M6 are connected in a cross-coupling manner based on the inductor L G2 With inductance L D2 Coupling, inductance L G3 With inductance L D3 The oscillator's NMOS tubes M7 and M8 are connected in a cross-coupling manner based on the inductor L G3 With inductance L D3 Coupling, inductance L G4 With inductance L D4 The coupled cross-coupling connection provides negative resistance for the resonant cavity and maintains the oscillation of the oscillator.

[0040] The gate input voltage of NMOS tubes M1, M2, M3, M4, M5, M6, M7, and M8 is realized by transformers T1, T2, T3, and T4, and NMOS tubes M1, M3, M5, and M7 and NMOS tubes M2, M4, M6, and M8 are alternately turned on and off. In half an oscillation cycle, when the drain end of NMOS tubes M1, M3, M5, and M7 is at a high potential, the gates of NMOS tubes M1, M3, M5, and M7 are at a low potential due to transformers T1, T2, T3, and T4; when the drain end of NMOS tubes M2, M4, M6, and M8 is at a low potential, the gates of NMOS tubes M2, M4, M6, and M8 are at a high potential due to transformers T1, T2, T3, and T4. In half an oscillation period, when the drain terminals of the NMOS tubes M1, M3, M5 and M7 are at a low potential, the gate terminals of the NMOS tubes M1, M3, M5 and M7 are at a high potential due to the transformers T1, T2, T3 and T4; when the drain terminals of the NMOS tubes M2, M4, M6 and M8 are at a high potential, the gate terminals of the NMOS tubes M2, M4, M6 and M8 are at a low potential due to the transformers T1, T2, T3 and T4.

[0041] Furthermore, the gate capacitance C G1 , C G2 , C G3 , C G4 , drain capacitance C D1 , C D2 , C D3 , C D4 , floating coil capacitance C T1 , C T2 , C T3 , CT4 And transformers T1, T2, T3, T4 form the differential mode resonant cavity of the oscillator; inductor L D1 , L D2 , L D3 , L D4 、Inductance L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 , head oscillator HR1, head oscillator HR2, head oscillator HR3, and head oscillator HR4 constitute a common-mode resonant cavity of the oscillator.

[0042] The differential mode resonant cavity of the oscillator has high-order properties and can produce three resonance points. In the design of the differential mode resonant cavity, the first resonance point of the differential mode resonant cavity is designed at the fundamental frequency of the oscillator oscillation, and the second and third resonance points are designed near the third frequency of the oscillator oscillation; the common mode resonant cavity of the oscillator also has high-order characteristics and can produce two resonance points. When designing the common mode resonant cavity, the resonance point of the common mode resonant cavity is designed near the secondary frequency of the oscillator, so that the entire oscillator works in Class-F 23 under the oscillation state.

[0043] Furthermore, four inductors L with a shape of about 1 / 4 ring are used. D1 , L D2 , L D3 , L D4 The inductor L is composed of four inductors of about 1 / 4 of the ring shape. G1 , L G2 , L G3 , L G4 The inductor L is composed of four inductors of about 1 / 4 of the ring shape. T1 , L T2 , L T3 , L T4 A toroidal inductor is formed.

[0044] Furthermore, the inductor L D1 At the tap, two overlapping inductors L are connected. CM1 , L CM2 Inductance L D2 At the tap, two overlapping inductors L are connected. CM3 , L CM4 Inductance L D3 At the tap, two overlapping inductors L are connected. CM5 , L CM6Inductance L D4 At the tap, two overlapping inductors L are connected. CM7 , L CM8 .

[0045] Furthermore, an inductor L is used S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 Shorten the distance between power supply VDD and ground VSS, and use decoupling capacitor C decap The power supply VDD and the ground VSS are connected, and the secondary current path is clearly defined.

[0046] Example

[0047] In order to verify the effectiveness of the scheme of the present invention, the following experimental design was carried out.

[0048] Figure 1 This is a topology structure of an ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided in this embodiment. Figure 1 , the source of NMOS tube M1 and the source of NMOS tube M2 are connected to the inductor L S1 and inductor L S8 One end, inductor L S1 and inductor L S8 The other end is connected to 0 potential VSS; the drain of NMOS tube M1 and the inductor L D4 The positive and drain capacitance C D1 The gate of NMOS tube M1 is connected to the inductor L G1 The negative electrode and gate capacitance C G1 connected; the drain of NMOS tube M2 and the inductor L D1 The negative electrode and drain capacitance C D1 The other end of the NMOS tube M2 is connected to the gate capacitor C G1 The other end, inductor L G4 The positive electrode is connected to the floating coil capacitor C T1 One end of the inductor L is connected T4 The positive terminal of the floating coil capacitor C T1 The other end of the inductor L T1 The negative terminal of the inductor L D1 Center tap connected to inductor L CM1 , L CM2 One end, L CM1 The other end is connected to the power supply VDD potential, L CM2 The other end is connected to capacitor C CM1 One end of the capacitor CCM1 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G1 The center tap is connected to resistor R1, and the other end of resistor R1 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M1 and the NMOS tube M4.

[0049] The source of NMOS tube M3 and the source of NMOS tube M4 are connected to the inductor L S2 and inductor L S3 One end, inductor L S2 and inductor L S3 The other end is connected to 0 potential VSS; the drain of NMOS tube M3 and the inductor L D1 The positive and drain capacitance C D2 The gate of NMOS tube M3 is connected to the inductor L G2 The negative electrode and gate capacitance C G2 connected; the drain of NMOS tube M4 and the inductor L D2 The negative electrode and drain capacitance C D2 The other end of the NM OS tube M4 is connected to the gate capacitor C G2 The other end, inductor L G1 The positive electrode is connected to the floating coil capacitor C T2 One end of the inductor L is connected T1 The positive terminal of the floating coil capacitor C T2 The other end of the inductor L T2 The negative terminal of the inductor L D2 Center tap connected to inductor L CM3 , L CM4 One end, L CM3 The other end is connected to VDD potential, L CM4 The other end is connected to capacitor C CM2 One end of the capacitor C CM2 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G2 The center tap is connected to resistor R2, and the other end of resistor R2 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M3 and the NMOS tube M6.

[0050] The source of NMOS tube M5 and the source of NMOS tube M6 are connected to the inductor L S4 and inductor L S5 One end, inductor L S4 and inductor L S5 The other end is connected to 0 potential VSS; the drain of NMOS tube M5 and the inductor L D2 The positive and drain capacitance C D3 The gate of NMOS tube M5 is connected to the inductor LG3 The negative electrode and gate capacitance C G3 connected; the drain of NMOS tube M6 and the inductor L D3 The negative electrode and drain capacitance C D3 The other end of the NM OS tube M6 is connected to the gate capacitor C G3 The other end, inductor L G2 The positive electrode is connected to the floating coil capacitor C T3 One end of the inductor L is connected T2 The positive terminal of the floating coil capacitor C T3 The other end of the inductor L T3 The negative terminal of the inductor L D3 Center tap connected to inductor L CM5 , L CM6 One end, L CM5 The other end is connected to VDD potential, L CM6 The other end is connected to capacitor C CM3 One end of the capacitor C CM3 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G3 The center tap is connected to resistor R3, and the other end of resistor R3 is connected to V B The potential provides a gate DC voltage bias for the NMOS tube M5 and the NMOS tube M8.

[0051] The source of NMOS tube M7 and the source of NMOS tube M8 are connected to the inductor L S6 and inductor L S7 One end, inductor L S6 and inductor L S7 The other end is connected to 0 potential VSS; the drain of NMOS tube M7 and inductor L D3 The positive and drain capacitance C D4 The gate of NMOS tube M7 is connected to the inductor L G4 The negative electrode and gate capacitance C G4 connected; the drain of NMOS tube M8 and the inductor L D4 The negative electrode and drain capacitance C D4 The other end of the NM OS tube M8 is connected to the gate capacitor C G4 The other end, inductor L G3 The positive electrode is connected to the floating coil capacitor C T4 One end of the inductor L is connected T3 The positive terminal of the floating coil capacitor C T4 The other end of the inductor L T4 The negative terminal of the inductor L D4 Center tap connected to inductor L CM7 , L CM8 One end, L CM7The other end is connected to VDD potential, L CM8 The other end is connected to capacitor C CM4 One end of the capacitor C CM4 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G4 The center tap is connected to resistor R4, and the other end of resistor R4 is connected to V B The potential provides a gate DC voltage bias for NMOS tube M7 and NMOS tube M2. All VDD potentials and VSS potentials in the oscillator are connected by C decap are connected.

[0052] Figure 2 is an equivalent circuit of a differential mode resonant cavity of a harmonic quad-core voltage-controlled oscillator with ultra-low phase noise provided by an embodiment of the present invention, such as Figure 2 As shown. Gate capacitance C G , drain capacitance C D , floating coil capacitance C T , the mutually coupled inductor L D , L T , L G The inductor and capacitor values ​​can be Figure 1 The inductor is L D , L T , L G Inductance L D1 , L D2 , L D3 , L D4 The inductance value is equal to L D , inductance L T1 , L T2 , L T3 , L T4 The inductance value is equal to L T , inductance L G1 , L G2 , L G3 , L G4 The inductance value is equal to L G Capacitor C D1 , C D2 , C D3 , C D4 The capacitance value is equal to C D , capacitor C G1 , C G2 , C G3 , C G4 The capacitance value is equal to C G , capacitor C T1 , C T2 , C T3 , C T4 The capacitance value is equal to C T .

[0053] Figure 3 The equivalent circuit of the common mode resonant cavity of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention is as follows: Figure 3 Inductance L D 、Inductance L S , the mutually coupled inductor L CM1 、Inductance L CM2 , capacitor C CM , the parasitic capacitance C between the drain and source of the NMOS tube P The common mode resonant cavity of the oscillator is composed of the inductor and capacitor values. Figure 1 The inductor is L D , L S , L CM1 , L CM2 Indicated by C CM , C P The equivalent parasitic capacitance from source to drain of NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, and NMOS tube M8 is represented by C P Inductance L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 The inductance value is equal to L S ; Capacitor C CM1 , C CM2 , C CM3 , C CM4 The capacitance value is equal to C CM .

[0054] Figure 4 is a schematic diagram of the transformer structure provided by an embodiment of the present invention, Figure 1 The specific layout implementation of the inductor in the schematic diagram. Three mutually coupled 1 / 4 ring inductors L D , L G , L T The transformer is composed of an inductor L D With inductance L G The coupling coefficient between DG , inductance L G With inductance L T The coupling coefficient between GT , inductance L D With inductance L T The coupling coefficient between DTThe present invention combines the four groups of the above-mentioned 1 / 4 toroidal inductors to form a Figure 4 The complete toroidal inductor shown. Figure 8 inductor L CM1 , L CM2 The coupling between C M , the outermost inductor is L S .

[0055] The specific design process is given below:

[0056] Phase 1: The design goal is to design the first resonance point of the differential mode resonant cavity at the target frequency of the oscillator, and the second and third resonance points are designed near the third frequency of the oscillator. By simulating the input impedance, the inductance value L is determined. D1 , L D2 , L D2 , L D2 , L G1 , L G2 , L G3 , L G4 , L T1 , L T2 , L T3 , L T4 With the capacitance value C D1 , C D2 , C D3 , C D4 , C G1 , C G2 , C G3 , C G4 , C T1 , C T2 , C T3 , C T4 Size, coupling coefficient K in transformers T1, T2, T3, T4 DG , K GT , K DT , in order to achieve the effect of widening the input impedance near the third frequency, such as Figure 5 shown.

[0057] Figure 5 This is the simulation result of the differential mode resonant cavity input impedance provided by the embodiment of the present invention, see Figure 5 The resonant cavity composed of a transformer and a capacitor has high-order characteristics and can generate three resonance points. The first resonance point of the differential mode resonant cavity is designed at the fundamental frequency of the oscillator, and the second and third resonance points are designed near the third frequency of the oscillator. The input impedance image is consistent with the input impedance design requirements of the differential mode resonant cavity in the design process described above.

[0058] The coupling coefficient K is determined by designing the resonance point of the common mode resonant cavity near the secondary frequency of the oscillator. CM 、Inductance L CM1 , L CM2 , L CM3 , L CM4 , L CM5 , L CM6 , L CM7 , L CM8 , L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 , Capacitance C CM1 , C CM2 , C CM3 , C CM4 ,like Figure 6 shown.

[0059] Figure 6 This is the common mode resonant cavity input impedance simulation result provided by the embodiment of the present invention, please refer to Figure 6 The common-mode resonant cavity of the oscillator also has high-order characteristics and can generate two resonance points. When designing the common-mode resonant cavity, the two resonance points of the common-mode resonant cavity are designed near the secondary frequency of the oscillator. The input impedance image is consistent with the input impedance design requirements of the common-mode resonant cavity in the design process described above.

[0060] The second stage: Based on the above inductance, capacitance and coupling coefficient, draw the following Figure 4 The inductor layout and capacitor layout shown are post-simulated.

[0061] Figure 7 is the eight-shaped tapped inductor L provided in the embodiment of the present invention CM1 、Inductance L CM2 Structural diagram, Figure 4 The figure eight inductor is further described in the figure eight inductor section. CM1 With inductance L CM2 The upper and lower metal layers are overlapped, and the coupling coefficient between them is K CM Inductance L CM3 and L CM4 , L CM5 and L CM6 , L C M7 and L CM8 Structure and inductance L CM1 and L CM2 Consistent.

[0062] Figure 8 The single core circuit CORE complete schematic diagram of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention is Figure 1 In order to expand the frequency adjustment range, the gate capacitor is designed as a switched capacitor array C composed of four differential switched capacitors. G_BANK , fixed capacitor C G And the differential connection type varactor C VAR , to achieve Fig. 9 Continuous frequency adjustment of 20.3GHz-25.8GHz.

[0063] Fig. 9 The figure shows the frequency adjustment range curve of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention. Figure 8 The switched capacitor array and varactor shown can achieve continuous frequency adjustment from 20.3 GHz to 25.8 GHz.

[0064] Fig.10 The figure shows the phase noise variation curve of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention at 100KHz, 1MHz, and 10MHz frequency offsets. By combining the multi-core oscillator with the Class-F23 oscillator, the phase noise performance of the oscillator is optimized from multiple aspects such as inductor loss and noise conversion to phase noise. At 100kHz frequency offset, the minimum phase noise can reach -97.8dBc / Hz, at 1MHz frequency offset, the minimum phase noise is -118.8dBc / Hz, and at 10MHz frequency offset, the minimum phase noise is -139dBc / Hz.

[0065] Fig.11 The figure shows the pulse sensitivity function (ISF), noise modulation function (NMF), effective pulse sensitivity function (ISF) of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention. ,eff ). Through the design of second and third harmonic resonance, the ISF obtained by multiplying ISF and NMF can be obtained. ,eff The curve has a large number of zero areas, which means that due to the existence of Class-F23, some noise is not converted into phase noise; ISF ,eff The fact that the integral value of approaches 0 indicates that, due to the design of the secondary resonant circuit, the influence of some flicker noise on the phase noise is eliminated. The obtained results are consistent with the significant advantages of the design of the present invention as described above.

[0066] Fig.12 The chip layout of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided in the embodiment of the present invention.

[0067] Based on this, the chip of the ultra-low phase noise harmonic quad-core voltage-controlled oscillator provided by the embodiment of the present invention has a core area of ​​about 0.28mm 2 .

[0068] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An ultra-low phase noise harmonic quad-core voltage-controlled oscillator, characterized in that: Including NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, gate capacitor C G1 , gate capacitance C G2 , gate capacitance C G3 , gate capacitance C G4 , drain capacitance C D1 , drain capacitance C D2 , drain capacitance C D3 , drain capacitance C D4 , floating coil capacitance C T1 , floating coil capacitance C T2 , floating coil capacitance C T3 , floating coil capacitance C T4 , three mutually coupled inductors L D1 , L G1 , L T1 The transformer T1, three mutually coupled inductors L D2 , L G2 , L T2 The transformer T2, three mutually coupled inductors L D3 , L G3 , L T3 The transformer T3, three mutually coupled inductors L D4 , L G4 , L T4 The transformer T4 and the tail inductor L S1 , tail inductance L S2 , tail inductance L S3 , tail inductance L S4 , tail inductance L S5 , tail inductance L S6 , tail inductance L S7 , tail inductance L S8 , capacitor C CM1 The inductance L coupled with each other CM1 , L CM2 The head oscillator HR1, capacitor C CM2 The inductance L coupled to each other CM3 , L CM4 The head oscillator HR2, capacitor C CM3 The inductance L coupled with each other CM5 , L CM6 The head oscillator HR3, capacitor C CM4 The inductance L coupled to each other CM7 , L CM8 The head oscillator HR4, resistor R1, resistor R2, resistor R3, resistor R4, multiple decoupling capacitors C decap ,in: The source of NMOS tube M1 and the source of NMOS tube M2 are connected to the inductor L S1 and inductor L S8 One end, inductor L S1 and inductor L S8 The other end is connected to 0 potential VSS; the drain of NMOS tube M1 and inductor L D4 The positive and drain capacitance C D1 The gate of NMOS tube M1 is connected to the inductor L G1 The negative electrode and gate capacitance C G1 connected; the drain of NMOS tube M2 and the inductor L D1 The negative electrode and drain capacitance C D1 The other end of the NM OS tube M2 is connected to the gate capacitor C G1 The other end, inductor L G4 The positive electrode is connected to the floating coil capacitor C T1 One end of the inductor L is connected T4 The positive terminal of the floating coil capacitor C T1 The other end of the inductor L T1 The negative terminal of the inductor L D1 Center tap connected to inductor L CM1 , L CM2 One end, L CM1 The other end is connected to the power supply VDD potential, L CM2 The other end is connected to capacitor C CM1 One end of the capacitor C CM1 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G1 The center tap is connected to resistor R1, and the other end of resistor R1 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M1 and NMOS tube M4; The source of NMOS tube M3 and the source of NMOS tube M4 are connected to the inductor L S2 and inductor L S3 One end, inductor L S2 and inductor L S3 The other end is connected to 0 potential VSS; the drain of NMOS tube M3 and the inductor L D1 The positive and drain capacitance C D2 The gate of NMOS tube M3 is connected to the inductor L G2 The negative electrode and gate capacitance C G2 connected; the drain of NMOS tube M4 and the inductor L D2 The negative electrode and drain capacitance C D2 The other end of the NM OS tube M4 is connected to the gate capacitor C G2 The other end, inductor L G1 The positive electrode is connected to the floating coil capacitor C T2 One end of the inductor L is connected T1 The positive terminal of the floating coil capacitor C T2 The other end of the inductor L T2 The negative terminal of the inductor L D2 Center tap connected to inductor L CM3 , L CM4 One end, L CM3 The other end is connected to VDD potential, L CM4 The other end is connected to capacitor C CM2 One end of the capacitor C CM2 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G2 The center tap is connected to resistor R2, and the other end of resistor R2 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M3 and NMOS tube M6; The source of NMOS tube M5 and the source of NMOS tube M6 are connected to the inductor L S4 and inductor L S5 One end, inductor L S4 and inductor L S5 The other end is connected to 0 potential VSS; the drain of NMOS tube M5 and inductor L D2 The positive and drain capacitance C D3 The gate of NMOS tube M5 is connected to the inductor L G3 The negative electrode and gate capacitance C G3 connected; the drain of NMOS tube M6 and the inductor L D3 The negative electrode and drain capacitance C D3 The other end of the NM OS tube M6 is connected to the gate capacitor C G3 The other end, inductor L G2 The positive electrode is connected to the floating coil capacitor C T3 One end of the inductor L is connected T2 The positive terminal of the floating coil capacitor C T3 The other end of the inductor L T3 The negative terminal of the inductor L D3 Center tap connected to inductor L CM5 , L CM6 One end, L CM5 The other end is connected to VDD potential, L CM6 The other end is connected to capacitor C CM3 One end of the capacitor C CM3 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G3 The center tap is connected to resistor R3, and the other end of resistor R3 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M5 and NMOS tube M8; The source of NMOS tube M7 and the source of NMOS tube M8 are connected to the inductor L S6 and inductor L S7 One end, inductor L S6 and inductor L S7 The other end is connected to 0 potential VSS; the drain of NMOS tube M7 and the inductor L D3 The positive and drain capacitance C D4 The gate of NMOS tube M7 is connected to the inductor L G4 The negative electrode and gate capacitance C G4 connected; the drain of NMOS tube M8 and the inductor L D4 The negative electrode and drain capacitance C D4 The other end of the NM OS tube M8 is connected to the gate capacitor C G4 The other end, inductor L G3 The positive electrode is connected to the floating coil capacitor C T4 One end of the inductor L is connected T3 The positive terminal of the floating coil capacitor C T4 The other end of the inductor L T4 The negative terminal of the inductor L D4 Center tap connected to inductor L CM7 , L CM8 One end, L CM7 The other end is connected to VDD potential, L CM8 The other end is connected to capacitor C CM4 One end of the capacitor C CM4 The other end of the inductor L is connected to the VDD potential, which provides energy for the entire voltage-controlled oscillator. G4 The center tap is connected to resistor R4, and the other end of resistor R4 is connected to V B Potential, providing gate DC voltage bias for NMOS tube M7 and NMOS tube M2, between all VDD potential and VSS potential in the oscillator, using C decap are connected.

2. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that: The four transformers T1, T2, T3, and T4 are completely consistent, and the inductance L D1 , L D2 , L D3 , L D4 The inductance value is equal to L D , inductance L T1 , L T2 , L T3 , L T4 The inductance value is equal to L T , inductance L G1 , L G2 , L G3 , L G4 The inductance value is equal to L G , capacitor C D1 , C D2 , C D3 , C D4 The capacitance value is equal to C D , capacitor C G1 , C G2 , C G3 , C G4 The capacitance value is equal to C G , capacitor C T1 , C T2 , C T3 , C T4 The capacitance value is equal to C T , inductance L D1 With inductance L G1 、Inductance L D2 With inductance L G2 、Inductance L D3 With inductance L G3 、Inductance L D4 With inductance L G4 The coupling coefficient between them is equal to K DG , inductance L G1 With inductance L T1 、Inductance L G2 With inductance L T2 、Inductance L G3 With inductance L T3 、Inductance L G4 With inductance L T4 The coupling coefficient between them is equal to K GT , inductance L D1 With inductance L T1 、Inductance L D2 With inductance L T2 、Inductance L D3 With inductance L T3 、Inductance L D4 With inductance L T4 The coupling coefficient between them is equal to K DT ; Inductance L CM1 With inductance L CM2 、Inductance L CM3 With inductance L CM4 、Inductance L CM5 With inductance L CM6 、Inductance L CM7 With inductance L CM8 The coupling coefficient between them is equal to K CM .

3. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 2, characterized in that: Gate capacitance C G1 , C G2 , C G3 , C G4 , drain capacitance C D1 , C D2 , C D3 , C D4 , floating coil capacitance C T1 , C T2 , C T3 , C T4 And transformers T1, T2, T3, T4 form the differential mode resonant cavity of the oscillator; inductor L D1 , L D2 , L D3 , L D4 、Inductance L S1 , L S2 , L S3 , L S4 , L S5 , L S6 , L S7 , L S8 , head oscillator HR1, head oscillator HR2, head oscillator HR3, and head oscillator HR4 constitute a common-mode resonant cavity of the oscillator.

4. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 3, characterized in that: In the design of the differential mode resonant cavity, the first resonance point of the differential mode resonant cavity is designed at the fundamental frequency of the oscillator oscillation, and the second and third resonance points of the differential mode resonant cavity are designed near the third harmonic of the oscillator oscillation, that is, the input impedance has an impedance peak near the first harmonic, and the input impedance has a broadened double-peak impedance near the third harmonic.

5. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 3, characterized in that: In the design of the common-mode resonant cavity, the two resonance points of the common-mode resonant cavity are designed near the second harmonic frequency of the oscillator, that is, there is a broadened double-peak input impedance near the second harmonic, so that the entire oscillator works in Class-F 23 under the oscillation state.

6. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that: Use 4 1 / 4 ring inductors L D1 , L D2 , L D3 , L D4 A toroidal inductor is formed.

7. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that: Use 4 1 / 4 ring inductors L T1 , L T2 , L T3 , L T4 A toroidal inductor is formed.

8. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that: Use 4 1 / 4 ring inductors L G1 , L G2 , L G3 , L G4 A toroidal inductor is formed.

9. The ultra-low phase noise harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that: Inductance L CM1 , L CM2 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D1 Tap point; inductance L CM3 , L CM4 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D2 Tap point; L CM5 , L CM6 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D3 Tap point; inductance L CM7 , L CM8 Use an eight-shaped inductor, with the upper and lower overlapping arrangement connected to the inductor L D4 Tap point.

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