Ka-band power amplifier circuit of 65nm CMOS (Complementary Metal Oxide Semiconductor) process

Abstract

The invention discloses a Ka-band power amplifier circuit of a 65nm CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, which belongs to the field of millimeter wave integrated circuit design and comprises an orthogonal signal generator circuit, an input matching circuit, a driving amplifier circuit, an inter-stage matching circuit, a power amplifier circuit and an output matching circuit, the orthogonal signal generator circuit is connected with the input end of the driving amplifier circuit through the input matching circuit, the output end of the driving amplifier circuit is connected with the input end of the power amplifier circuit through the inter-stage matching circuit, and the output end of the power amplifier circuit is connected with the output matching circuit. According to the power amplifier, high amplification gain and output efficiency can be obtained, the stability coefficient and the maximum available gain are higher, the synthesis loss is reduced, the chip area is reduced, the insertion loss is effectively reduced, and the working reliability of a power amplifier chip is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave integrated circuit design, specifically a Ka-band power amplifier circuit using 65nm CMOS technology. Background Art

[0002] To meet people's demand for high-speed, low-latency communication, wireless communication technology has undergone rapid development and iteration. The Ka band, as part of the 5G millimeter-wave band, has become a research hotspot due to its advantages such as low latency and high penetration. Power amplifiers, as a crucial component of RF front-end transceivers, directly affect the performance of the entire transceiver circuit due to their signal amplification capability.

[0003] Existing Ka-band power amplifier circuits generally use large-size MOSFETs. The large size of the MOSFETs leads to large parasitic resistance and capacitance, which affects the gain and output efficiency of the circuit, affects the stability of the circuit, and increases the power consumption of the circuit. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, the present invention aims to provide a Ka-band power amplifier circuit using a 65nm CMOS process to solve the problems mentioned in the background art.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A Ka-band power amplifier circuit using 65nm CMOS technology includes an orthogonal signal generator circuit, an input matching circuit, a driver amplifier circuit, an interstage matching circuit, a power amplifier circuit, and an output matching circuit.

[0007] The input terminal of the quadrature signal generator circuit is connected to the RF input interface RFin. The output terminal of the quadrature signal generator circuit is connected to the input terminal of the input matching circuit. The output terminal of the input matching circuit is connected to the input terminal of the driver amplifier circuit. The output terminal of the driver amplifier circuit is connected to the input terminal of the interstage matching circuit. The output terminal of the interstage matching circuit is connected to the input terminal of the power amplifier circuit. The output terminal of the power amplifier circuit is connected to the input terminal of the output matching circuit. The output terminal of the output matching circuit is connected to the RF output interface RFout.

[0008] As a further aspect of the present invention: the quadrature signal generator circuit includes a first quadrature signal generator circuit and a second quadrature signal generator circuit;

[0009] The first quadrature signal generator circuit includes a resistor R1 and a transformer T1;

[0010] The second quadrature signal generator circuit includes resistor R2 and transformer T2.

[0011] As a further aspect of the present invention: the input matching circuit includes transformer T3, transformer T4, transformer T5, transformer T6, capacitor C1, capacitor C2, capacitor C3 and capacitor C4;

[0012] In the first quadrature signal generator circuit, one end of the input side of transformer T1 is connected to the radio frequency input interface RFin, and the other end of the input side of transformer T1 is connected to one end of the input side of transformer T4 in the input matching circuit; the other end of the input side of transformer T4 in the input matching circuit is grounded.

[0013] A capacitor C3 is connected in parallel across the output side of transformer T4 in the input matching circuit;

[0014] In the first quadrature signal generator circuit, one end of the output side of transformer T1 is connected to one end of resistor R1, and the other end of resistor R1 is grounded; the other end of the output side of transformer T1 in the first quadrature signal generator circuit is connected to one end of the input side of transformer T3 in the input matching circuit; the other end of the input side of transformer T3 in the input matching circuit is grounded.

[0015] A capacitor C1 is connected in parallel across the output side of transformer T3 in the input matching circuit;

[0016] The center tap on the output side of transformer T3 in the input matching circuit is connected to power supply Vb1;

[0017] In the second quadrature signal generator circuit, one end of the input side of transformer T2 is connected to the radio frequency input interface RFin, and the other end of the input side of transformer T2 is connected to one end of the input side of transformer T5 in the input matching circuit; the other end of the input side of transformer T5 in the input matching circuit is grounded.

[0018] A capacitor C3 is connected in parallel across the output side of transformer T5 in the input matching circuit;

[0019] In the second quadrature signal generator circuit, one end of the output side of transformer T2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded; the other end of the output side of transformer T2 in the second quadrature signal generator circuit is connected to one end of the input side of transformer T6 in the input matching circuit; the other end of the input side of transformer T6 in the input matching circuit is grounded.

[0020] A capacitor C4 is connected in parallel across the output side of transformer T6 in the input matching circuit.

[0021] As a further aspect of the present invention: the driving amplifier circuit includes driving amplifier U1, driving amplifier U2, driving amplifier U3 and driving amplifier U4;

[0022] The positive and negative input terminals of the driver amplifier U1 are connected to the two ends of the output side of the transformer T3 in the input matching circuit, respectively.

[0023] The positive and negative input terminals of the driver amplifier U2 are connected to the two ends of the output side of the transformer T4 in the input matching circuit, respectively.

[0024] The positive and negative input terminals of the driver amplifier U3 are connected to the two ends of the output side of the transformer T5 in the input matching circuit, respectively.

[0025] The positive and negative input terminals of the driver amplifier U4 are connected to the two ends of the output side of the transformer T6 in the input matching circuit, respectively.

[0026] As a further aspect of the present invention: the interstage matching circuit includes transformer T7, transformer T8, transformer T9, transformer T10, capacitor C5, capacitor C6, capacitor C7, and capacitor C8;

[0027] The positive and negative output terminals of the driver amplifier U1 are connected to the two ends of the input side of the transformer T7 in the interstage matching circuit, respectively.

[0028] The two ends of the output side of transformer T7 are connected in parallel with the two ends of capacitor C5;

[0029] The center tap on the output side of transformer T7 is connected to power supply Vb2;

[0030] The positive and negative output terminals of the driver amplifier U2 are connected to the two ends of the input side of the transformer T8 in the interstage matching circuit, respectively.

[0031] The two ends of the output side of transformer T8 are connected in parallel with the two ends of capacitor C6;

[0032] The positive and negative output terminals of the driver amplifier U3 are connected to the two ends of the input side of the transformer T9 in the interstage matching circuit, respectively.

[0033] The two ends of the output side of transformer T9 are connected in parallel with the two ends of capacitor C7;

[0034] The positive and negative output terminals of the driver amplifier U4 are connected to the two ends of the input side of the transformer T10 in the interstage matching circuit, respectively.

[0035] The two ends of the output side of transformer T10 are connected in parallel with the two ends of capacitor C8.

[0036] As a further aspect of the present invention: the power amplifier circuit includes power amplifier U5, power amplifier U6, power amplifier U7 and power amplifier U8;

[0037] In the power amplifier circuit, the positive and negative input terminals of power amplifier U5 are connected to the two ends of the output side of transformer T7 in the interstage matching circuit, respectively.

[0038] In the power amplifier circuit, the positive and negative input terminals of the power amplifier U6 are connected to the two ends of the output side of the transformer T8 in the interstage matching circuit, respectively.

[0039] In the power amplifier circuit, the positive and negative input terminals of power amplifier U7 are connected to the two ends of the output side of transformer T9 in the interstage matching circuit, respectively.

[0040] In the power amplifier circuit, the positive and negative input terminals of the power amplifier U8 are connected to the two ends of the output side of the transformer T10 in the interstage matching circuit.

[0041] As a further aspect of the present invention: the output matching circuit includes transformer T11, transformer T12, transformer T13, transformer T14, capacitor C9, capacitor C10, capacitor C11, and capacitor C12;

[0042] The two ends of the input side of transformer T11 in the output matching circuit are connected to the two ends of the output of power amplifier U5 in the power amplifier circuit;

[0043] The center tap on the input side of transformer T11 in the output matching circuit is connected to power supply VDD1;

[0044] The two ends of the output side of transformer T11 are connected in parallel with the two ends of capacitor C9;

[0045] The two ends of the input side of transformer T12 in the output matching circuit are connected to the two ends of the output of power amplifier U6 in the power amplifier circuit;

[0046] The two ends of the output side of transformer T12 are connected in parallel with the two ends of capacitor C10;

[0047] The two ends of the input side of transformer T13 in the output matching circuit are connected to the two ends of the output terminal of power amplifier U7 in the power amplifier circuit;

[0048] The two ends of the output side of transformer T13 are connected in parallel with the two ends of capacitor C11;

[0049] The two ends of the input side of transformer T14 in the output matching circuit are connected to the two ends of the output of power amplifier U8 in the power amplifier circuit;

[0050] The two ends of the output side of transformer T14 are connected in parallel with the two ends of capacitor C12;

[0051] One end of the output side of transformer T11 and one end of the output side of transformer T14 are grounded;

[0052] The other end of the output side of transformer T11 is connected to one end of the output side of transformer T12, the other end of the output side of transformer T14 is connected to one end of the output side of transformer T13, and the other ends of the output sides of transformer T12 and transformer T13 are simultaneously connected to the RF output interface RFout.

[0053] As a further aspect of the present invention: the driving amplifier U1 includes MOS transistor M5 and MOS transistor M6, the gate of MOS transistor M5 is the positive input terminal of driving amplifier U1, and the gate of MOS transistor M6 is the negative input terminal of driving amplifier U1.

[0054] The sources of MOSFET M5 and MOSFET M6 are both grounded;

[0055] The drain of MOSFET M5 is connected to one end of capacitor Cg2, and the other end of capacitor Cg2 is connected to the gate of MOSFET M6.

[0056] The drain of MOSFET M6 is connected to one end of capacitor Cg1, and the other end of capacitor Cg1 is connected to the gate of MOSFET M5.

[0057] The drain of MOSFET M5 is connected to the positive output terminal of amplifier U1, and the drain of MOSFET M6 is connected to the negative output terminal of amplifier U1.

[0058] Capacitors Cg1 and Cg2 are neutralizing capacitors for the driving amplifier.

[0059] As a further aspect of the present invention: the power amplifier U5 includes MOS transistors M1, M2, M3 and M4;

[0060] The gate of MOSFET M1 is the positive input terminal of power amplifier U5, and the negative input terminal of power amplifier U5 is the gate of MOSFET M2.

[0061] The sources of both MOSFET M1 and MOSFET M2 are grounded;

[0062] The drain of MOSFET M1 is connected to the source of MOSFET M3 and one end of capacitor Cg3, while the other end of capacitor Cg3 is connected to the gate of MOSFET M2.

[0063] The drain of MOSFET M2 is connected to the source of MOSFET M4 and one end of capacitor Cg4, while the other end of capacitor Cg4 is connected to the gate of MOSFET M1.

[0064] The gates of MOSFET M3 and MOSFET M4 are simultaneously connected to the power supply VCAS.

[0065] The drain of MOSFET M3 is the positive output terminal of power amplifier U5, and the drain of MOSFET M4 is the negative output terminal of power amplifier U5.

[0066] Capacitors Cg3 and Cg4 are neutralizing capacitors for the power amplifier.

[0067] As a further aspect of the present invention: the driving amplifiers U1, U2, U3 and U4 have the same model and internal structure; the power amplifiers U5, U6, U7 and U8 have the same model and internal structure.

[0068] As a further aspect of the present invention: the primary coil of the transformer in the input matching circuit, inter-stage matching circuit and output matching circuit uses M8 layer metal, and the secondary coil uses M9 layer thick metal.

[0069] A satellite communication system comprising a Ka-band power amplifier circuit using a 65nm CMOS process as described in any one of claims 1-11.

[0070] Compared with the prior art, the beneficial effects of the present invention are:

[0071] This invention features a four-channel combined circuit structure, avoiding the large parasitic resistance and capacitance issues associated with large-size MOSFETs. This results in higher amplification gain and output efficiency, higher stability coefficient, and maximum usable gain. Furthermore, a neutralizing capacitor is added to reduce the impact of parasitic capacitance, further improving gain and stability. The matching transformer in this invention increases the Q value of each coil, reducing combining losses. Simultaneously, it achieves power combining and output matching, reducing chip area. A parallel capacitor is added after the secondary coil, effectively increasing the secondary coil inductance and improving the passive efficiency of the matching network. This circuit employs a high-power series-type Doherty load modulation network, achieving efficiency improvement at the power back-off point through active load modulation. As the auxiliary amplifier output current increases, the main amplifier load impedance decreases. The circuit uses power combining output from four amplifiers, which is beneficial for the design and implementation of a wideband, low-loss output matching network. Integrating the impedance inverter into the transformer output matching network effectively reduces insertion loss, decreases chip size, and ensures the reliability of the power amplifier chip. Attached Figure Description

[0072] Figure 1 This is a circuit diagram of a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in an embodiment.

[0073] Figure 2 This is a schematic diagram of the driver amplifier circuit in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in an embodiment.

[0074] Figure 3 This is a circuit diagram of the power amplifier circuit in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in an embodiment.

[0075] Figure 4 The circuit layout of the driver amplifier circuit in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in the embodiment is shown below.

[0076] Figure 5 The circuit layout of the power amplifier circuit in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in the embodiment is shown below.

[0077] Figure 6 The circuit layout of the input matching circuit in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in the embodiment is shown below.

[0078] Figure 7 This is a schematic diagram of the simulated S-parameter results in a Ka-band power amplifier circuit using a 65nm CMOS process disclosed in the embodiment. Detailed Implementation

[0079] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0080] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0081] Please see Figure 1-7 A Ka-band power amplifier circuit using 65nm CMOS technology includes an orthogonal signal generator circuit, an input matching circuit, a driver amplifier circuit, an interstage matching circuit, a power amplifier circuit, and an output matching circuit.

[0082] The input terminal of the quadrature signal generator circuit is connected to the RF input interface RFin. The output terminal of the quadrature signal generator circuit is connected to the input terminal of the input matching circuit. The output terminal of the input matching circuit is connected to the input terminal of the driver amplifier circuit. The output terminal of the driver amplifier circuit is connected to the input terminal of the interstage matching circuit. The output terminal of the interstage matching circuit is connected to the input terminal of the power amplifier circuit. The output terminal of the power amplifier circuit is connected to the input terminal of the output matching circuit. The output terminal of the output matching circuit is connected to the RF output interface RFout.

[0083] The quadrature signal generator circuit includes a first quadrature signal generator circuit and a second quadrature signal generator circuit;

[0084] The first quadrature signal generator circuit includes a resistor R1 and a transformer T1;

[0085] The second quadrature signal generator circuit includes resistor R2 and transformer T2;

[0086] The input matching circuit includes transformers T3, T4, T5, and T6, as well as capacitors C1, C2, C3, and C4.

[0087] In the first quadrature signal generator circuit, one end of the input side of transformer T1 is connected to the radio frequency input interface RFin, and the other end of the input side of transformer T1 is connected to one end of the input side of transformer T4 in the input matching circuit; the other end of the input side of transformer T4 in the input matching circuit is grounded.

[0088] A capacitor C3 is connected in parallel across the output side of transformer T4 in the input matching circuit;

[0089] In the first quadrature signal generator circuit, one end of the output side of transformer T1 is connected to one end of resistor R1, and the other end of resistor R1 is grounded; the other end of the output side of transformer T1 in the first quadrature signal generator circuit is connected to one end of the input side of transformer T3 in the input matching circuit; the other end of the input side of transformer T3 in the input matching circuit is grounded.

[0090] A capacitor C1 is connected in parallel across the output side of transformer T3 in the input matching circuit;

[0091] The center tap on the output side of transformer T3 in the input matching circuit is connected to power supply Vb1;

[0092] In the second quadrature signal generator circuit, one end of the input side of transformer T2 is connected to the radio frequency input interface RFin, and the other end of the input side of transformer T2 is connected to one end of the input side of transformer T5 in the input matching circuit; the other end of the input side of transformer T5 in the input matching circuit is grounded.

[0093] A capacitor C3 is connected in parallel across the output side of transformer T5 in the input matching circuit;

[0094] In the second quadrature signal generator circuit, one end of the output side of transformer T2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded; the other end of the output side of transformer T2 in the second quadrature signal generator circuit is connected to one end of the input side of transformer T6 in the input matching circuit; the other end of the input side of transformer T6 in the input matching circuit is grounded.

[0095] A capacitor C4 is connected in parallel across the output side of transformer T6 in the input matching circuit;

[0096] The driver amplifier circuit includes driver amplifier U1, driver amplifier U2, driver amplifier U3 and driver amplifier U4;

[0097] The positive and negative input terminals of the driver amplifier U1 are connected to the two ends of the output side of the transformer T3 in the input matching circuit, respectively.

[0098] The positive and negative input terminals of the driver amplifier U2 are connected to the two ends of the output side of the transformer T4 in the input matching circuit, respectively.

[0099] The positive and negative input terminals of the driver amplifier U3 are connected to the two ends of the output side of the transformer T5 in the input matching circuit, respectively.

[0100] The positive and negative input terminals of the driver amplifier U4 are connected to the two ends of the output side of the transformer T6 in the input matching circuit, respectively.

[0101] The interstage matching circuit includes transformers T7, T8, T9, and T10, and capacitors C5, C6, C7, and C8.

[0102] The positive and negative output terminals of the driver amplifier U1 are connected to the two ends of the input side of the transformer T7 in the interstage matching circuit, respectively.

[0103] The two ends of the output side of transformer T7 are connected in parallel with the two ends of capacitor C5;

[0104] The center tap on the output side of transformer T7 is connected to power supply Vb2;

[0105] The positive and negative output terminals of the driver amplifier U2 are connected to the two ends of the input side of the transformer T8 in the interstage matching circuit, respectively.

[0106] The two ends of the output side of transformer T8 are connected in parallel with the two ends of capacitor C6;

[0107] The positive and negative output terminals of the driver amplifier U3 are connected to the two ends of the input side of the transformer T9 in the interstage matching circuit, respectively.

[0108] The two ends of the output side of transformer T9 are connected in parallel with the two ends of capacitor C7;

[0109] The positive and negative output terminals of the driver amplifier U4 are connected to the two ends of the input side of the transformer T10 in the interstage matching circuit, respectively.

[0110] The two ends of the output side of transformer T10 are connected in parallel with the two ends of capacitor C8;

[0111] The power amplifier circuit includes power amplifier U5, power amplifier U6, power amplifier U7 and power amplifier U8;

[0112] In the power amplifier circuit, the positive and negative input terminals of power amplifier U5 are connected to the two ends of the output side of transformer T7 in the interstage matching circuit, respectively.

[0113] In the power amplifier circuit, the positive and negative input terminals of the power amplifier U6 are connected to the two ends of the output side of the transformer T8 in the interstage matching circuit, respectively.

[0114] In the power amplifier circuit, the positive and negative input terminals of power amplifier U7 are connected to the two ends of the output side of transformer T9 in the interstage matching circuit, respectively.

[0115] In the power amplifier circuit, the positive and negative input terminals of the power amplifier U8 are connected to the two ends of the output side of the transformer T10 in the interstage matching circuit, respectively.

[0116] The output matching circuit includes transformers T11, T12, T13, and T14, capacitors C9, C10, C11, and C12;

[0117] The two ends of the input side of transformer T11 in the output matching circuit are connected to the two ends of the output of power amplifier U5 in the power amplifier circuit;

[0118] The center tap on the input side of transformer T11 in the output matching circuit is connected to power supply VDD1;

[0119] The two ends of the output side of transformer T11 are connected in parallel with the two ends of capacitor C9;

[0120] The two ends of the input side of transformer T12 in the output matching circuit are connected to the two ends of the output of power amplifier U6 in the power amplifier circuit;

[0121] The two ends of the output side of transformer T12 are connected in parallel with the two ends of capacitor C10;

[0122] The two ends of the input side of transformer T13 in the output matching circuit are connected to the two ends of the output terminal of power amplifier U7 in the power amplifier circuit;

[0123] The two ends of the output side of transformer T13 are connected in parallel with the two ends of capacitor C11;

[0124] The two ends of the input side of transformer T14 in the output matching circuit are connected to the two ends of the output of power amplifier U8 in the power amplifier circuit;

[0125] The two ends of the output side of transformer T14 are connected in parallel with the two ends of capacitor C12;

[0126] One end of the output side of transformer T11 and one end of the output side of transformer T14 are grounded;

[0127] The other end of the output side of transformer T11 is connected to one end of the output side of transformer T12, the other end of the output side of transformer T14 is connected to one end of the output side of transformer T13, and the other ends of the output sides of transformer T12 and transformer T13 are simultaneously connected to the RF output interface RFout.

[0128] Transformer T11 and capacitor C9 form the first auxiliary amplifier; transformer T14 and capacitor C12 form the second auxiliary amplifier.

[0129] Transformer T12 and capacitor C10 form the first main amplifier; transformer T13 and capacitor C1 form the second main amplifier.

[0130] The driver amplifier U1 includes MOSFET M5 and MOSFET M6. The gate of MOSFET M5 is the positive input terminal of driver amplifier U1, and the gate of MOSFET M6 is the negative input terminal of driver amplifier U1.

[0131] The sources of MOSFET M5 and MOSFET M6 are both grounded;

[0132] The drain of MOSFET M5 is connected to one end of capacitor Cg2, and the other end of capacitor Cg2 is connected to the gate of MOSFET M6.

[0133] The drain of MOSFET M6 is connected to one end of capacitor Cg1, and the other end of capacitor Cg1 is connected to the gate of MOSFET M5.

[0134] The drain of MOSFET M5 is connected to the positive output terminal of amplifier U1, and the drain of MOSFET M6 is connected to the negative output terminal of amplifier U1.

[0135] Capacitors Cg1 and Cg2 are neutralizing capacitors for the driving amplifier;

[0136] The drive amplifiers U1, U2, U3, and U4 have the same model and internal structure, which facilitates the use of the device.

[0137] Power amplifier U5 includes MOSFETs M1, M2, M3, and M4;

[0138] The gate of MOSFET M1 is the positive input terminal of power amplifier U5, and the negative input terminal of power amplifier U5 is the gate of MOSFET M2.

[0139] The sources of both MOSFET M1 and MOSFET M2 are grounded;

[0140] The drain of MOSFET M1 is connected to the source of MOSFET M3 and one end of capacitor Cg3, while the other end of capacitor Cg3 is connected to the gate of MOSFET M2.

[0141] The drain of MOSFET M2 is connected to the source of MOSFET M4 and one end of capacitor Cg4, while the other end of capacitor Cg4 is connected to the gate of MOSFET M1.

[0142] The gates of MOSFET M3 and MOSFET M4 are simultaneously connected to the power supply VCAS.

[0143] The drain of MOSFET M3 is the positive output terminal of power amplifier U5, and the drain of MOSFET M4 is the negative output terminal of power amplifier U5.

[0144] Capacitors Cg3 and Cg4 are neutralizing capacitors for the power amplifier;

[0145] Power amplifiers U5, U6, U7, and U8 have the same model number and internal structure, which facilitates the use of the device.

[0146] The overall circuit design of this invention is suitable for 65nm CMOS process. It can achieve the performance described above at an operating voltage of 1.2V.

[0147] The overall circuit of this invention is a four-way combined structure. Each amplifying MOS transistor (M1-M4) employs a parallel structure of eight MOS transistors with a gate width of 45µm, achieving a total gate width of 360µm, which can meet power output requirements greater than 15dBm. Simultaneously, the moderate size of each individual MOS transistor avoids the problem of large parasitic resistance and capacitance associated with larger MOS transistors, resulting in higher amplification gain and output efficiency. The power stage amplifier adopts a common-source, common-gate structure, offering higher stability and maximum usable gain. Furthermore, a neutralizing capacitor is added to reduce the influence of parasitic capacitance, further improving gain and stability.

[0148] The driver-stage differential amplifier of this invention employs a parallel structure of four MOS transistors with a gate width of 50µm, resulting in a total gate width of 200µm. This structure amplifies the input signal in the first stage before outputting it to the final amplifier stage. Due to the layout rules of the CMOS 65nm process, the gates of all MOS transistors in the entire PA chip need to be vertically arranged. Therefore, the driver-stage amplifier uses a differential common-source circuit, and a neutralizing capacitor is also included.

[0149] This invention relates to a matching transformer design. The primary coil of the transformer uses an M8-layer metal core, while the secondary coil uses an M9-layer thick metal core, increasing the Q value of each coil and reducing combined losses. This simultaneously achieves power combining and output matching, reducing chip area. A parallel capacitor is added after the secondary coil, resulting in a higher equivalent secondary coil inductance and improving the passive efficiency of the matching network.

[0150] This circuit employs a high-power series-type Doherty load modulation network, achieving efficiency improvement at the power back-off point through active load modulation. As the output current of the auxiliary amplifier increases, the load impedance of the main amplifier decreases. The circuit utilizes the power combining output of four amplifiers, which is beneficial for the design and implementation of a wideband, low-loss output matching network. The impedance inverter is integrated into the transformer output matching network, effectively reducing insertion loss and minimizing chip size.

[0151] This invention belongs to the technical field of millimeter-wave integrated circuit design, and relates to a power amplifier based on 65nm CMOS process, with an operating frequency of 26-30GHz, adopting a series Doherty structure, which can be used in satellite communication systems and broadband communication.

[0152] At a 1.2V operating voltage, the simulated power amplifier exhibits a 3dB bandwidth of 26-30GHz, an in-band gain greater than 20dB in the 24.5-31.5GHz range, a simulated saturated output power of 15.1dBm, a maximum PAE efficiency of 13%, and a power consumption of 0.2W. The 1.2V operating voltage is the rated voltage for 65nm process transistors. Compared to techniques that use higher operating voltages to achieve the required output power, this design ensures the reliability of the power amplifier chip.

[0153] The power amplifier of this invention adopts a Doherty structure, which improves the efficiency at the power back-off point through active load modulation, and does not require an additional power supply modulator and baseband signal processing circuit. It is widely used in the design of high-efficiency amplifiers.

[0154] In 65nm CMOS technology, the transistor operating voltage is 1V, which is lower than that of 180nm and earlier CMOS nodes. This results in reduced output power and efficiency of power amplifiers. Furthermore, advanced CMOS processes place stricter requirements on layout regularity. Power amplifier structures designed based on previous generation nodes are difficult to apply directly. Therefore, this design proposes a 26-30GHz power amplifier circuit based on 65nm CMOS technology for broadband communication.

[0155] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered exemplary and not restrictive in all respects. The scope of the invention is defined by the appended claims rather than the foregoing description, and therefore all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0156] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A Ka-band power amplifier circuit using 65nm CMOS technology, characterized in that: It includes an orthogonal signal generator circuit, an input matching circuit, a driver amplifier circuit, an inter-stage matching circuit, a power amplifier circuit and an output matching circuit; The input end of the orthogonal signal generator circuit is connected to the radio frequency input interface RFin, the output end of the orthogonal signal generator circuit is connected to the input end of the input matching circuit, the output end of the input matching circuit is connected to the input end of the driver amplifier circuit, the output end of the driver amplifier circuit is connected to the input end of the inter-stage matching circuit, the output end of the inter-stage matching circuit is connected to the input end of the power amplifier circuit, the output end of the power amplifier circuit is connected to the input end of the output matching circuit, and the output end of the output matching circuit is connected to the radio frequency output interface RFout.

2. The 65nm CMOS Ka-band power amplifier circuit according to claim 1, characterized in that: The orthogonal signal generator circuit includes a first orthogonal signal generator circuit and a second orthogonal signal generator circuit; The first quadrature signal generator circuit includes a resistor R1 and a transformer T1; The second quadrature signal generator circuit includes a resistor R2 and a transformer T2.

3. The 65nm CMOS Ka-band power amplifier circuit according to claim 2, characterized in that: The input matching circuit includes a transformer T3, a transformer T4, a transformer T5, a transformer T6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; One end of the input side of the transformer T1 in the first orthogonal signal generator circuit is connected to the radio frequency input interface RFin, and the other end of the input side of the transformer T1 in the first orthogonal signal generator circuit is connected to one end of the input side of the transformer T4 in the input matching circuit; the other end of the input side of the transformer T4 in the input matching circuit is grounded; A capacitor C3 connected in parallel at both ends of the output side of the transformer T4 in the input matching circuit; One end of the output side of the transformer T1 in the first orthogonal signal generator circuit is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; the other end of the output side of the transformer T1 in the first orthogonal signal generator circuit is connected to one end of the input side of the transformer T3 in the input matching circuit; the other end of the input side of the transformer T3 in the input matching circuit is grounded; The two-terminal parallel capacitor C1 of the output side of the transformer T3 in the input matching circuit; The center tap on the output side of the transformer T3 in the input matching circuit is connected to the power supply Vb1; One end of the input side of the transformer T2 in the second orthogonal signal generator circuit is connected to the radio frequency input interface RFin, and the other end of the input side of the transformer T2 in the second orthogonal signal generator circuit is connected to one end of the input side of the transformer T5 in the input matching circuit; the other end of the input side of the transformer T5 in the input matching circuit is grounded; A capacitor C3 connected in parallel at both ends of the output side of the transformer T5 in the input matching circuit; One end of the output side of the transformer T2 in the second orthogonal signal generator circuit is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded; the other end of the output side of the transformer T2 in the second orthogonal signal generator circuit is connected to one end of the input side of the transformer T6 in the input matching circuit; the other end of the input side of the transformer T6 in the input matching circuit is grounded; A capacitor C4 is connected in parallel to both ends of the output side of the transformer T6 in the input matching circuit.

4. The 65nm CMOS Ka-band power amplifier circuit according to claim 3, characterized in that: The driving amplifier circuit includes a driving amplifier U1, a driving amplifier U2, a driving amplifier U3 and a driving amplifier U4; The positive input terminal and the negative input terminal of the driving amplifier U1 are respectively connected to the two ends of the output side of the transformer T3 in the input matching circuit; The positive input terminal and the negative input terminal of the driving amplifier U2 are respectively connected to the two ends of the output side of the transformer T4 in the input matching circuit; The positive input terminal and the negative input terminal of the driving amplifier U3 are respectively connected to the two ends of the output side of the transformer T5 in the input matching circuit; The positive input terminal and the negative input terminal of the driving amplifier U4 are respectively connected to the two ends of the output side of the transformer T6 in the input matching circuit.

5. The 65nm CMOS Ka-band power amplifier circuit according to claim 4, characterized in that: The inter-stage matching circuit includes a transformer T7, a transformer T8, a transformer T9, a transformer T10, a capacitor C5, a capacitor C6, a capacitor C7 and a capacitor C8; The positive output terminal and the negative output terminal of the driving amplifier U1 are respectively connected to the two ends of the input side of the transformer T7 in the inter-stage matching circuit; The two ends of the output side of the transformer T7 are connected in parallel with the two ends of the capacitor C5; The center tap on the output side of transformer T7 is connected to the power source Vb2; The positive output terminal and the negative output terminal of the driving amplifier U2 are respectively connected to the two ends of the input side of the transformer T8 in the inter-stage matching circuit; The two ends of the output side of the transformer T8 are connected in parallel with the two ends of the capacitor C6; The positive output terminal and the negative output terminal of the driving amplifier U3 are respectively connected to the two ends of the input side of the transformer T9 in the inter-stage matching circuit; The two ends of the output side of the transformer T9 are connected in parallel with the two ends of the capacitor C7; The positive output terminal and the negative output terminal of the driving amplifier U4 are respectively connected to the two ends of the input side of the transformer T10 in the inter-stage matching circuit; Both ends of the output side of the transformer T10 are connected in parallel to both ends of the capacitor C8.

6. The 65nm CMOS Ka-band power amplifier circuit according to claim 5, characterized in that: The power amplifier circuit includes power amplifier U5, power amplifier U6, power amplifier U7 and power amplifier U8; The positive input terminal and the negative input terminal of the power amplifier U5 in the power amplifier circuit are respectively connected to the two ends of the output side of the transformer T7 in the inter-stage matching circuit; The positive input terminal and the negative input terminal of the power amplifier U6 in the power amplifier circuit are respectively connected to the two ends of the output side of the transformer T8 in the inter-stage matching circuit; The positive input terminal and the negative input terminal of the power amplifier U7 in the power amplifier circuit are respectively connected to the two ends of the output side of the transformer T9 in the inter-stage matching circuit; The positive input terminal and the negative input terminal of the power amplifier U8 in the power amplifier circuit are respectively connected to the two ends of the output side of the transformer T10 in the inter-stage matching circuit.

7. The 65nm CMOS Ka-band power amplifier circuit according to claim 6, characterized in that: The output matching circuit includes a transformer T11, a transformer T12, a transformer T13, a transformer T14, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12; The two ends of the input side of the transformer T11 in the output matching circuit are connected to the two ends of the output end of the power amplifier U5 in the power amplifier circuit; The center tap on the input side of the transformer T11 in the output matching circuit is connected to the power supply VDD1; The two ends of the output side of the transformer T11 are connected in parallel with the two ends of the capacitor C9; The two ends of the input side of the transformer T12 in the output matching circuit are connected to the two ends of the output end of the power amplifier U6 in the power amplifier circuit; The two ends of the output side of the transformer T12 are connected in parallel with the two ends of the capacitor C10; The two ends of the input side of the transformer T13 in the output matching circuit are connected to the two ends of the output end of the power amplifier U7 in the power amplifier circuit; The two ends of the output side of the transformer T13 are connected in parallel with the two ends of the capacitor C11; The two ends of the input side of the transformer T14 in the output matching circuit are connected to the two ends of the output end of the power amplifier U8 in the power amplifier circuit; The two ends of the output side of the transformer T14 are connected in parallel with the two ends of the capacitor C12; One end of the output side of the transformer T11 and the output side of the transformer T14 is grounded; The other end of the output side of transformer T11 is connected to one end of the output side of transformer T12, the other end of the output side of transformer T14 is connected to one end of the output side of transformer T13, and the other end of the output side of transformer T12 and the other end of the output side of transformer T13 are both connected to the RF output interface RFout.

8. The 65nm CMOS Ka-band power amplifier circuit according to claim 7, characterized in that: The driving amplifier U1 includes a MOS tube M5 and a MOS tube M6, wherein the gate of the MOS tube M5 is the positive input terminal of the driving amplifier U1, and the gate of the MOS tube M6 is the negative input terminal of the driving amplifier U1; The source of the MOS tube M5 and the source of the MOS tube M6 are both grounded; The drain of the MOS tube M5 is connected to one end of the capacitor Cg2, and the other end of the capacitor Cg2 is connected to the gate of the MOS tube M6; The drain of the MOS tube M6 is connected to one end of the capacitor Cg1, and the other end of the capacitor Cg1 is connected to the gate of the MOS tube M5; The drain of the MOS tube M5 is connected to the positive output terminal of the driving amplifier U1, and the drain of the MOS tube M6 is connected to the negative output terminal of the driving amplifier U1; Capacitor Cg1 and capacitor Cg2 are neutralizing capacitors of the driving amplifier.

9. The 65nm CMOS Ka-band power amplifier circuit according to claim 8, characterized in that: The power amplifier U5 includes a MOS tube M1, a MOS tube M2, a MOS tube M3 and a MOS tube M4; The gate of MOS tube M1 is the positive input terminal of power amplifier U5, and the gate of MOS tube M2 is the negative input terminal of power amplifier U5; The source of the MOS tube M1 and the source of the MOS tube M2 are both grounded; The drain of the MOS tube M1 is connected to the source of the MOS tube M3 and one end of the capacitor Cg3 at the same time, and the other end of the capacitor Cg3 is connected to the gate of the MOS tube M2; The drain of the MOS tube M2 is connected to the source of the MOS tube M4 and one end of the capacitor Cg4 at the same time, and the other end of the capacitor Cg4 is connected to the gate of the MOS tube M1; The gate of the MOS tube M3 and the gate of the MOS tube M4 are simultaneously connected to the power supply VCAS; The drain of the MOS tube M3 is the positive output terminal of the power amplifier U5, and the drain of the MOS tube M4 is the negative output terminal of the power amplifier U5; Capacitor Cg3 and capacitor Cg4 are neutralizing capacitors of the power amplifier.

10. The 65nm CMOS Ka-band power amplifier circuit according to claim 9, characterized in that: The models and internal structures of the driving amplifiers U1, U2, U3 and U4 are the same; the models and internal structures of the power amplifiers U5, U6, U7 and U8 are the same.

11. The 65nm CMOS Ka-band power amplifier circuit according to claim 10, characterized in that: The primary coil of the transformer in the input matching circuit, the inter-stage matching circuit and the output matching circuit adopts M8 layer metal, and the secondary coil adopts M9 layer thick metal.

12. A satellite communication system, characterized in that: A Ka-band power amplifier circuit comprising a 65nm CMOS process as described in any one of claims 1-11.

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