Multi-phase clock generation circuit and multi-phase clock calibration circuit

Abstract

According to an embodiment of the present disclosure, a multi-phase clock generation circuit and a multi-phase clock calibration circuit are provided. The multi-phase clock generation circuit comprises a multi-phase clock generation circuit; a multi-phase clock error detection circuit comprises a first group of direct current component extraction modules, a phase difference detection circuit, a second group of direct current component extraction modules, a multi-path selection module and a comparison module, and multi-phase clock signals are input to the comparison module through the first group of direct current component extraction modules and the multi-path selection module. A multi-phase clock signal is input into the comparison module through the phase difference detection circuit, the second direct current component extraction module and the multi-path selection module, and the comparison module outputs a detection error; the digital control circuit is used for distributing a selection module number for each sub-module in the multi-path selection module; the multi-phase clock adjusting circuit comprises a duty ratio adjusting circuit and a phase adjusting circuit. According to the embodiment of the invention, the calibration process of the chip can be effectively reduced, the chip design is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to a clock generating circuit, and in particular to a multi-phase clock generating circuit and a multi-phase clock calibrating circuit. Background Art

[0002] As data centers continue to grow in demand for high-speed communications, the communication rate requirements for serial interfaces are also increasing. However, traditional analog receivers are no longer able to meet these high-speed communication requirements. In recent years, new receivers based on high-speed time-interleaved analog-to-digital converters (Time-Interleaved ADCs) have gradually become mainstream.

[0003] High-speed time-interleaved analog-to-digital converters achieve efficient data conversion by using multiple clocks to sample the same analog signal in parallel. However, the phase error between the multi-phase clocks will have a significant impact on the signal-to-noise distortion ratio. This error will degrade the performance of the analog-to-digital converter and further affect the bit error rate of the receiver, becoming an important factor restricting the reliability of high-speed communications.

[0004] In the prior art, there is an eight-phase clock generation scheme using a delay-locked loop. However, in the locking process of the delay-locked loop, accurate delay calibration must be performed, otherwise it is easy to have a locking delay that is not equal to the clock period, but equal to an integer multiple of the clock period. After completing the calibration of the delay-locked loop, it is necessary to further calibrate the duty cycle and phase deviation of the clock to ensure the stability and accuracy of the clock signal. However, this method makes the overall chip structure complex and the calibration process is also relatively lengthy. Summary of the invention

[0005] In view of the problems existing in the prior art, embodiments of the present disclosure provide a multi-phase clock generation circuit and a multi-phase clock calibration circuit.

[0006] According to a first aspect, an embodiment of the present disclosure provides a multi-phase clock generation circuit, which includes a multi-phase clock generation circuit, which generates a multi-phase clock signal through a plurality of serially connected registers; a multi-phase clock error detection circuit, which includes a first group of DC component extraction modules, a phase difference detection circuit, a second group of DC component extraction modules, a multi-way selection module and a comparison module, wherein the multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or is input to the comparison module via the multi-way selection module and the first group of DC component extraction modules, the multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module and the multi-way selection module or is input to the comparison module via the phase difference detection circuit, the multi-way selection module and the second DC component extraction module, and the comparison module outputs a detection error; a digital control circuit, which assigns a selection module number to each submodule in the multi-way selection module and corresponds the number to each detection error; a multi-phase clock adjustment circuit, which includes a duty cycle adjustment circuit and a phase adjustment circuit, and the multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

[0007] In the embodiments of the present disclosure, the positions of the multi-way selection module and the DC component extraction module can be interchanged. The multi-way selection module can be placed after the DC component extraction module to select and output a detection value of a clock signal detection, such as a duty cycle or a phase difference value. It can also be placed before the DC component extraction module, and the result is the same for the comparison module. Each submodule in the multi-way selection module will select a group of duty cycle detection values ​​or a group of phase difference detection values ​​to input into the comparison module. The multi-phase clock adjustment circuit fine-tunes the duty cycle and phase, and the adjustment range can be picosecond level.

[0008] The multi-phase clock generation circuit provided in the embodiment of the present disclosure has a simple structure and does not require a delay locked loop, thus avoiding a complicated calibration process and simplifying chip design.

[0009] Optionally, the multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or is input to the comparison module via the multi-way selection module and the first group of DC component extraction modules, for detecting the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal. The duty cycle information can be extracted by measuring the DC component of the signal, and the DC component extraction module can be implemented using a low-pass filter, thereby making the duty cycle detection circuit structure simple.

[0010] Optionally, the phase difference detection circuit detects the phase difference between at least two groups of clock signals, and the second DC component extraction module extracts the DC component from the phase difference between the two groups of clock signals.

[0011] Optionally, the phase difference detection circuit includes an XOR logic circuit, and the phase difference detection circuit performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 90 degrees, clock signals with phases of 0 degrees and 270 degrees, clock signals with phases of 180 degrees and 270 degrees, and clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals, and the second DC component extraction module extracts the DC component from the signal superimposed by the first and third phase difference signals, and extracts the DC component from the signal superimposed by the second and fourth phase difference signals. The phase difference detection circuit only needs to use a logic circuit and a DC component extraction module, and has a simple structure and simplified design. Superimposing the four groups of clocks after phase difference detection can keep the load of each clock signal balanced and avoid the detection process affecting the clock signal.

[0012] Optionally, the multi-phase clock generating circuit according to the first aspect of the present disclosure also includes a multi-phase clock duty cycle adjustment circuit, which includes a logic circuit and a delay circuit, which receives the output of the multi-phase clock generating circuit, and uses the logic circuit to perform a logic operation on each clock signal and another clock signal in the multi-phase clock signal delayed by the delay circuit as a group of signals to obtain a multi-phase clock signal with a predetermined duty cycle, wherein the delay size of the delay circuit is determined according to the predetermined duty cycle. When the duty cycle of the clock signal output by the multi-phase clock generating circuit is significantly different from the required duty cycle, the duty cycle can be adjusted by the duty cycle adjustment circuit. The above-mentioned duty cycle adjustment method adjusts the duty cycle by performing a logic operation on the clock signal and the other phase clocks after the delay.

[0013] Optionally, the phase adjustment circuit includes at least one set of connected inverters and variable capacitors, each phase adjustment circuit is used to adjust the phase of a clock signal, and when the digital control circuit determines that the phase of one or more clock signals needs to be adjusted according to the selection module number and the detection error, a control signal is sent to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor. The circuit structure is simple, and a high-precision adjustment result can be obtained without a complicated adjustment process.

[0014] Optionally, the duty cycle adjustment circuit includes a variable number of connected PMOS and a variable number of connected NMOS, each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal, and when the digital control circuit determines the duty cycle of one or more clock signals that need to be adjusted according to the selection module number and the detection error, a control signal is sent to the duty cycle adjustment circuit of the one or more clock signals to adjust the number of connected PMOS or the number of connected NMOS in the corresponding duty cycle adjustment circuit. Here, the PMOS and NMOS can be connected to form an inverter structure, and the number of PMOS transistors and NMOS transistors is adjusted to change the phase characteristics of the output signal.

[0015] Optionally, the multi-phase clock generation circuit includes 8 cascaded shift registers, and the four-phase clock signal is input to the clock terminals of the first to fourth shift registers and the fifth to eighth shift registers respectively to obtain an eight-phase clock signal. The multi-phase clock generation circuit can also be used to generate four-phase, sixteen-phase and other clock signals. Two or more inverters can be connected between the shift registers to enhance the driving capability.

[0016] Optionally, the multi-way selection module includes one or more stages of transmission gate circuits, the comparison module is a comparator, and the multi-phase clock error detection circuit also includes an amplifier connected to the output of the comparator and a latch connected to the output of the amplifier.

[0017] According to a second aspect of the present disclosure, a multi-phase clock calibration circuit is provided, which includes a multi-phase clock error detection circuit, which includes a first group of DC component extraction modules, a phase difference detection circuit, a second group of DC component extraction modules, a multi-way selection module and a comparison module, wherein the multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or is input to the comparison module via the multi-way selection module and the first group of DC component extraction modules, the multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module and the multi-way selection module or is input to the comparison module via the phase difference detection circuit, the multi-way selection module and the second DC component extraction module, and the comparison module outputs a detection error digital control circuit, which assigns a selection module number to each submodule in the multi-way selection module and corresponds the number to each detection error; a multi-phase clock adjustment circuit, whose input end is a multi-phase clock signal, each group of clock signals with opposite phases is connected to a duty cycle adjustment circuit and a phase adjustment circuit, and the multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

[0018] The multi-phase clock calibration circuit according to the embodiment of the present disclosure is not only applicable to the analog-to-digital conversion module in a high-speed communication receiver, but can also be used in other application scenarios that require precise control of phase errors.

[0019] Optionally, the multi-phase clock signal is input to the comparison module via a first group of DC component extraction modules and a multi-way selection module or is input to the comparison module via a multi-way selection module and a first group of DC component extraction modules, for detecting the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal.

[0020] Optionally, the phase difference detection circuit detects the phase difference between at least two groups of clock signals, and the second DC component extraction module extracts the DC component from the phase difference between the two groups of clock signals.

[0021] Optionally, the phase difference detection circuit includes an XOR logic circuit, which performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 90 degrees, clock signals with phases of 0 degrees and 270 degrees, clock signals with phases of 180 degrees and 270 degrees, and clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals, and the second DC component extraction module extracts the DC component from the signal where the first and third phase difference signals are superimposed, and extracts the DC component from the signal where the second and fourth phase difference signals are superimposed.

[0022] Optionally, the phase adjustment circuit includes at least one group of connected inverters and variable capacitors, each phase adjustment circuit is used to adjust the phase of a clock signal, and when the digital control circuit determines that the phase of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor.

[0023] Optionally, the duty cycle adjustment circuit includes a variable number of connected PMOS and a variable number of connected NMOS, each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal, and when the digital control circuit determines that the duty cycle of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the duty cycle adjustment circuits of the one or more clock signals to adjust the number of connected PMOS or the number of connected NMOS in the corresponding duty cycle adjustment circuit.

[0024] Optionally, the phase difference detection circuit includes an XOR logic circuit, which performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 45 degrees, clock signals with phases of 45 degrees and 90 degrees, clock signals with phases of 180 degrees and 225 degrees, and clock signals with phases of 225 degrees and 270 degrees, to obtain the corresponding fifth to eighth phase difference signals, and the second DC component extraction module extracts the DC component from the signal where the fifth and eighth phase difference signals are superimposed, and extracts the DC component from the signal where the sixth and seventh phase difference signals are superimposed.

[0025] It is not necessary to achieve all the advantages described above at the same time for any device implementing the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be realized and obtained by the structures indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 is a multi-phase clock generation circuit according to an embodiment of the present disclosure;

[0028] Figure 2 is a structural schematic diagram of a clock generation circuit for generating eight phases from four phases according to an embodiment of the present disclosure;

[0029] Figure 3 yes Figure 2 A timing diagram of multiple shift registers in a clock generation circuit;

[0030] Figure 4 is a structural schematic diagram of an eight-phase clock duty cycle adjustment circuit according to an embodiment of the present disclosure;

[0031] Figure 5 yes Figure 4 The eight-phase clock duty cycle adjustment circuit shown is a partial input and output signal timing diagram;

[0032] Figure 6 is a structural schematic diagram of an eight-phase clock error detection circuit according to an embodiment of the present disclosure;

[0033] Figure 7 is a schematic diagram of a portion of the structure of a multi-phase clock adjustment circuit according to an embodiment of the present disclosure;

[0034] Figure 8 yes Figure 7 A circuit example of a partial structure of a clock adjustment circuit in FIG. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not necessarily indicate a quantity restriction. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] Figure 1 The multi-phase clock generation circuit according to the embodiment of the present disclosure is shown in FIG. The circuit includes a multi-phase clock generation circuit 11 , a multi-phase clock duty cycle adjustment circuit 12 , a multi-phase clock adjustment circuit 13 and a multi-phase clock error detection circuit 14 .

[0038] The multi-phase clock generating circuit 11 can be used to generate an initial multi-phase clock signal. For example, a clock signal with half the number of phases can be input to generate a clock signal of a target phase through multiple cascaded registers. The cascade connection of multiple registers can make the output end (Q end) of the previous one between adjacent registers connected to the data end (D end) of the next one. The number of cascaded registers corresponds to the number of phases of the multi-phase clock to be generated. For example, an 8-phase clock signal can be obtained by inputting a 4-phase clock signal, and a 16-phase clock signal can be obtained by inputting an 8-phase clock signal.

[0039] The multi-phase clock duty cycle adjustment circuit 12 can adjust the duty cycle of the clock signals of multiple phases as required, and it can use a delay unit to obtain the required duty cycle. The delay time of the delay unit can be determined according to the required duty cycle. When the output duty cycle of the multi-phase clock generation circuit 11 meets the requirements, the multi-phase clock duty cycle adjustment circuit 12 can be omitted. The multi-phase clock adjustment circuit 13 adjusts the phase and duty cycle of the corresponding clock signal according to the clock signal phase difference and duty cycle comparison result detected by the multi-phase clock error detection circuit 14 to obtain a calibrated multi-phase clock signal. Figure 2-Figure 5 Taking an eight-phase clock generation circuit as an example, the circuit structures of a multi-phase clock generation circuit 11, a multi-phase clock duty cycle adjustment circuit 12, a multi-phase clock adjustment circuit 13 and a multi-phase clock error detection circuit 14 are shown. Figure 2-Figure 5The circuit structure shown is exemplary and is not intended to limit the scope of the present disclosure.

[0040] like Figure 2 As shown, this embodiment of the present disclosure generates an eight-phase clock based on a four-phase clock. The input four-phase clock signals are ick_d0_dp, ick_d0_dn, ick_d90_dp and ick_d90_dn, which respectively represent the clock signal of the 0th phase, the reverse clock signal of the 0th phase (i.e., the 180th degree clock signal), the clock signal of the 90th phase and the reverse clock signal of the 90th phase (i.e., the 270th degree clock signal). When marking the clock signal, a phase greater than or equal to 0 and less than 180 degrees is marked as a P-way phase, and a phase greater than or equal to 180 degrees and less than 360 degrees is marked as an N-way phase.

[0041] The circuit includes eight cascaded shift registers, and the number of shift registers corresponds to the number of phases of the clock signal to be generated. The four-phase clock signal is sequentially input to the first to fourth shift registers and the fifth to eighth shift registers. The data end of the first shift register can input a 2-frequency clock signal of a phase clock signal of the four-phase clock signal. The signal can be obtained by a frequency dividing circuit. The circuit can generate other number of phase clock signals such as a four-phase clock or a sixteen-phase clock by increasing or decreasing the number of registers.

[0042] More specifically, the input clock signal ick_d0_dp is divided (here by two) and input to the first shift register via an inverter. In the eight cascaded shift registers, the output and data terminals between adjacent shift registers are connected via two inverters. Thus, using ick_d0_dp, ick_d90_dn, ick_d0_dn, ick_d90_dp, ick_d0_dp, ick_d90_dn, ick_d0_dn, ick_d90_dp to input to the clock terminals (CLK) of the eight shift registers, an eight-phase clock signal can be generated, namely wck_d0_dn, wck_d135_dn, wck_d90_dp, wck_d45_dn, wck_d0_dp, wck_d135_dp, wck_d90_dn and wck_d45_dp.

[0043] Figure 3 Shows Figure 2The data terminal signals of the first to eighth shift registers and the timing diagram of the output clock signal are shown in FIG. The frequency of the eight-phase clock signal is half of the four-phase clock frequency, and its duty cycle is the same as the four-phase clock frequency. The data terminal signals of the first to eighth shift registers are wck_shift_0, wck_shift_1, wck_shift_2, wck_shift_3, wck_shift_4, wck_shift_5, wck_shift_6, and wck_shift_7, respectively. Although the clock signals input to the first to fourth and fifth to eighth shift registers are the same, since the signals at the data terminal are opposite, the output clock signals are also opposite, thereby forming a complete eight-phase clock signal.

[0044] The eight-phase clock signal generated by the above structure has a simple hardware structure, does not require complex frequency division logic, and has a small generated phase deviation.

[0045] In the above embodiment, the two-stage inverter is an optional part, which can be used to enhance the driving capability, and other electrical components can also be selected to replace the two-stage inverter. The register can also be implemented by various devices, such as latches, triggers, register arrays, etc. The circuits that can implement the above functions of the register are all included in the scope of the register described in the above embodiment.

[0046] Figure 4 The present invention is a schematic diagram of a structure of an eight-phase clock duty cycle adjustment circuit according to an embodiment of the present invention. The duty cycle adjustment circuit does not need to go through a phase interpolator and a delay locked loop, but only needs to use a delay unit and logic operations to achieve duty cycle adjustment.

[0047] For a clock signal, a new clock signal with an adjusted duty cycle can be generated by performing a logic operation on it and another signal with the same frequency. The other signal is a signal selected from the multi-phase clock signal and can be delayed. The delay size and the logic operation are determined according to the desired duty cycle.

[0048] In this embodiment, the logic operation can be a NAND operation. The role of the inverter in this circuit is similar to Figure 1 Similar. According to the duty cycle to be generated, for each signal in the multi-phase clock signal, a clock signal with a fixed phase difference is selected and delayed for a predetermined time. A new multi-phase clock signal with a changed duty cycle can be obtained by performing a non-AND operation on the two signals in each group. The phase difference and delay of the two signals in each group are the same.

[0049] Figure 4For each clock signal, the example in the example selects another clock signal that is 90 degrees out of phase with the clock signal, and outputs the clock signal after the duty cycle is adjusted by performing a NAND operation on each clock signal and another clock signal delayed for a certain time. For example, after wck_d90_dn passes through the delay unit, it performs a NAND operation with wck_d0_dp, passes through two stages of inverters, and outputs ock_d0_dp after the duty cycle is adjusted; after wck_d135_dn passes through the delay unit, it performs a NAND operation with wck_d45_dp, and then passes through two stages of inverters to output ock_d45_dp after the duty cycle is adjusted. The duty cycle of the clock signals of other phases is similarly adjusted. The delay time of delay unit 1 to delay unit 8 is consistent, and the duty cycle of the output eight-phase clock signals is consistent. Figure 5 Shown by Figure 4 Schematic diagram of a timing diagram of a portion of a clock signal generated by a circuit before and after duty cycle adjustment.

[0050] In an example, the duty cycle of the output eight-phase clock signals ock_d0_dp, ock_d45_dp, ock_d90_dp, ock_d135_dp, ock_d0_dn, ock_d45_dn, ock_d90_dn, and ock_d135_dn is not higher than 25% after being inverted, thereby obtaining non-overlapping clock signals.

[0051] In order to meet the requirements of analog-to-digital converter sampling for clock signals, the embodiments of the present disclosure design an eight-phase clock signal with a specific duty cycle. In order to ensure that the data sampled by each phase does not overlap with other phases, the input data will be divided into multiple groups when used, and the clocks in each group do not overlap. Figure 4 The circuit shown can ensure that the four clocks in at least two groups do not overlap if the duty cycle is not greater than 25%. When the duty cycle is adjusted to below 12.5%, eight non-overlapping clocks can be obtained. The circuit can be modified to be applicable to other multi-phase clock signals according to the number of phase clock signals.

[0052] Due to factors such as mismatch between devices and routing parasitics, the generated multi-phase clock will have phase errors, so a circuit is needed to detect and calibrate the phase error.

[0053] Figure 6 An eight-phase clock error detection circuit is shown. Figure 6In the embodiment shown, the detection circuit at least includes a duty cycle detection circuit 601, a phase difference detection circuit 602, a second DC component extraction module 603, a multi-way selection module 604, and a comparison module 605, and may also include an amplification module 606 and a latch module 607. The output of the duty cycle detection circuit 601 and the phase difference detection circuit 602 are connected to a comparison module through the multi-way selection module 604 via the output of the second DC component extraction module 603 to output the comparison result. Optionally, the duty cycle detection circuit 601 and the phase difference detection circuit 602 may also be connected to a separate comparison module via a multi-way selection module to obtain two error signals for the duty cycle and the phase difference. The above-mentioned circuit structures of each part can be adjusted according to the number of phases, so as to be applicable to other multi-phase clocks.

[0054] The duty cycle detection circuit 601 includes a first DC component extraction module for extracting DC components from an eight-phase clock signal, wherein the DC component is extracted from each clock signal. Every two signals with opposite phases in the eight-phase clock signal are divided into a group, and the two DC component extraction modules in each group are connected to a selection module in the multi-way selection module. The selection module is connected or disconnected with a group of DC component extraction modules corresponding to it according to the received control signal, so that only one group of extracted detection results is output to the comparison module 605 in each predetermined time interval. The comparison module 605 compares the DC components of the two signals with opposite phases in each group. The comparison result can be amplified by the amplification module 606 and output to the digital control circuit (not shown) via the latch module 607. The comparison module 605, the amplification module 606, and the latch module 607 can be implemented by a comparator, an amplifier, and a latch, respectively, or other circuit structures can be used to implement the corresponding functions as needed.

[0055] The first and second DC component extraction modules may include one or more DC component extraction modules, and the number of modules is related to the number of clock signals to be processed. The first and second DC component extraction modules may be implemented by a low-pass filter, and the circuit is simple to implement and low in cost. The conversion of duty cycle information into DC information may also be implemented by other circuits. After obtaining the DC components of two clock signals with opposite phases, they are compared to obtain a comparison result of the duty cycle. The first and second DC component extraction modules may be placed before the multi-way selection module or after the multi-way selection module. If each DC component extraction module is placed after the multi-way selection module, the output of each DC component extraction module will be connected to the comparison module.

[0056] exist Figure 6 In the illustrated embodiment, when the multi-path selection module is placed before each DC component extraction module, a group of signals from which DC components are to be extracted are first selected, and then the DC components are extracted through the corresponding DC component extraction modules.

[0057] exist Figure 6 In the embodiment, each selection module in the multi-way selection module can be turned on and off according to the control signal of the digital control circuit, and when turned off, it prevents the upstream circuit connected to it from affecting the subsequent comparison module. For each detection and comparison period, only one corresponding selection module is turned on, so that the comparison module compares a group of measurement signals and outputs the comparison result. The digital control circuit can number each selection module to determine which group of detection results the error signal err outputs. The selection module can include one or more transmission gate circuits.

[0058] For example, the duty cycle information of ock_d0_dp and ock_d0_dn is converted into a DC signal through the DC component extraction module and output to the comparison module 605 through the selection module. If the duty cycle of ock_d0_dp is slightly greater than the duty cycle of ock_d0_dn, the comparison module, the amplification module and the latch module can output "1" to correspond to the above situation, and the result is output to the digital control circuit to feedback adjust ock_d0_dp and / or ock_d0_dn so that the duty cycles of the two are the same. This adjustment method will refer to Figure 7 Provide explanation.

[0059] The phase difference detection circuit 602 divides the eight-phase clock signal into multiple groups to detect phase errors. From the results of each group of phase errors, the clock signal with a phase lag can be found. Figure 7 Specifically, Figure 6 The first group of signals includes ock_d0_dp, ock_d90_dp, ock_d0_dn, ock_d90_dn, and the corresponding phases are 0 degree, 90 degree, 180 degree and 270 degree phase signals. The signals corresponding to the four groups of phase differences of ock_d0_dp and ock_d90_dp, ock_d0_dn and ock_d90_dn, ock_d0_dn and ock_d90_dp, ock_d0_dp and ock_d90_dn are generated by an XOR logic circuit. In this example, if the result of superimposing ock_d0_dp and ock_d90_dp with ock_d0_dn and ock_d90_dn through the XOR logic circuit is compared with the result of superimposing ock_d0_dn with ock_d90_dp with ock_d0_dp and ock_d90_dn through the XOR logic circuit, the former is greater than the latter after passing through the second DC component extraction module, which can indicate that ock_d90_dp and ock_d90_dn are lagging in phase. After passing through the multi-channel selection module and the comparison module, the detected DC error information will be fed back to the multi-channel clock adjustment circuit for calibration.

[0060] The second group of signals includes ock_d0_dp, ock_d45_dp, ock_d90_dp, ock_d0_dn, ock_d45_dn, ock_d90_dn, which detect the phase error between ock_d0_dp, ock_d45_dp, ock_d90_dp and the phase error between ock_d0_dn, ock_d45_dn, ock_d90_dn. Similarly, by comparing the extracted DC components, the clock signal with a phase lag is found and adjusted. Specifically, the phase differences between ock_d0_dp and ock_d45_dp, ock_d45_dp and ock_d90_dp, ock_d0_dn and ock_d45_dn, and ock_d45_dn and ock_d90_dn are obtained through the XOR logic circuit, and after superposition, they enter the second DC component extraction module and by comparing the two groups of signals, the information on whether the phases of ock_d45_dp and ock_d45_dn are lagging or leading can be obtained, thereby determining how to adjust them.

[0061] Similar to the second group of signals, the third group of signals (not shown) may include ock_d0_dp, ock_d90_dp, ock_d135_dp, ock_d0_dn, ock_d90_dn, ock_d135_dn, which detect phase differences between ock_d90_dn, ock_d135_dn, ock_d0_dp and between ock_d90_dp, ock_d135_dp, ock_d0_dn. Specifically, the phase differences between ock_d90_dp and ock_d135_dp, ock_d135_dp and ock_d0_dn, ock_d90_dn and ock_d135_dn, and ock_d135_dn and ock_d0_dp are obtained through the XOR logic circuit to determine whether the phases of ock_d135_dp and ock_d135_dn are lagging or leading, thereby determining how to adjust them.

[0062] The above example is a phase error detection method for an eight-phase clock signal. For a four-phase clock signal, the circuit for detecting the first group of signals can be used to implement the phase error measurement of the four-phase clock signal. For a sixteen-phase clock signal, four groups of signals can be added similarly on the basis of the above circuit to implement the phase error measurement of the remaining eight phase clock signals.

[0063] The above circuit realizes a high-gain multiple conversion from phase error to DC error, and can accurately detect phase errors at the tens-femtosecond level.

[0064] Figure 7A partial structural schematic diagram of a multi-phase clock adjustment circuit according to an embodiment of the present disclosure is shown. The circuit includes a decoding control circuit 701, a phase adjustment circuit 702 and a duty cycle adjustment circuit 703. Figure 7 Only the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 for a group of clock signals with opposite phases are shown. The multi-phase clock adjustment circuit includes a phase adjustment circuit and a duty cycle adjustment circuit for each group of clock signals with opposite phases, and the structure for the remaining phases is consistent with the structure shown in the figure, so the remaining parts are omitted here. Figure 7 In the embodiment, clock signals with opposite phases are input to respective phase adjustment circuits and duty cycle adjustment circuits, and they can be adjusted independently, so the circuit can be used as an independent phase adjustment circuit and duty cycle adjustment circuit for each clock signal. The decoding control circuit can be a part of the digital control circuit, which receives the error signal err and the number of the selection module corresponding to the error signal. The decoding control circuit 701 determines whether the error signal err is a duty cycle error or a phase error according to the received number, and determines the clock signal corresponding to the error signal that needs to be adjusted. Figure 7 Only the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 for ock_d0_dp and ock_d0_dn are shown. Both the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 may include sub-circuits for adjusting ock_d0_dp and ock_d0_dn respectively, for example, the phase or duty cycle of ock_d0_dp may be adjusted separately. The decoding control circuit 701 may send control signals to the sub-circuits respectively. For each group of clock signals with opposite phases, a phase adjustment circuit and a duty cycle adjustment circuit are provided, which receive the signal sent by the decoding control circuit 701. Since the circuit structures are the same, only ock_d0_dp and ock_d0_dn are used as examples for explanation.

[0065] For example, if the error signal err is determined to be a phase error based on the number of the received selection module, and it is determined that the error signal indicates that ock_d90_dp and ock_d90_dn lag behind ock_d0_dp and ock_d0_dn, a phase adjustment circuit is used to adjust the phase of ock_d0_dp and ock_d0_dn and / or ock_d90_dp and ock_d90_dn, that is, to adjust the phase of ock_d0_dp and ock_d0_dn backward and / or adjust the phase of ock_d90_dp and ock_d90_dn forward.

[0066] The circuit example of the phase adjustment circuit 702 can be found in Figure 8. The circuit may include one or more stages of inverters and their adjustable load capacitors, and the phase of the corresponding clock signal may be adjusted by adjusting the capacitance value of the load capacitor. Specifically, the clock signal of each phase is connected to one end of the adjustable capacitor through an inverter, and the other end of the adjustable capacitor is grounded. Each clock signal may be input into a circuit of a one-stage inverter and its adjustable load capacitor, or may be input into a circuit of a multi-stage inverter and its adjustable load capacitor, so that the adjustment accuracy is higher, and a specific implementation method may be selected according to the phase variation range caused by PVT, so that the adjustment range may cover the phase variation range. The adjustment of the capacitance value may be achieved by adjusting the load capacitance value or the number of load capacitors. The adjustable load capacitance may be adjusted according to the control signal output by the decoding control circuit. As in the example described above, if it is detected that ock_d90_dp and ock_d90_dn lag behind ock_d0_dp and ock_d0_dn, you can choose to reduce the load capacitance of both ock_d90_dp and ock_d90_dn and increase the load capacitance of ock_d0_dp and ock_d0_dn, or only increase the load capacitance of ock_d0_dp and ock_d0_dn, or only reduce the load capacitance of ock_d90_dp and ock_d90_dn.

[0067] The duty cycle adjustment circuit 703 may be composed of a plurality of parallel PMOS and a plurality of parallel CMOS. The duration of the high level or low level may be changed by adjusting the number of parallel PMOS or parallel NMOS, thereby adjusting the duty cycle. For example, PMOS and NMOS may form a multi-stage inverter circuit for the duty cycle adjustment circuit 703.

[0068] For example, if it is determined according to the number of the selection module that the error signal corresponds to the duty cycle error between ock_d0_dp and ock_d0_dn, the duty cycle adjustment circuit 703 can be used to adjust ock_d0_dp and / or ock_d0_dn according to the meaning represented by the error value (for example, "1" means that the duty cycle of ock_d0_dp is greater than the duty cycle of ock_d0_dn). By adjusting the number of PMOS and NMOS, the phase error and / or duty cycle error between the same group of clocks P and N can be calibrated. The duty cycle adjustment circuit can also be implemented in other circuit forms, not limited to the above-mentioned method of adjusting the number of PMOS and NMOS.

[0069] The output signals of the clock adjustment circuit, such as ock_d0p, ock_d0n, etc., will be returned to the Figure 6 The input end of the eight-phase clock error detection circuit shown is used to achieve a high-precision clock signal.

[0070] Figure 6 and Figure 7The circuit shown can be used as a clock calibration circuit to adjust the phase and duty cycle errors that occur in a multi-phase clock generator.

[0071] Compared with the technical solution of using a delay phase-locked loop, the embodiment of the present disclosure can effectively reduce the calibration process of the chip, simplify the chip design, and reduce costs. In addition, the embodiment of the present disclosure only uses a simple logic circuit to achieve the generation of multi-phase clocks, as well as the detection and calibration of phase errors between each other. The calibration circuit can automatically calibrate to the optimal phase according to the changes in PVT (Process, Voltage, Temperature), thereby improving the reliability of the chip under different working conditions and reducing the cost of chip mass production testing.

[0072] The clock calibration circuit proposed in the present disclosure is not limited to the use scenario of time-interleaved analog-to-digital converters, but can also be extended to other scenarios that use multi-phase clocks and require precise control of phase errors, such as the digital-to-analog conversion output driver at the transmitter end of a high-speed serial interface circuit.

[0073] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-phase clock generating circuit, characterized in that include: A multi-phase clock generation circuit that generates a multi-phase clock signal through a plurality of serially connected registers; A multi-phase clock error detection circuit, comprising a first group of DC component extraction modules, a phase difference detection circuit, a second group of DC component extraction modules, a multi-way selection module and a comparison module, wherein a multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or via the multi-way selection module and the first group of DC component extraction modules, the multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module and the multi-way selection module or via the phase difference detection circuit, the multi-way selection module and the second DC component extraction module, and the comparison module outputs a detection error; A digital control circuit that assigns a selection module number to each submodule in the multi-way selection module and corresponds the number to each detection error; A multi-phase clock adjustment circuit comprises a duty cycle adjustment circuit and a phase adjustment circuit. The multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of a digital control circuit.

2. The multi-phase clock generating circuit as claimed in claim 1, characterized in that The multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or is input to the comparison module via the multi-way selection module and the first group of DC component extraction modules, and is used to detect the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal.

3. The multi-phase clock generating circuit as claimed in claim 1, characterized in that the phase difference The detection circuit detects the phase difference between at least two groups of clock signals, the second DC component extraction module extracts the DC component from the phase difference between the two groups of clock signals, and the multi-phase clock generation circuit does not include a phase-locked loop.

4. The multi-phase clock generating circuit as claimed in claim 3, characterized in that the phase difference The detection circuit includes an XOR logic circuit. The phase difference detection circuit performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 90 degrees, clock signals with phases of 0 degrees and 270 degrees, clock signals with phases of 180 degrees and 270 degrees, and clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component from the signal where the first and third phase difference signals are superimposed, and extracts the DC component from the signal where the second and fourth phase difference signals are superimposed.

5. The multi-phase clock generating circuit as claimed in claim 1, characterized in that It also includes a multi-phase clock duty cycle adjustment circuit, which includes a logic circuit and a delay circuit, which receives the output of the multi-phase clock generating circuit, and uses the logic circuit to perform logic operations on each clock signal and another clock signal in the multi-phase clock signal delayed by the delay circuit as a group of signals to obtain a multi-phase clock signal with a predetermined duty cycle, wherein the delay size of the delay circuit is determined according to the predetermined duty cycle.

6. The multi-phase clock generating circuit as claimed in claim 1, characterized in that The phase adjustment circuit includes at least one group of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that the phase of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor.

7. The multi-phase clock generating circuit as claimed in claim 1, characterized in that The duty cycle adjustment circuit includes a PMOS with a variable number of connections and a NMOS with a variable number of connections. Each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal. When the digital control circuit determines that the duty cycle of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the duty cycle adjustment circuits of the one or more clock signals to adjust the number of connected PMOS or the number of connected NMOS in the corresponding duty cycle adjustment circuit.

8. The multi-phase clock generating circuit as claimed in claim 1, characterized in that The multi-phase clock generating circuit includes 8 cascaded shift registers, and inputs the four-phase clock signal to the clock ends of the first to fourth shift registers and the fifth to eighth shift registers respectively to obtain an eight-phase clock signal.

9. The multi-phase clock generating circuit as claimed in claim 1, characterized in that The multiplexer module includes one or more transmission gates, the comparison module is a comparator, and the multi-phase clock error detection circuit also includes an amplifier connected to the output of the comparator and a latch connected to the output of the amplifier.

10. A multi-phase clock calibration circuit, characterized in that include A multi-phase clock error detection circuit, comprising a first group of DC component extraction modules, a phase difference detection circuit, a second group of DC component extraction modules, a multi-way selection module and a comparison module, wherein a multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or via the multi-way selection module and the first group of DC component extraction modules, the multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module and the multi-way selection module or via the phase difference detection circuit, the multi-way selection module and the second DC component extraction module, and the comparison module outputs a detection error; A digital control circuit that assigns a selection module number to each submodule in the multi-way selection module and corresponds the number to each detection error; A multi-phase clock adjustment circuit has a multi-phase clock signal as its input, each group of clock signals with opposite phases is connected to a duty cycle adjustment circuit and a phase adjustment circuit, and the multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

11. The multi-phase clock calibration circuit according to claim 10, characterized in that The multi-phase clock signal is input to the comparison module via the first group of DC component extraction modules and the multi-way selection module or is input to the comparison module via the multi-way selection module and the first group of DC component extraction modules, and is used to detect the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal.

12. The multi-phase clock calibration circuit as claimed in claim 10, characterized in that the phase difference The detection circuit detects the phase difference between at least two groups of clock signals, the second DC component extraction module extracts the DC component from the phase difference between the two groups of clock signals, and the multi-phase clock calibration circuit does not include a phase-locked loop.

13. The multi-phase clock calibration circuit as claimed in claim 12, characterized in that the phase difference The detection circuit includes an XOR logic circuit. The phase difference detection circuit performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 90 degrees, clock signals with phases of 0 degrees and 270 degrees, clock signals with phases of 180 degrees and 270 degrees, and clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component from the signal where the first and third phase difference signals are superimposed, and extracts the DC component from the signal where the second and fourth phase difference signals are superimposed.

14. The multi-phase clock calibration circuit according to claim 10, characterized in that The phase adjustment circuit includes at least one group of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that the phase of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor.

15. The multi-phase clock calibration circuit of claim 10, wherein The duty cycle adjustment circuit includes a PMOS with a variable number of connections and a NMOS with a variable number of connections. Each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal. When the digital control circuit determines that the duty cycle of one or more clock signals needs to be adjusted based on the selection module number and the detection error, a control signal is sent to the duty cycle adjustment circuits of the one or more clock signals to adjust the number of connected PMOS or the number of connected NMOS in the corresponding duty cycle adjustment circuit.

16. The multi-phase clock calibration circuit as claimed in claim 13, characterized in that the phase difference The detection circuit includes an XOR logic circuit. The phase difference detection circuit performs an XOR operation on the following four groups of clock signals: clock signals with phases of 0 degrees and 45 degrees, clock signals with phases of 45 degrees and 90 degrees, clock signals with phases of 180 degrees and 225 degrees, and clock signals with phases of 225 degrees and 270 degrees, to obtain corresponding fifth to eighth phase difference signals. The second DC component extraction module extracts the DC component from the signal on which the fifth and eighth phase difference signals are superimposed, and extracts the DC component from the signal on which the sixth and seventh phase difference signals are superimposed.

Images