High-speed CML type multiplexer circuit

Abstract

The invention discloses a high-speed CML type multiplexer circuit, and belongs to the technical field of microelectronics. The circuit comprises a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 are connected with a power supply voltage VDD, and a negative electrode of the resistor R1 is connected with drain electrodes of an NM1 and an NM5; the grid electrode of the NM1 is connected with the positive end of an input differential pair signal 1, and the grid electrode of the NM5 is connected with the positive end of an input differential pair signal 2; the negative end of the R2 is connected with the drain electrodes of the NM2 and the NM6; the grid electrode of the NM2 is connected with the negative end of an input differential pair signal 1, and the grid electrode of the NM6 is connected with the negative end of an input differential pair signal 2; according to the invention, part or all of the tail current tubes are multiplexed as control switches of the multiplexer, so that the chip area of the circuit is further reduced, and crosstalk of a turn-off path to a turn-on path is reduced.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and more particularly to a high-speed CML type multiplexer circuit. Background Art

[0002] like Figure 1 As shown, in the conventional NMOS tube type CML two-way selector, NM3 and NM4 are the output control switches of the first way. When SEL1 is "high", NM3 and NM4 are turned on, thereby selecting and outputting the signals of IN_P1 and IN_N1; similarly, NM7 and NM8 are the output control switches of the second way. When SEL2 is "high", NM7 and NM8 are turned on, thereby outputting the signals of IN_P2 and IN_N2. Figure 2 It is a PMOS tube type CML two-way selector. PM3 and PM4 are the output switches of the first way. When SEL1B is "low", PM3 and PM4 are turned on and the differential signal of IN_P1 and IN_N1 is output; similarly, when SEL2B is "low", PM7 and PM8 are turned on and IN_P2 and IN_N2 are output.

[0003] Since the control switch is on the signal path from input to output of the CML two-way selector, the on-resistance of the switch will seriously affect the speed of the signal from input to output; when the input signal frequency is very high, the amplitude of the output signal will become very small and cannot meet the needs of actual engineering.

[0004] In order to solve the bandwidth reduction of CML multiplexers at high frequencies due to the above defects, in some applications, these switch control tubes need to be removed, but the differential signal of the one or more channels that are not selected for conduction should be controlled to be "low" at the same time ( Figure 1 corresponding NMOS tube type) or "high" ( Figure 2 Corresponding PMOS tube type). In order to control the input signal, additional CML logic is added, which increases power consumption and chip area overhead. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention aims to provide a high-speed CML multiplexer circuit to solve the following technical problems: improve the working bandwidth of the CML multiplexer and overcome the influence of the switch tube on the transmission path.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A high-speed CML type multiplexer circuit includes resistors R1 and R2, the resistors R1 and R2 are connected to a power supply voltage VDD, the negative electrode of R1 is connected to the drain electrodes of NM1 and NM5; the gate of NM1 is connected to the positive end of the input differential pair signal 1, and the gate of NM5 is connected to the positive end of the input differential pair signal 2; the negative end of R2 is connected to the drain electrodes of NM2 and NM6; the gate of NM2 is connected to the negative end of the input differential pair signal 1, and the gate of NM6 is connected to the negative end of the input differential pair signal 2;

[0008] The source and drain of NM10 are connected to the drains of NM3 and NM4 respectively; the source and drain of NM11 are connected to the drains of NM7 and NM8 respectively, the sources of NM3 and NM4 are connected to NM0, the sources of NM7 and NM8 are connected to NM9, the gates of NM0 and NM9 are connected to the bias voltage NBIAS together, the gates of NM3, NM4 and NM10 are connected to the control signal SEL1, and the gates of NM7, NM8 and NM11 are connected to the control signal SEL2.

[0009] Furthermore, when path 1 is turned on, SEL1 is "high", and NM10 connects the source terminals of NM1 and NM2, so that the switch impedance of NM3 and NM4 becomes a common mode impedance, which has no effect on the differential signal; at this time, path 2 is disconnected, SEL2 is "low", switch NM11 is disconnected, and NM7 and NM8 are disconnected; since the differential pair NM5 and NM6 do not conduct current, IN_P2 and IN_N2 cannot pass the signal to the output;

[0010] When path 2 is selected, SEL2 is "high", NM11, NM7 and NM8 are turned on; while SEL1 is "low", NM10, NM3 and NM4 are turned off.

[0011] Further, path 1 is a path when differential pair signal 1 is transmitted to the output through NM1 and NM2, and path 2 is a path when differential pair signal 2 is transmitted to the output through NM5 and NM6.

[0012] Furthermore, the sources of NM1 and NM2 are connected to the drains of NM3 and NM4 respectively, and the sources of NM5 and NM6 are connected to the drains of NM7 and NM8 respectively.

[0013] Furthermore, the NM0 tail current tube with a channel width and length of W and L is replaced by NM2 and NM3 with channel widths and lengths of 0.5W and 0.5L respectively. NM2 and NM3 are connected in parallel and in series with NM1 with a channel width and length of W and 0.5L.

[0014] Furthermore, the NM0 tail current tube with a channel width and length of W and L is replaced by two NM2 and NM3 with channel widths and lengths of 0.5W and L respectively, and NM2 and NM3 are connected in parallel.

[0015] Compared with the existing solutions, the present invention has the following beneficial effects:

[0016] The present invention overcomes the disadvantage of limited bandwidth of traditional CML multiplexers, and effectively improves the speed and bandwidth of the circuit without increasing hardware overhead and circuit power consumption; by reusing part or all of the tail current tubes as control switches of the multiplexer, the chip area of ​​the circuit is further reduced, and the crosstalk of the off path to the on path is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the structure diagram of the traditional NMOS CML type two-way selector.

[0018] Figure 2 It is a traditional PMOS CML type two-way selector structure.

[0019] Figure 3 It is a high-speed CML type multiplexer circuit in the present invention.

[0020] Figure 4 It is the evolution diagram of the NMOS tail current tube in the present invention.

[0021] Figure 5 Another evolution diagram of the NMOS tail current tube in the present invention.

[0022] Figure 6 This is an NMOS CML multiplexer structure in the present invention that utilizes part of the multiplexed tail current tube as a switch.

[0023] Figure 7 This is an NMOS CML multiplexer structure in the present invention that utilizes all tail current tubes as switches.

[0024] Figure 8 This is the improved NMOS tube CML type m-way selector structure in the present invention.

[0025] Fig. 9 This is the improved PMOS tube CML type m-way selector structure in the present invention.

[0026] Fig.10 The invention provides an improved NMOS tube CML type m-way selector structure for multiplexing part of the tail current tube.

[0027] Fig.11 The invention provides a PMOS tube CML type m-way selector structure for improving the multiplexing of part of the tail current tube.

[0028] Fig.12 The invention provides an improved NMOS tube CML type m-way selector structure for multiplexing all tail current tubes.

[0029] Fig.13 The invention provides a PMOS tube CML type m-way selector structure for multiplexing all tail current tubes. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for the purpose of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

[0031] Example 1

[0032] Reference Figure 3 As shown, the present invention is a high-speed CML type multiplexer circuit, including resistors R1 and R2, the positive electrodes of the resistors R1 and R2 are connected to the power supply voltage VDD, the negative electrode of R1 is connected to the drains of NMOS tubes NM1 and NM5; the gate of NM1 is connected to the positive end of the input differential pair signal 1, namely IN_P1, and the gate of NM5 is connected to the positive end of the input differential pair signal 2, namely IN_P2; the negative end of R2 is connected to the drains of NMOS tubes NM2 and NM6; the gate of NM2 is connected to the negative end of the input differential pair signal 1, namely IN_N1, and the gate of NM6 is connected to the negative end of the input differential pair signal 2, namely IN_N2.

[0033] It should be further explained that the source of NM1 is connected to the drain of NMOS tube NM3, the source of NM2 is connected to the drain of NMOS tube NM4, the source of NM5 is connected to the drain of NMOS tube NM7, and the source of NM6 is connected to the drain of NMOS tube NM8; the source of NM10 is connected to the drain of NM3, and the drain of NM10 is connected to the drain of NM4; the source of NM11 is connected to the drain of NM7, and the drain of NM11 is connected to the drain of NM8; the sources of NM3 and NM4 are connected to the drain of tail current NMOS tube NM0, and the sources of NM7 and NM8 are connected to the drain of tail current NMOS tube NM9; the sources of NM0 and NM9 are grounded, and the gates are connected to the bias voltage NBIAS; the gates of NM3, NM4 and NM10 are connected to the control signal SEL1, The gates of NM7, NM8 and NM11 are connected to the control signal SEL2.

[0034] When path 1 is turned on, the differential pair signal 1 (IN_P1 and IN_N1) is transmitted to the output through NM1 and NM2, and the path is path 1. SEL1 is "high", and NM10 connects the source terminals of NM1 and NM2, so that the switch impedance of NM3 and NM4 becomes a common mode impedance, which has no effect on the differential signal. At this time, path 2 is disconnected, and the differential pair signal 2 (IN_P2 and IN_N2) is transmitted to the output through NM5 and NM6. The path is path 2, SEL2 is "low", switch NM11 is disconnected, and NM7 and NM8 are disconnected. Since the differential pair NM5 and NM6 do not conduct current, IN_P2 and IN_N2 cannot pass the signal to the output. Similarly, when path 2 is selected, SEL2 is "high", NM11, NM7 and NM8 are turned on; and SEL1 is "low", NM10, NM3 and NM4 are turned off.

[0035] It should be further explained that in order to minimize the impact of the signal of the disconnected path on the selector output, the impedance of the device when NM3 and NM4 or NM7 and NM8 are disconnected should be maximized, and all control switch tubes should avoid being designed according to the minimum channel length or a larger device size; if designed according to the minimum channel length, the disconnected impedance cannot be maximized; if designed according to a larger device size, it will occupy too much chip area.

[0036] Example 2

[0037] Reference Figure 4 As shown, based on Example 1, Figure 3 The tail current tube of the NMOS tube in the circuit and layout are improved. Because in order to ensure the matching of the tail current, the channel length of the tail current tube is usually designed according to a larger value. The tail current tube of an NMOS tube NM0 with a channel width and length of W and L can be transformed into two NMOS tubes NM2 and NM3 with channel widths and lengths of 0.5W and 0.5L in parallel in circuit connection, and then connected in series with the NMOS tube NM1 with a channel width and length of W and 0.5L. Without increasing the chip area, the NM2 and NM3 used as control switches can be decomposed by changing the connection of the tail current tube.

[0038] Example 3

[0039] Reference Figure 5 As shown, based on Example 1, Figure 3 The NMOS tail current source is further improved to become NMOS tubes NM2 and NM3 with channel width and length of 0.5W and L in parallel, which can further improve the impedance after the control switch is turned off and strengthen the isolation of the selection signal.

[0040] Example 4

[0041] Reference Figure 6 As shown, based on Example 2, a NMOS CML multiplexer structure is proposed that utilizes part of the multiplexed tail current tube as a switch;

[0042] NM12 and PM1 as well as NM15 and PM2 form a CMOS switch respectively, and NM13 and NM14 are grounded switches. When the power supply voltage VDD is relatively high, PM1 and PM2 can be omitted, and a single NMOS can be directly used as a switch.

[0043] When path 1 is selected, SEL1 is "high" and SEL1B is "low". NM10 is closed, NM13 is open, and the CMOS switch composed of NM12 and PM1 is turned on, connecting the gate voltage of NM3 and NM4 to NBIAS. At this time, NM3, NM4 and NM0 form a tail current tube; path 2 is disconnected, SEL2 is "low", and SEL2B is "high". NM11 is disconnected, NM14 is closed, and the CMOS switch composed of NM15 and PM2 is disconnected, connecting the gate voltage of NM7 and NM8 to ground. Since NM11, NM7 and NM8 are all in the cut-off region, the differential pair tubes NM5 and NM6 have no tail current, and the connection between path 2 and the output is disconnected.

[0044] Similarly, when path 2 is selected, SEL2 is "high", SEL2B is "low", NM11 is turned on, NM14 is turned off, and the gate voltages of NM7 and NM8 are connected to the bias voltage NBIAS. At this time, NM7, NM8 and NM9 form a tail current tube; path 1 is disconnected, SEL1 is "low", SEL1B is "high", and the gate voltages of NM3 and NM4 are connected to ground. Since the differential pair tubes NM1 and NM2 have no tail current, path 1 is disconnected from the output.

[0045] Example 5

[0046] Reference Figure 7 As shown, based on Example 3, a NMOS CML multiplexer structure is proposed that utilizes all tail current tubes as switches;

[0047] The new NMOS CML selector can remove the tail current tubes NM0 and NM9 and transform into Figure 7 The structure, working principle of the structure and embodiment 4 Figure 6 same;

[0048] Compared with Example 4, although NM10, NM11, NM12, NM13, NM14, NM15 and PM1, PM2 control switches are added, except for NM10 and NM11 which need to conduct a maximum of half of the tail current, the other switches have no static current when working, so the size of the device can be made relatively small. Since the tail current tube is reused as the control switch of the CML two-way selector, there is no need to increase the additional hardware cost, which has an area advantage compared to the traditional CML two-way selector.

[0049] Example 6

[0050] In Example 1 Figure 3 On the basis of Figure 8 and Fig. 9 They are respectively an improved NMOS tube CML type m-way selector structure and an improved PMOS tube CML type m-way selector structure, where m is an integer greater than 1; Figure 8 is based on Figure 3 A circuit embodiment in which the two-way selector is expanded to an m-way selector; Fig. 9 Yes Figure 8 Another variation of the circuit embodiment of converting an NMOS tube into a PMOS tube.

[0051] Example 7

[0052] In Example 4 Figure 6 On the basis of Fig.10 and Fig.11 They are respectively an NMOS tube CML type m-way selector structure of an improved multiplexing part tail current tube and a PMOS tube CML type m-way selector structure of an improved multiplexing part tail current tube, where m is an integer greater than 1; Fig.10 is based on Figure 6 A circuit embodiment in which the two-way selector is expanded to an m-way selector; Fig.11 Yes Fig.10 Another variation of the circuit embodiment of converting an NMOS tube into a PMOS tube.

[0053] Example 8

[0054] In Example 5 Figure 7 On the basis of Fig.12 and Fig.13 They are respectively an improved NMOS tube CML type m-way selector structure for multiplexing all tail current tubes and an improved PMOS tube CML type m-way selector structure for multiplexing all tail current tubes, where m is an integer greater than 1;

[0055] Fig.12 is based on Figure 7 A circuit embodiment in which the two-way selector is expanded to an m-way selector; Fig.13 Yes Fig.12Another variation of the circuit embodiment of converting an NMOS tube into a PMOS tube.

[0056] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A high-speed CML type multiplexer circuit, characterized in that: It includes resistors R1 and R2, the resistors R1 and R2 are connected to the power supply voltage VDD, the negative electrode of R1 is connected to the drains of NM1 and NM5; the gate of NM1 is connected to the positive end of the input differential pair signal 1, and the gate of NM5 is connected to the positive end of the input differential pair signal 2; the negative end of R2 is connected to the drains of NM2 and NM6; the gate of NM2 is connected to the negative end of the input differential pair signal 1, and the gate of NM6 is connected to the negative end of the input differential pair signal 2; The source and drain of NM10 are connected to the drains of NM3 and NM4 respectively; the source and drain of NM11 are connected to the drains of NM7 and NM8 respectively, the sources of NM3 and NM4 are connected to NM0, the sources of NM7 and NM8 are connected to NM9, the gates of NM0 and NM9 are connected to the bias voltage NBIAS together, the gates of NM3, NM4 and NM10 are connected to the control signal SEL1, and the gates of NM7, NM8 and NM11 are connected to the control signal SEL2.

2. A high-speed CML type multiplexer circuit according to claim 1, characterized in that: When path 1 is turned on, SEL1 is "high", NM10 connects the source terminals of NM1 and NM2, so that the switch impedance of NM3 and NM4 becomes a common mode impedance, which has no effect on the differential signal; at this time, path 2 is disconnected, SEL2 is "low", switch NM11 is disconnected, and NM7 and NM8 are disconnected; since the differential pair NM5 and NM6 have no conduction current, IN_P2 and IN_N2 cannot pass the signal to the output; When channel 2 is selected, SEL2 is "high", NM11, NM7 and NM8 are turned on; while SEL1 is "low", NM10, NM3 and NM4 are turned off.

3. A high-speed CML type multiplexer circuit according to claim 2, characterized in that: Path 1 is a path when differential pair signal 1 is transmitted to output through NM1 and NM2, and path 2 is a path when differential pair signal 2 is transmitted to output through NM5 and NM6.

4. A high-speed CML type multiplexer circuit according to claim 1, characterized in that: The sources of NM1 and NM2 are connected to the drains of NM3 and NM4 respectively, and the sources of NM5 and NM6 are connected to the drains of NM7 and NM8 respectively.

5. A high-speed CML multiplexer circuit according to claim 1, characterized in that: The NM0 tail current tube with a channel width and length of W and L is replaced by NM2 and NM3 with channel widths and lengths of 0.5W and 0.5L respectively. NM2 and NM3 are connected in parallel and in series with NM1 with a channel width and length of W and 0.5L.

6. A high-speed CML type multiplexer circuit according to claim 1, characterized in that: The NM0 tail current tube with a channel width and length of W and L is replaced by two NM2 and NM3 with channel width and length of 0.5W and L respectively, and NM2 and NM3 are connected in parallel.

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