Signal generation device and molecular clock

Abstract

The invention provides a signal generation device and a molecular clock, and the signal generation device can comprise a sub-sampling phase-locked loop and a sub-sampling frequency multiplier connected with the sub-sampling phase-locked loop. The sub-sampling frequency multiplier comprises a first voltage-controlled oscillator, a first sub-sampling phase discriminator, a transconductance amplifier and a logic processing unit; the output end of the first voltage-controlled oscillator and the output end of the sub-sampling phase-locked loop are connected with the first sub-sampling phase discriminator. The output end of the first sub-sampling phase discriminator is connected with the transconductance amplifier; the logic processing unit is used for outputting a control signal to the transconductance amplifier so as to control the output of the transconductance amplifier; when the sub-sampling phase-locked loop is in a locked state, the reference voltage of the transconductance amplifier is adjusted, so that the control voltage of the first voltage-controlled oscillator is adjusted.

Description

Technical Field

[0001] The present application relates to the field of clock technology, and in particular to a signal generating device and a molecular clock. Background Art

[0002] A high-precision clock is a device that can provide accurate and stable time measurement. It is widely used in scientific research, navigation systems such as the Global Positioning System (GPS), communication systems, financial transactions, scientific experiments and other fields that require high time accuracy.

[0003] At present, high-precision clocks mainly include atomic clocks and molecular clocks. Atomic clocks use the interaction between electromagnetic radiation and the excited state of specific atoms to achieve time measurement, and use the absorption peak generated by laser penetrating the glass gas chamber as a frequency reference. Molecular clocks use the electromagnetic wave molecular rotation spectrum generated by the quantized rotation energy level transition of polar gas molecules under the action of electromagnetic fields to achieve time measurement. Molecular clocks use the rotation spectrum peak of polar gas that penetrates the gas chamber with high-frequency electromagnetic waves as a frequency reference.

[0004] The existing clock signal generation source usually relies on an oscillator, but the existing oscillator design either has high power consumption or too low output power. Summary of the invention

[0005] The purpose of the present application is to provide a signal generating device and a molecular clock, which can enable the signal generating device to generate greater output power.

[0006] In a first aspect, the present invention provides a signal generating device, comprising: a sub-sampling phase-locked loop and a sub-sampling frequency multiplier connected to the sub-sampling phase-locked loop; the sub-sampling frequency multiplier comprises a first voltage-controlled oscillator, a first sub-sampling phase detector, a transconductance amplifier and a logic processing unit; wherein the output ends of the first voltage-controlled oscillator and the sub-sampling phase-locked loop are both connected to the first sub-sampling phase detector; the output end of the first sub-sampling phase detector is connected to the transconductance amplifier; the logic processing unit is used to output a control signal to the transconductance amplifier to control the output of the transconductance amplifier; wherein, when the sub-sampling phase-locked loop is in a locked state, the control voltage of the first voltage-controlled oscillator is adjusted by adjusting the reference voltage of the transconductance amplifier.

[0007] In the above implementation, the frequency and phase difference between the output signal and the reference signal can be maintained within the allowable range through the locking effect of the sub-sampling phase-locked loop. When the sub-sampling phase-locked loop is in a locked state, the output signal of the entire signal generating device further improves the overall performance. Further, through the use of the sub-sampling frequency multiplier, based on the processing of the sampling frequency and the output frequency of the first voltage-controlled oscillator by the sub-sampling frequency multiplier, it can realize spread spectrum processing to output the required frequency.

[0008] In an optional embodiment, the sub-sampling frequency multiplier also includes: a lock detection unit connected to the output of the transconductance amplifier, and the output of the lock detection unit is connected to the logic processing unit; the detection unit is used to perform frequency lock detection based on the output signal received from the transconductance amplifier to detect whether the sub-sampling phase-locked loop enters a locked state.

[0009] In an optional embodiment, the lock detection unit includes: a first comparator and a second comparator; the three-phase inputs of the first comparator are respectively a high level, a clock input and the output of the transconductance amplifier; the three-phase inputs of the second comparator are respectively a low level, a clock input and the output of the transconductance amplifier; wherein the logic processing unit is used to determine whether the sub-sampling phase-locked loop enters a locked state based on the output signal of the first comparator and the output signal of the second comparator.

[0010] In the above-mentioned implementation, the locking state of the sub-sampling phase-locked loop can also be detected based on the locking detection unit. The locking detection unit can monitor the state of the sub-sampling phase-locked loop in real time. When it is detected that the sub-sampling phase-locked loop is not locked, the system can be re-entered into the locking state. The lock state check can better realize working in the locking state, and the overall working stability of the sub-sampling phase-locked loop and the signal generating device can be improved.

[0011] In an optional embodiment, the sub-sampling frequency multiplier further includes: a calibration unit connected to the output end of the first sub-sampling phase detector; the calibration unit is used to calibrate the signal of the transconductance amplifier based on the output of the first sub-sampling phase detector and the input signal obtained by the calibration unit.

[0012] In an optional embodiment, the calibration unit includes: a first chopper connected to the output end of the first sub-sampling phase detector; an amplifier connected to the output end of the first chopper; a second chopper connected to the output end of the amplifier; and a third comparator connected to the output end of the second chopper; wherein the output end of the third comparator is connected to the logic processing unit, and the logic processing unit is used to calibrate the signal of the transconductance amplifier based on the received signal.

[0013] In the above implementation, the first sub-sampling phase detector output signal may be calibrated so that the sub-sampling frequency multiplier operates at the sub-sampling phase detector zero-crossing point, thereby making the phase change more sensitive to the signal amplitude change.

[0014] In an optional implementation, the first voltage-controlled oscillator includes: a grounded capacitor; an antenna connected to the grounded capacitor; and a MOS tube differential oscillator pair connected to the antenna.

[0015] In the above implementation, by integrating the radiating antenna with the oscillator, the antenna suppresses the fundamental signal radiation of the oscillator and strengthens the second harmonic signal radiation. Furthermore, by setting a grounding capacitor, the grounding capacitor can prevent signal leakage between the antenna and the power supply end.

[0016] In an optional embodiment, a first side of the MOS tube differential oscillation pair is connected to a transmission line; the transmission line is configured to have a specified impedance and a specified electrical length; and a second side of the MOS tube differential oscillation pair is connected to a regulating device for regulating the current in the circuit where the MOS tube differential oscillation pair is located.

[0017] In an optional implementation, the antenna is a loop antenna, and the length of the antenna is determined according to the wavelength of the fundamental wave of the first voltage-controlled oscillator.

[0018] In traditional designs, due to the limitation of transistor output power in high frequency bands and the interference of various parasitic parameters, the actual output power is very limited. The maximum output power of transistors limited by the process cannot be changed. In the above implementation, the interference caused by parasitic parameters can be reduced by designing the first voltage-controlled oscillator, and the output power of the oscillator can be maximized by designing the transmission line.

[0019] In an optional implementation, the sub-sampling frequency multiplier further includes: a temperature sensor for detecting the ambient temperature of the environment in which the sub-sampling frequency multiplier is located.

[0020] In the above implementation, by designing a temperature sensor, it is possible to monitor the ambient temperature of the environment where the sub-sampling frequency multiplier is located.

[0021] In an optional implementation, the sub-sampling phase-locked loop includes: a sub-sampling loop and an auxiliary frequency-locked loop; the sub-sampling loop and the auxiliary frequency-locked loop are cascaded.

[0022] In an optional embodiment, the sub-sampling loop includes: a second sub-sampling phase detector, a transconductance charge pump, a pulse generator, a loop filter, and a second voltage-controlled oscillator; wherein the second sub-sampling phase detector, the transconductance charge pump, the loop filter, and the second voltage-controlled oscillator are cascaded; and the output end of the pulse generator is connected to the transconductance charge pump.

[0023] In an optional embodiment, the auxiliary frequency locked loop includes: a frequency detector with a dead zone, a charge pump and a multi-mode divider; the input end of the multi-mode divider is connected to the output end of the second voltage-controlled oscillator; the output end of the multi-mode divider is a frequency detector with a dead zone, and the output end of the frequency detector with a dead zone is connected to the charge pump.

[0024] In the above implementation, the sub-sampling loop utilizes the absence of a frequency divider on the feedback path to greatly improve the core loop gain, so that the loop has better in-band phase noise suppression capability and achieves better phase noise. In addition, the multi-mode frequency divider is designed on the auxiliary frequency-locked loop to reduce the impact on the core loop.

[0025] In a second aspect, the present invention provides a molecular clock, comprising the signal generating device described in any one of the aforementioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A block diagram of a signal generating device provided in an embodiment of the present application;

[0028] Figure 2 A circuit diagram of a signal generating device provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the change of the output voltage of the sub-sampling phase detector provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of a voltage-controlled oscillator provided in an embodiment of the present application;

[0031] Figure 5a A schematic diagram of the working state of the voltage-controlled oscillator provided in an embodiment of the present application;

[0032] Figure 5b A schematic diagram of another working state of the voltage-controlled oscillator provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of a model of a voltage-controlled oscillator provided in an embodiment of the present application;

[0034] Figure 7 A block diagram of a sub-sampling phase-locked loop provided in an embodiment of the present application.

[0035] Icons: 100-subsampling phase-locked loop; 110-subsampling loop; 111-second subsampling phase detector; 112-transconductance charge pump; 113-pulse generator; 114-loop filter; 115-second voltage-controlled oscillator; 120-auxiliary frequency-locked loop; 121-frequency phase detector; 122-charge pump; 123-multi-mode divider; 210-first voltage-controlled oscillator; 211-transmission line; 212-antenna; 213-ground capacitor; 214-MOS tube differential oscillation Pair; 220-first sub-sampling phase detector; 230-transconductance amplifier; 240-logic processing unit; 250-lock detection unit; 251-first comparator; 252-second comparator; 261-inverter; 262-Schmitt trigger; 263-sampling switch; 271-first chopper; 272-amplifier; 273-second chopper; 274-third comparator; 280-temperature sensor; 281-bandgap reference; 282-low dropout linear regulator. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0037] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0038] In the design of millimeter wave signal generator, a charge pump phase-locked loop is usually used to generate a 12.83GHz signal, where the charge pump phase-locked loop includes a voltage-controlled oscillator, a charge pump, a phase detector, and a frequency division link. However, these processes will encounter a common problem in the millimeter wave frequency band: reduced output power. This is mainly due to the limited speed and breakdown voltage of silicon transistors. The terahertz frequency band is close to the highest operating frequency of transistors. At this frequency band, the transistor transconductance is small, making it difficult to obtain sufficient output power.

[0039] Since the operating frequency of the transistor is too high, in some technologies, the harmonics generated by the oscillator are used as the required signal instead of the fundamental wave. For example, if the second harmonic of the oscillator is used as the required output signal, the oscillator only needs to work at half the frequency of the output signal, so the transconductance of the transistor increases and the output power is increased. However, current research has shown that the output achieved based on the above method either has high power consumption or too low output power.

[0040] Based on the above research, the embodiments of the present application provide a signal generating device and a molecular clock that can better output the required high power.

[0041] The present application embodiment provides a signal generating device, such as Figure 1 As shown, the signal generating device may include: a sub-sampling phase-locked loop 100 and a sub-sampling frequency multiplier connected to the sub-sampling phase-locked loop 100 .

[0042] The sub-sampling frequency multiplier includes a first voltage-controlled oscillator 210 , a first sub-sampling phase detector 220 , a transconductance amplifier 230 and a logic processing unit 240 .

[0043] The output ends of the first voltage-controlled oscillator 210 and the sub-sampling phase-locked loop 100 are both connected to the first sub-sampling phase detector 220 ; and the output end of the first sub-sampling phase detector 220 is connected to the transconductance amplifier 230 .

[0044] The logic processing unit 240 is used to output a control signal to the transconductance amplifier 230 to control the output of the transconductance amplifier 230 .

[0045] When the sub-sampling phase-locked loop 100 is in a locked state, the control voltage of the first voltage-controlled oscillator 210 is adjusted by adjusting the reference voltage of the transconductance amplifier 230 .

[0046] In one example, a signal with a sampling frequency of 12.83G is input through the sub-sampling phase-locked loop 100, and the first voltage-controlled oscillator 210 is locked to a frequency of 115.47G through a sub-sampling frequency multiplier. Under the action of the second harmonic of the sub-sampling frequency multiplier, the output frequency is 231.06G, and the output power is -5dBm, which is applied to a chip-level molecular clock transmitter chip to achieve 18 times the frequency.

[0047] In the embodiment of the present application, when the sub-sampling phase-locked loop 100 is locked, the signal generating device architecture can adjust the reference voltage of the common-mode feedback circuit set in the transconductance amplifier 230, thereby adjusting the control voltage Vctrl of the first voltage-controlled oscillator 210, so that the input phase difference is reduced to achieve loop gain calibration, thereby making the phase-locked loop more stable when the PVT (Process Voltage Temperature) changes. The integration of sub-terahertz signal sources can achieve the advantages of high frequency and small size, so as to better realize the miniaturization of radio frequency and millimeter wave circuits, so as to further miniaturize chip-level molecular clocks.

[0048] See also Figure 2 As shown, a buffer may be provided between the sub-sampling phase-locked loop 100 and the first sub-sampling phase detector 220. A buffer may also be provided between the first voltage-controlled oscillator 210 and the first sub-sampling phase detector 220. Figure 2 As shown, a variable resistor VAR may also be provided.

[0049] In order to better understand the locking state of the sub-sampling phase-locked loop 100 and reduce the instability caused by the operation without processing the locking state, the above-mentioned sub-sampling frequency multiplier may also include: a locking detection unit 250 connected to the output of the transconductance amplifier 230, and the output of the locking detection unit 250 is connected to the logic processing unit 240; the detection unit is used to perform frequency locking detection based on the output signal received from the transconductance amplifier 230 to detect whether the sub-sampling phase-locked loop 100 enters the locking state.

[0050] Alternatively, if Figure 2 As shown, the lock detection unit 250 may include a first comparator 251 and a second comparator 252 .

[0051] The three-phase inputs of the first comparator 251 are respectively a high level, a clock input and the output of the transconductance amplifier 230; the three-phase inputs of the second comparator 252 are respectively a low level, a clock input and the output of the transconductance amplifier 230; wherein the logic processing unit 240 is used to determine whether the sub-sampling phase-locked loop 100 enters a locked state based on the output signal of the first comparator 251 and the output signal of the second comparator 252.

[0052] Optionally, the output of the transconductance amplifier 230 received by the first comparator 251 may not be the output of the transconductance amplifier 230 , but an output processed by some processing devices.

[0053] Optionally, the processing device may include devices such as an inverter 261 and a Schmitt trigger 262 .

[0054] Exemplarily, the output end of the transconductance amplifier 230 can also be connected to a DC detection branch. The DC detection branch can include an inverter 261, a Schmitt trigger 262, and a sampling switch 263. The signal output by the transconductance amplifier 230 can be output after passing through the inverter 261, the Schmitt trigger 262, and the sampling switch 263 in sequence. The output signal can be a DC detection level DC_DET, and the lock state is determined based on the DC detection level DC_DET. In an example, when the DC_DET is 0 / 1, it can be determined that the sub-sampling phase-locked loop 100 has entered the lock state, and when the DC_DET output signal is 0.5V, it is determined that the sub-sampling phase-locked loop 100 has not entered the lock state.

[0055] exist Figure 3 In the example shown, the output signal after sequentially passing through the inverter 261, the Schmitt trigger 262 and the sampling switch 263 can be input to the first comparator 251 and the second comparator 252. The first comparator 251 can be input with a high level, and the second comparator 252 can be input with a low level, and then the first comparator 251 can output a common mode high level COMH, and the second comparator 252 can output a common mode low level COML, and then the logic processing unit 240 can sample the outputs of the first comparator 251 and the second comparator 252 to judge and identify the common mode high level COMH and the common mode low level COML, so as to determine whether the sub-sampling phase-locked loop 100 enters a locked state.

[0056] exist Figure 3 In the example shown, the ideal lock point is the origin P1. If the lock point is selected at another location, for example, Figure 3 As shown, a point P2 close to the origin may not be able to suppress the interference of high-order harmonics well.

[0057] The lock detection can be realized by the DC detection branch and the lock detection unit 250. The lock detection is used to determine whether the sub-sampling phase-locked loop 100 has entered the lock state, that is, whether the frequency and phase difference between the output signal in the loop and the reference signal are maintained within the allowed range. When the sub-sampling phase-locked loop 100 is locked, the system can work normally and the output signal is stable. If the sub-sampling phase-locked loop 100 is not locked, the loop output may have frequency drift or jitter, affecting the overall performance. In practical applications, the signal may be interfered or changed (such as sudden frequency jump). Therefore, the lock detection can be continuously detected in the form of real-time monitoring of the loop state. When it is detected that the sub-sampling phase-locked loop 100 is not locked, the protection measures are triggered or the loop parameters are adjusted to make the system re-enter the lock state. In addition, the result of the lock detection can be used to adjust the loop parameters (such as loop gain, bandwidth, etc.) to optimize the dynamic performance and stability of the sub-sampling phase-locked loop 100.

[0058] Since the sub-sampling phase detector is near the zero crossing point, the phase change is most sensitive to the amplitude change of the signal. Therefore, in order to improve the sensitivity of the phase change to the amplitude change of the signal, the sub-sampling frequency multiplier may also include: a calibration unit connected to the output end of the first sub-sampling phase detector 220.

[0059] The calibration unit is used to calibrate the signal of the transconductance amplifier 230 based on the output of the first sub-sampling phase detector 220 and the input signal obtained by the calibration unit.

[0060] Optionally, the calibration unit may include: a first chopper 271 , an amplifier 272 , a second chopper 273 and a third comparator 274 .

[0061] The first chopper 271 is connected to the output end of the first sub-sampling phase detector 220 ; the amplifier 272 can be connected to the output end of the first chopper 271 ; the second chopper 273 is connected to the output end of the amplifier 272 ; and the third comparator 274 is connected to the output end of the second chopper 273 .

[0062] The output end of the third comparator 274 is connected to the logic processing unit 240 , and the logic processing unit 240 is used to calibrate the signal of the transconductance amplifier 230 based on the received signal.

[0063] In this embodiment, the signal output from the output end of the first sub-sampling phase detector 220 can enter the calibration unit for calibration. The logic processing unit 240 can judge the output signal of the calibration unit to filter out the required voltage. The logic processing unit 240 can provide the time point of the required voltage to the first sub-sampling phase detector 220 to complete the calibration.

[0064] Exemplarily, the phase change of the sub-sampling phase detector near the zero crossing point is most sensitive to the amplitude change of the signal. The first sub-sampling phase detector 220 obtains phase information by sampling the amplitude of the input signal, so the zero crossing point can be selected to achieve the most sensitive phase detection. If the sampling position deviates from the zero crossing point, the amplitude response of the phase difference will be weakened, resulting in a decrease in the sensitivity of the phase detection. Further, at the zero crossing point, the change of the input signal is approximately linear, which helps to reduce the error introduced by the nonlinearity of the signal amplitude in the sub-sampling process. Further, since the dynamic performance (such as loop stability and bandwidth) of the sub-sampling phase-locked loop 100 depends on the linear range of the phase detector and the amplitude characteristics of the error signal. Sampling at the zero crossing point of the sub-sampling phase detector, the amplitude of the error signal is linearly related to the phase difference, which is conducive to improving the dynamic performance of the loop. In addition, sampling at the zero crossing point can effectively suppress the interference of higher harmonics, because the main characteristics of the signal at this time are determined by the fundamental wave, and the contribution of higher harmonics is relatively small.

[0065] like Figure 3 As shown, Figure 3 The schematic diagram shows the change of the output voltage of the first sub-sampling phase detector 220. Since the output of the first sub-sampling phase detector 220 and the input of the transconductance amplifier 230 both have an offset voltage, the loop lock of the sub-sampling phase-locked loop 100 will not be at the position of the zero crossing point of the curve of the first sub-sampling phase detector 220. Therefore, after the lock detection of the sub-sampling phase-locked loop 100 is completed, the output signal of the first sub-sampling phase detector 220 can be calibrated.

[0066] For example, in Figure 2 In the example shown, the choppers on both sides of the amplifier 272 of the calibration unit reduce the influence of the input offset voltage of the amplifier 272. When the amplifier 272 amplifies the output signal of the locked first sub-sampling phase detector 220, it is transmitted to the logic processing unit 240 through the third comparator 274. The logic processing unit 240 can determine the output signal of the third comparator 274. When the output signal of the third comparator 274 has continuous 1 and continuous 0, the logic processing unit 240 determines that the voltage corresponding to the junction of 1 and 0 is the voltage after the calibration is completed. At this time, it is considered that the first sub-sampling phase detector 220 is operating at the zero crossing point and the calibration is completed.

[0067] The key component in the signal generating device is the voltage-controlled oscillator, which needs to work in a steady state. When a single transistor works in a steady state, all the fundamental power it generates is distributed and consumed in the peripheral passive network. Since the peripheral network is linear, the higher the output power, the greater the voltage swing and nonlinearity. Based on this, in order to maximize the output power of the voltage-controlled oscillator, a subsampling multiplier can be designed. Figure 4 As shown, the first voltage-controlled oscillator 210 of the sub-sampling frequency multiplier may include a grounding capacitor 213 , an antenna 212 , and a MOS transistor differential oscillation pair 214 .

[0068] The grounding capacitor 213 may be connected to a first side of the antenna 212 , and the MOS transistor differential oscillator pair 214 may be connected to a second side of the antenna 212 .

[0069] exist Figure 4 In the example shown, the first voltage-controlled oscillator 210 may also be designed with a transmission line 211. The transmission line 211 and the antenna 212 are distributed on both sides of the MOS tube differential oscillation pair 214. Figure 4 The first voltage controlled oscillator 210 shown can achieve a second harmonic output of -6dBm with a power consumption of 20mW.

[0070] Exemplarily, the transmission line 211 is configured to have a specified impedance and a specified electrical length. The impedance and electrical length of the transmission line 211 may be determined based on parasitic parameters of the first voltage-controlled oscillator 210 .

[0071] One side of the antenna 212 of the first voltage-controlled oscillator 210 is connected to a grounded capacitor 213, and the lower end is connected to a MOS tube differential oscillator pair 214. Since it is necessary to add power supply to the antenna 212, by connecting one side of the antenna 212 of the first voltage-controlled oscillator 210 to a grounded capacitor 213, the signal leakage between the antenna 212 and the power supply end can be prevented under the action of the grounding electricity.

[0072] In this embodiment, the antenna 212 mainly functions to radiate the second harmonic signal downwards. Therefore, the antenna 212 is a loop antenna 212 , and the length of the antenna 212 can be determined according to the wavelength of the fundamental wave of the first voltage-controlled oscillator 210 .

[0073] Exemplarily, the length of the antenna 212 may be equal to the value range defined by half of the fundamental wave of the first voltage-controlled oscillator 210. The length of the antenna 212 may be (λ / 2-ε, λ / 2+ε), where λ represents the fundamental wave of the first voltage-controlled oscillator 210, and ε may represent a preset smaller value. For example, the ε may be 0.1, 0.2, 0.15, etc. For example, the length of the antenna 212 may be equal to the length of half the wavelength of the fundamental wave of the first voltage-controlled oscillator 210, that is, the length of the half-circle antenna 212 is equal to the length of a quarter wavelength.

[0074] Based on the design of the length of the antenna 212, the signal of the corresponding wavelength can be changed from open circuit to short circuit or from short circuit to open circuit. Figure 5a and Figure 5b As shown, the length of the antenna 212 can be determined as follows: the length of a half circle of the antenna 212 can be one quarter of the fundamental wave. The half circle antenna 212, which is one quarter of the fundamental wave, can prevent the fundamental wave from radiating (i.e., short circuit becomes open circuit), and on the other hand, can allow the second harmonic to be synthesized in the center of the antenna 212 to cause a greater radiation power (short circuit becomes open circuit and then short circuit), so that the second harmonic can be output with higher power in combination with the design of the feedback structure of the dual transmission line 211.

[0075] exist Figure 5a and Figure 5b In the example shown, the light grey portion in the figure is the common ground, the dark grey portion is the antenna 212, and the one-way arrow is the electric field distribution. Figure 5a and Figure 5b The grounding capacitor 213 is shown above the antenna 212, and the MOS tube differential oscillator pair 214 is connected below the antenna 212. From the example shown in the figure, it can be understood that the fundamental frequency cannot be radiated because of the left and right phase cancellation at the grounding capacitor 213 caused by the antenna 212, and the same reason causes the second harmonic signal to be mutually enhanced at the grounding capacitor 213 after passing through the two sections of the antenna 212 and radiated.

[0076] In order to make the first voltage-controlled oscillator 210 have a more stable output, the MOS transistor of the first voltage-controlled oscillator 210 may be modeled.

[0077] For example, we can start with the modeling of the MOS transistor in the first voltage-controlled oscillator 210. The MOS transistor can be modeled as a two-port network with Y parameters using port parameters. For example, the relationship between the voltage and current flowing through the MOS transistor and the Y parameter can be expressed as:

[0078]

[0079] Among them, I1 and I2 represent the current flowing into the MOS tube; V1 and V2 represent the voltage across the MOS tube; Represents the Y parameter.

[0080] The above modeling method can simplify the analysis of MOS tubes into the relationship between Y parameters, which is convenient for deducing the maximum output power. By introducing the transmission line 211 design, the influence of parasitic parameters can be offset to obtain the maximum output power. Figure 6 As shown, the model of the first voltage-controlled oscillator 210 can be divided into three parts: Figure 6 The upper portion N1 of the example shown is designed for a transmission line 211, which is configured with an impedance Z and an electrical length φ. Therefore, as far as the transmission line 211 is concerned, it has two parameters, namely, impedance Z0 and electrical length φ. TL . Figure 6 The middle part N2 of the example shown is a MOS tube model without parasitic parameters; Figure 6 The lower part N3 of the example shown is the influence of parasitic parameters, which is presented in the form of Y parameters including parameter Y1 and parameter Y2.

[0081] exist Figure 6 In the example shown, the current distribution of the model of the first voltage-controlled oscillator 210 is that the current I1 flowing into the MOS tube is divided into I 11 ,I 12 and I 13 , the current I2 flowing into the MOS tube is divided into I 21 ,I 22 and I 23 .

[0082] exist Figure 6 In the model shown, the impedance Z0 and electrical length φ of the transmission line 211 can be designed. TL , so that it can offset the influence of Y1Y2.

[0083] By designing the first voltage-controlled oscillator 210 , the working state of the voltage-controlled oscillator can be reduced to be more stable.

[0084] In order to better understand the working condition of the whole circuit, a temperature sensor 280 may be provided to collect the temperature of the environment where the whole circuit is located. Based on this, the sub-sampling frequency multiplier further includes: a temperature sensor 280 for detecting the ambient temperature of the environment where the sub-sampling frequency multiplier is located.

[0085] Optionally, the temperature sensor 280 may include a bandgap reference 281 and a resistor. The resistor may be a resistor having a positive temperature coefficient as it changes with temperature.

[0086] Alternatively, if Figure 2 As shown, the temperature sensor 280 may further include a bandgap reference 281 (Bandgap Reference, referred to as BGR) and a low-dropout linear regulator 282 (Low-Dropout Linear Regulator, referred to as LDO).

[0087] The coordination of the bandgap reference 281 and the resistor can better reduce the influence of the offset voltage on the temperature accuracy, thereby improving the temperature measurement resolution.

[0088] In order to further improve the in-band phase noise suppression capability of the sub-sampling phase-locked loop 100. Figure 7 As shown, the sub-sampling phase-locked loop 100 may include a sub-sampling loop 110 and an auxiliary frequency-locked loop 120 , and the sub-sampling loop 110 and the auxiliary frequency-locked loop 120 are cascaded.

[0089] Exemplarily, an oven controlled crystal oscillator (OCXO) may be configured to input a 100 MHz signal as a reference signal.

[0090] The sub-sampling phase-locked loop 100 can achieve a 12.83 GHz output with a 100 MHz crystal input signal. The sub-sampling loop 110 as a core loop can directly sample the high-frequency feedback output. Since the auxiliary frequency-locked loop 120 realizes frequency division, and there is no frequency divider on the feedback path of the sub-sampling loop 110, the core loop gain is greatly improved, so that the loop has better in-band phase noise suppression capability. The sub-sampling phase-locked loop 100 is a core loop, and the noise of each module of the sub-sampling phase-locked loop 100 determines the overall phase noise of the sub-sampling phase-locked loop 100. The linearity of the phase interpolator and the time-to-digital converter that realize the fractional function determines the fractional spurious level of the sub-sampling phase-locked loop 100.

[0091] Optionally, the sub-sampling loop 110 may include: a second sub-sampling phase detector 111 (Sub-Sampling Phase Detector, SSPD for short), a transconductance charge pump 112 (Gm-CP), a pulse generator 113 (Pulser), a loop filter 114 , and a second voltage-controlled oscillator 115 .

[0092] The second sub-sampling phase detector 111 , the transconductance charge pump 112 , the loop filter 114 , and the second voltage-controlled oscillator 115 are cascaded; and the output end of the pulse generator 113 is connected to the transconductance charge pump 112 .

[0093] In this embodiment, the frequency divider required by the sub-sampling phase-locked loop 100 can be set on the auxiliary frequency-locked loop 120. The auxiliary frequency-locked loop 120 may include: a phase-frequency detector 121 (Phase-Frequency Detector, PFD) with a dead zone (Dead Zone, DZ), a charge pump 122 (CP) and a multi-mode frequency divider 123.

[0094] The input end of the multi-mode frequency divider 123 is connected to the output end of the second voltage-controlled oscillator 115 ; the output end of the multi-mode frequency divider 123 is connected to the frequency detector 121 with a dead zone, and the output end of the frequency detector 121 with a dead zone is connected to the charge pump 122 .

[0095] The second sub-sampling phase detector 111 uses a low-frequency reference clock to sub-sample the high-frequency second voltage-controlled oscillator 115 feedback output signal. The transconductance charge pump 112 has a higher phase-detection gain suppression. The noise of the transconductance charge pump 112 is transmitted to the output without being multiplied by the N multiple of the multi-mode frequency divider 123, thereby reducing the in-band phase noise. However, when the phase-detection gain of the transconductance charge pump 112 is large to a certain extent, the in-band phase noise will no longer be dominated by the transconductance charge pump 112. At this time, further increasing the phase-detection gain of the transconductance charge pump 112 will not improve the in-band phase noise of the sub-sampling phase-locked loop 100, and a larger loop filter 114 will be required, occupying chip area. For reference, the cascade gain of the transconductance charge pump 112 can also be reduced by adjusting the charge and discharge time of the transconductance charge pump 112 based on the use of the pulse generator 113.

[0096] Due to the sinusoidal phase detection characteristics of the second sub-sampling phase detector 111, the second sub-sampling phase detector 111 is similar to a mixer-based phase detector and has a limited frequency acquisition range. In addition, the sub-sampling process cannot distinguish between the reference signal frequency N·fRef of the N-times second voltage-controlled oscillator 115 and other subharmonics of the reference signal frequency fRef. The sub-sampling phase-locked loop 100 may lock to the wrong frequency, so an additional loop is required to lock the frequency to near N·fRef. When the frequency is close to locked, the auxiliary frequency-locked loop 120 will be closed, and only the sub-sampling loop 110 as the core loop will work to ensure that the sub-sampling phase-locked loop 100 has good in-band phase noise. The auxiliary frequency-locked loop 120 has no effect on the core loop and will not deteriorate the jitter performance of the sub-sampling phase-locked loop 100. Therefore, when the system is just powered on, if the output frequency of the second voltage-controlled oscillator 115 is far away from the locking frequency, at this time, the phase error is greater than the dead zone of the frequency-locked loop phase detector, and the auxiliary frequency-locked loop 120 participates in the work. The frequency detector 121 compares the phase error between the input reference signal and the feedback signal of the frequency divider, and converts it into a narrow pulse to control the switch of the charge pump 122. The charge pump 122 charges and discharges the loop filter 114 to control the accumulated phase of the loop until the phase error is less than the dead zone, and the auxiliary frequency-locked loop 120 stops outputting current to the loop. The core loop begins to take the lead in control, and the second sub-sampling phase detector 111 converts the phase error between the second voltage-controlled oscillator 115 and the input reference signal into a voltage error. The charge pump 122 converts the voltage error into a current error and continues to charge and discharge the loop filter 114 until the second sub-sampling phase detector 111 samples the zero-crossing point of the output of the second voltage-controlled oscillator 115, and the phase lock state is reached. As long as the output frequency fVCO of the second voltage controlled oscillator 115 and the reference signal frequency fRef are integers, the operation can be performed without using a frequency divider.

[0097] based on Figure 2 The structure shown realizes 100MHz signal input and 231.06GHz signal output by cascading the sub-sampling phase-locked loop 100 and the sub-sampling frequency multiplier. Specifically, in the present invention, the sub-sampling phase-locked loop 100 and the sub-sampling frequency multiplier are realized by the sub-sampling architecture. For the sub-sampling frequency multiplier, loop calibration is adopted to reduce the influence of the input offset voltage of the amplifier 272 module on the loop gain, so that the loop is locked at the zero crossing point, so that the loop lock is more stable when the temperature, process and voltage change, and the loop phase noise is better.

[0098] In the present application, the full-chip sub-sampling loop 110 is designed. The sub-sampling phase-locked loop 100 utilizes the absence of a divider on the feedback path to greatly improve the core loop gain, so that the loop has better in-band phase noise suppression capability and achieves better phase noise. At the same time, by calibrating the sub-sampling multiplier, the loop is locked to the place where the loop gain is highest, thereby improving the loop stability and phase noise performance.

[0099] Furthermore, the maximum output power of the transistor can be obtained by designing the transmission line 211 of the first voltage-controlled oscillator 210. The second harmonic output is achieved by integrating the oscillator and the antenna 212 in the second voltage-controlled oscillator 115, and the antenna 212 suppresses the radiation of the fundamental signal of the second voltage-controlled oscillator 115 and enhances the radiation of the second harmonic signal.

[0100] An embodiment of the present application also provides a molecular clock, which includes a signal generating device.

[0101] The signal generating device involved in the embodiment of the present application is similar to the signal generating device provided in the aforementioned embodiment. For other details about the signal generating device, please refer to the description in the aforementioned embodiment, which will not be repeated here.

[0102] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0103] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal generating device, characterized in that: include: A sub-sampling phase-locked loop and a sub-sampling frequency multiplier connected to the sub-sampling phase-locked loop; The sub-sampling frequency multiplier comprises a first voltage-controlled oscillator, a first sub-sampling phase detector, a transconductance amplifier and a logic processing unit; Wherein, the output ends of the first voltage-controlled oscillator and the sub-sampling phase-locked loop are both connected to the first sub-sampling phase detector; the output end of the first sub-sampling phase detector is connected to the transconductance amplifier; The logic processing unit is used to output a control signal to the transconductance amplifier to control the output of the transconductance amplifier; Wherein, when the sub-sampling phase-locked loop is in a locked state, the control voltage of the first voltage-controlled oscillator is adjusted by adjusting the reference voltage of the transconductance amplifier.

2. The signal generating device according to claim 1, characterized in that: The sub-sampling frequency multiplier further comprises: a lock detection unit connected to the output of the transconductance amplifier, the output of the lock detection unit being connected to the logic processing unit; The detection unit is used for performing frequency lock detection based on the output signal of the transconductance amplifier, so as to detect whether the sub-sampling phase-locked loop enters a locked state.

3. The signal generating device according to claim 2, characterized in that: The lock detection unit includes: a first comparator and a second comparator; The three-phase inputs of the first comparator are respectively a high level, a clock input and the output of the transconductance amplifier; The three-phase inputs of the second comparator are respectively a low level, a clock input and the output of the transconductance amplifier; The logic processing unit is used to determine whether the sub-sampling phase-locked loop enters a locked state based on the output signal of the first comparator and the output signal of the second comparator.

4. The signal generating device according to claim 1, characterized in that: The sub-sampling frequency multiplier further comprises: a calibration unit connected to the output end of the first sub-sampling phase detector; The calibration unit is used to calibrate the signal of the transconductance amplifier based on the output of the first sub-sampling phase detector and the input signal obtained by the calibration unit.

5. The signal generating device according to claim 4, characterized in that: The calibration unit comprises: a first chopper connected to an output end of the first sub-sampling phase detector; an amplifier connected to an output of the first chopper; a second chopper connected to the output of the amplifier; A third comparator is connected to the output end of the second chopper; wherein the output end of the third comparator is connected to the logic processing unit, and the logic processing unit is used to calibrate the signal of the transconductance amplifier based on the received signal.

6. The signal generating device according to claim 1, characterized in that: The first voltage controlled oscillator comprises: Grounding capacitor; an antenna connected to the grounded capacitor; A MOS tube differential oscillator pair connected to the antenna.

7. The signal generating device according to claim 6, characterized in that: A first side of the MOS tube differential oscillation pair is connected to a transmission line; The transmission line is configured to have a specified impedance and a specified electrical length; The second side of the MOS transistor differential oscillation pair is connected to a regulating device for regulating the current in the circuit where the MOS transistor differential oscillation pair is located.

8. The signal generating device according to claim 6, characterized in that: The antenna is a loop antenna, and the length of the antenna is determined according to the wavelength of the fundamental wave of the first voltage-controlled oscillator.

9. The signal generating device according to claim 1, characterized in that: The sub-sampling frequency multiplier further includes a temperature sensor for detecting the ambient temperature of the environment in which the sub-sampling frequency multiplier is located.

10. The signal generating device according to any one of claims 1 to 9, characterized in that: The sub-sampling phase-locked loop comprises: a sub-sampling loop and an auxiliary frequency-locked loop; The sub-sampling loop and the auxiliary frequency-locked loop are cascaded.

11. The signal generating device according to claim 10, characterized in that: The sub-sampling loop includes: a second sub-sampling phase detector, a transconductance charge pump, a pulse generator, a loop filter, and a second voltage-controlled oscillator; Wherein, the second sub-sampling phase detector, the transconductance charge pump, the loop filter, and the second voltage-controlled oscillator are cascaded; The output end of the pulse generator is connected to the transconductance charge pump.

12. The signal generating device according to claim 11, characterized in that: The auxiliary frequency locked loop includes: a frequency detector and phase detector with a dead zone, a charge pump and a multi-mode frequency divider; The input end of the multi-mode frequency divider is connected to the output end of the second voltage-controlled oscillator; The output end of the multi-mode frequency divider is provided with a frequency detector and a phase detector with a dead zone, and the output end of the frequency detector and the phase detector with a dead zone is connected to the charge pump.

13. A molecular clock, characterized in that: A signal generating device comprising any one of claims 1-12.

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