Delay phase-locked loop circuit and system device

Abstract

The invention provides a time-delay phase-locked loop circuit and a system device, which are used for optimizing the condition that the DLL locking time is prolonged due to 1C-subtracting operation in the prior art, and adding one step when the first step of 1C-subtracting operation is started (further after the last step of 1C-subtracting operation), so that the original first step of 1C-subtracting operation has two updating opportunities, and the updating time is shortened. The DLL circuit can be locked normally, so that the condition that 1C is firstly added and then 2C is reduced in the actual 1C subtraction operation is avoided, the possibility that the phase discrimination result of the phase discriminator is wrong is reduced, the condition that the 1C subtraction operation which needs to be executed for one beat is executed for multiple times due to the wrong phase discrimination result of the phase discriminator is avoided, the DLL circuit can be locked normally, and the normal operation of the system device is ensured. Besides, according to the technical scheme of the invention, one step can be added after the last step minus 1C operation is completed, so that two updating opportunities exist in the original first step of fine adjustment operation (such as + 4F operation), and the possibility of phase discrimination result errors of the phase discriminator is further reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a delayed phase-locked loop circuit and a system device. Background Art

[0002] When an external clock signal applied from an external device is used in a corresponding system device, a delay or clock deviation may be generated by the internal circuit of the system device. Currently, a delay-locked loop (DLL) circuit is usually used to compensate for this delay or clock deviation, so that the output frequency and phase of the system device are locked to an output clock signal with a fixed frequency and phase, and the phase of the output clock signal and the external clock signal are synchronized (they can be edge-aligned or differ by a fixed value). At this time, the DLL circuit is locked to ensure the normal operation of the system device.

[0003] At present, in the actual DLL circuit locking process, the DLL circuit locking time may become longer, thereby causing the system device to fail to operate normally. Summary of the invention

[0004] The object of the present invention is to provide a delay phase-locked loop circuit and a system device, which can optimize the situation where the DLL locking time is prolonged, thereby ensuring the normal operation of the system device.

[0005] To achieve the above object, the present invention provides a delay phase-locked loop circuit, comprising a controllable delay chain and a control circuit, wherein the controllable delay chain comprises a coarse adjustment delay chain and a fine adjustment delay chain, wherein the coarse adjustment delay chain is used to output a first clock and a second clock with a phase difference of 1C to the fine adjustment delay chain, 1C being a unit coarse adjustment step; the control circuit is used to output a coarse adjustment code to control the delay of the coarse adjustment delay chain and output a fine adjustment code to control the delay of the fine adjustment delay chain, and implement a 1C-subtraction operation of the output of the fine adjustment delay chain, wherein when performing the first step of the 1C-subtraction operation of the output of the fine adjustment delay chain, the control circuit is further configured as follows:

[0006] Outputting a second coarse adjustment code to the coarse adjustment delay chain in an initial state, and outputting a second fine adjustment code to the fine adjustment delay chain at the same time, so that the fine adjustment delay chain selects the second clock output;

[0007] When the first update timing is reached, the second fine adjustment code is kept output unchanged, so that the fine adjustment delay chain still selects the second clock output, and at the same time, a first coarse adjustment code different from the second coarse adjustment code is output to the coarse adjustment delay chain to perform a 2C subtraction operation on the first clock;

[0008] When the second update timing is reached, a first fine adjustment code different from the second fine adjustment code is output to the fine adjustment delay chain, so that the fine adjustment delay chain selects the first clock output to implement the first step minus 1C operation of the output of the fine adjustment delay chain.

[0009] Optionally, the first fine adjustment code is a minimum value of all fine adjustment codes that can be output by the control circuit, and the second fine adjustment code is a maximum value of all fine adjustment codes that can be output by the control circuit.

[0010] Optionally, the control circuit is further configured to: when the second update timing arrives, while outputting the first fine adjustment code, also output a zeroth coarse adjustment code different from the first coarse adjustment code to the coarse adjustment delay chain to perform a 2C subtraction operation on the second clock.

[0011] Optionally, the first coarse adjustment code is the second coarse adjustment code minus 1, and / or the zeroth coarse adjustment code is the first coarse adjustment code minus 1.

[0012] Optionally, the control circuit is further configured to start fine-tuning the output of the fine-tuning delay chain after completing the last step of subtracting 1C from the output of the fine-tuning delay chain.

[0013] Optionally, when performing the first step of fine adjustment operation on the output of the fine adjustment delay chain, the control circuit is further configured to:

[0014] In an initial state, outputting the zeroth coarse adjustment code to the coarse adjustment delay chain, and outputting the first fine adjustment code to the fine adjustment delay chain, so that the fine adjustment delay chain selects the first clock output;

[0015] When the first update timing is reached, the first fine adjustment code is kept output unchanged, so that the fine adjustment delay chain still selects the first clock output, and the first coarse adjustment code is output to the coarse adjustment delay chain to perform a 2C operation on the second clock;

[0016] When the second update timing is reached, the output of the first coarse adjustment code is kept unchanged, and a third fine adjustment code different from the first fine adjustment code is output to the fine adjustment delay chain, so that the fine adjustment delay chain performs a phase adjustment on its output according to the third fine adjustment code, so as to implement the first step of fine adjustment operation on the output of the fine adjustment delay chain.

[0017] Optionally, after completing the first fine adjustment operation, the output of the fine adjustment delay chain is updated to a clock signal with an earlier phase between the first clock and the second clock.

[0018] Optionally, the control circuit includes:

[0019] a state stretching circuit, configured to generate a fine-tuning gating signal and a stretching control signal according to an original control signal and an update timing signal, wherein a first edge of the stretching control signal is aligned with a first edge of the original control signal, and a second edge of the stretching control signal is delayed relative to a second edge of the original control signal; and

[0020] The fine tuning code control circuit is used to generate a fine tuning code control signal according to the fine tuning control clock and the fine tuning gating signal, and the fine tuning code control signal is used to freeze the fine tuning code.

[0021] Optionally, the state widening circuit includes:

[0022] A first trigger, whose clock terminal is coupled to the update timing signal, whose input terminal is coupled to the original control signal, and whose output terminal outputs a delayed control signal with a delay relative to the original control signal;

[0023] an XOR logic circuit, a first input terminal of which is coupled to the original control signal, a second input terminal of which is coupled to the delay control signal, and an output terminal of which outputs the fine-tuning gating signal; and

[0024] A first AND logic circuit, wherein a first input terminal thereof is coupled to the original control signal, a second input terminal thereof is coupled to the delay control signal, and an output terminal thereof outputs the stretch control signal;

[0025] And / or, the fine-tuning code control circuit includes a second AND logic circuit, a first input terminal of which is coupled to the fine-tuning gating signal, a second input terminal of which is coupled to the fine-tuning control clock, and an output terminal of which outputs the fine-tuning code control signal.

[0026] Optionally, the delay phase-locked loop circuit further includes:

[0027] A clock buffer circuit, whose input end is coupled to the output end of the fine-adjustment delay chain, and is used to convert the output of the fine-adjustment delay chain into an internal clock required for the operation of the internal circuit of the system device;

[0028] A clock replica buffer circuit, whose input end is coupled to the output end of the fine-adjustment delay chain, and is used to delay the output of the fine-adjustment delay chain and output it as a feedback clock signal;

[0029] A phase detector has one input end coupled to the input end of the controllable delay chain and another input end coupled to the output end of the replica clock buffer circuit, and is used to identify the phase difference between the external clock signal received by the controllable delay chain and the feedback clock signal, and output the phase detection result to the control circuit.

[0030] Based on the same inventive concept, the present invention further provides a system device, which includes the delay locked loop circuit as described in the present invention.

[0031] Optionally, the system device is a memory chip, the clock signal output by the delay phase-locked loop circuit is a data selection pulse signal of the memory chip, and the delay phase-locked loop circuit is used to adjust the phase difference between an external clock signal input to the memory chip and the data selection pulse signal until the external clock signal is phase-synchronized with the data selection pulse signal and locked.

[0032] Compared with the prior art, the delay phase-locked loop circuit and the system device having the delay phase-locked loop circuit provided by the present invention optimize the situation in the prior art where the subtraction 1C operation causes the DLL locking time to be prolonged. An additional step is added at the beginning of the first step of the subtraction 1C operation, so that the original first step of the subtraction 1C operation has two update opportunities, thereby avoiding the situation where the actual subtraction 1C operation "first adds 1C and then subtracts 2C", reducing the possibility of an error in the phase detection result of the phase detector, thereby avoiding the situation where the subtraction 1C operation that should be executed for one beat is executed multiple times due to an error in the phase detection result of the phase detector, so that the DLL circuit can be locked normally, and the normal operation of the system device is guaranteed.

[0033] In addition, the technical solution of the present invention can add a step after completing the last step of subtracting 1C operation, so that there are two update opportunities in the original first step of fine-tuning operation (for example, +4F operation), further reducing the possibility of error in the phase detection result of the phase detector, which is more conducive to achieving rapid locking of the DLL circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0035] Figure 1 The invention is a schematic diagram of the structure of an existing delay phase-locked loop circuit.

[0036] Figure 2 yes Figure 1 The schematic diagram of control code and clock changes when the output of the fine-tuning delay chain in the delay phase-locked loop circuit performs a +1C operation is shown.

[0037] Figure 3 yes Figure 1 The schematic diagram of control code and clock changes when the output of the fine-tuning delay chain in the delay phase-locked loop circuit performs -1C operation is shown.

[0038] Figure 4 yes Figure 1 The DQS in the delay phase-locked loop circuit shown fb Schematic diagram of the changes of VCLK and VCLK during -1C operation.

[0039] Figure 5It is a schematic diagram of the structure of a delay phase-locked loop circuit according to an embodiment of the present invention.

[0040] Figure 6 yes Figure 5 The schematic diagram of control code and clock changes when the output of the fine-tuning delay chain in the delay phase-locked loop circuit performs -1C operation is shown.

[0041] Figure 7 yes Figure 5 The schematic diagram of control code and clock changes when the output of the fine-tuning delay chain in the delay phase-locked loop circuit performs -1C operation is shown.

[0042] Figure 8 The figure is a schematic diagram of a circuit example structure of a control circuit in a delay phase-locked loop circuit according to an embodiment of the present invention.

[0043] Fig. 9 It is a timing diagram of some signals in a delay phase-locked loop circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] As described in the background technology, the application field of DLL circuit technology is relatively wide. For example, in DRAM (Dynamic Random Access Memory) chips, the DLL circuit is used to align the phase of the external clock signal VCLK input to the DRAM chip by the external bus and the output clock signal DQS generated by the DRAM chip. When the phases of VCLK and DQS are aligned, the DLL circuit is locked. For DRAM chips, the fast locking of the DLL circuit can ensure the correct implementation of operations such as reading and writing.

[0046] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a typical DLL circuit, which includes a controllable delay chain (i.e., Delay Line) 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, and a phase detector (PD) 14. The replica clock buffer circuit 13 is a replica circuit of the clock buffer circuit 11. The controllable delay chain 10 receives an external clock signal VCLK, delays the external clock signal VCLK, and outputs it as a delayed clock signal CLKout. The replica clock buffer circuit 13 provides a feedback clock signal DQS after delaying the delayed clock signal CLKout. fb , phase detector 14 pairs of VCLK and DQS fb The control circuit 12 generates corresponding control codes (i.e., coarse adjustment codes Coarse Code and fine adjustment codes Fine Code) according to the phase detection result of the phase detector 14 to control the length of the controllable delay chain (DelayLine) 10 to increase or decrease, so as to increase or decrease the delay of CLKout relative to VCLK, and then adjust the phase difference between VCLK and DQS until the phases of VCLK and DQS are synchronized (or in other words, the phase difference between the two is 0), and the DLL circuit is locked. At this time, VCLK and DQS are aligned (i.e., synchronized).

[0047] Please combine Figure 1, the controllable delay chain 10 includes a coarse delay chain (Coarse Delay Line) 10a and a fine delay chain (Fine Delay Line) 10b. During the DLL locking process, the coarse delay chain 10a outputs two clock signals, namely, a first clock (e.g., an odd clock) even clk and a second clock (e.g., an even clock) oddclk, according to the coarse code (Coarse code) output by the control circuit 12. The time difference between the two clock signals is 1C (i.e., the minimum coarse step, representing the minimum delay that the controllable delay chain 10 can increase or decrease during the coarse adjustment of the delay). The fine delay chain 10b receives the first clock even clk and the second clock odd clk output by the coarse delay chain 10a, and outputs a phase-adjusted clock signal CLK_out according to the fine code (Fine code) output by the control circuit 12. For example, when the fine code is <0000> When the fine-tuning code is <1111> (i.e., the maximum value of the fine-tuning code), the second clock odd clk is output as CLK_out, and when the fine-tuning code is at an intermediate value, a clock signal located between the phases of the first clock even clk and the second clock odd clk is output as CLK_out.

[0048] Among them, it is assumed that when DLL locking starts, the fine code in the initial state is Fine code = <0000> , fine-tune the delay chain 10b to select the first clock even clk output, that is, CLK_out is even clk. When performing the plus 1C operation (i.e. "+1C"), please refer to Figure 2 , there are: ① Fine code Fine code from <0000> Switch directly to <1111> , indicating that the fine-tuning delay chain 10b switches its output CLK_out from even clk to odd clk; ② Coarse code switching, code2 = code1 + 1, the first clock even clk is adjusted, so that the output CLK_out of the fine-tuning delay chain 10b finally realizes the +1C operation function. When performing -1C operation, please refer to Figure 3 , there are: ① Fine code Fine code first from <1111> Switch directly to <0000> , indicating that the fine-tuning delay chain 10b switches the output CLK_out from odd clk to even clk, which is equivalent to first performing "+1C" on CLK_out; ② The coarse-tuning code Coarse code switches, code1=code2-1, and the first clock even clk is adjusted, which is equivalent to performing "-2C" on CLK_out again, thereby the output CLK_out of the fine-tuning delay chain 10b finally realizes the -1C operation function.

[0049] Obviously, when the +1C or -1C operation is performed, both the coarse code and the fine code will change, so Figure 2 , Figure 3 In the example, ① comes first and ② comes second. Since the coarse adjustment delay chain 10a includes an initial delay, the delay of the coarse adjustment delay chain 10a is generally greater than the delay of the fine adjustment delay chain 10b. That is, the delay of the controllable delay chain 10 is fine-tuned first and then coarse-tuned under the control of the control circuit 12. Among them, for the case of -1C operation, since ① comes first and ② comes second, the -1C operation is equivalent to "+1C first, then -2C". Finally, the feedback clock signal DQS received at the input end of the phase detector 14 is fb It is also "first +1C, then -2C", which may lead to the following problems:

[0050] Please refer to Figure 4 As shown, assuming that DQS fb The rising edge is after the VCLK rising edge. After the -1C operation, if the phase detection result of the phase detector 14 is reversed, it means that DQS fb The rising edge is adjusted to before the rising edge of VCLK. However, since the actual -1C operation is "first +1C, then -2C", the phase detector 14 may detect the effect of +1C, and its phase detection result is not flipped (that is, the phase detection result of the phase detector 14 is wrong). At this time, the control circuit 12 believes that -1C is required, which causes the -1C operation that should be performed in one step to be performed in multiple steps (that is, multiple steps of -1C operation are performed incorrectly) due to the wrong phase detection result of the phase detector 14, which leads to DQS fb The rising edge is getting farther and farther away from the VCLK rising edge, resulting in a situation where the DLL locking time is greatly prolonged, affecting the normal operation of the system device.

[0051] Based on this, the present invention provides a delay phase-locked loop (DLL) circuit and a system device having the delay phase-locked loop (DLL) circuit, which modifies the control circuit (also called "controller") in the DLL circuit, and can optimize the situation in the prior art where the -1C operation causes the DLL locking time to be prolonged. It adds one step at the beginning of the first step of the subtracting 1C operation, so that the original first step of the subtracting 1C operation has two update opportunities, avoiding the situation of "adding 1C first and then subtracting 2C" in the actual subtracting 1C operation, so that the DQS received by the phase detector in the DLL circuit is fbThe delay change is consistent with the change of the control code output by the control circuit in the DLL circuit, reducing the possibility of the phase detector's phase detection result being wrong, thereby avoiding the situation where the minus 1C operation that should be executed once is executed multiple times due to the wrong phase detection result of the phase detector, so that the DLL circuit can be locked normally to ensure the normal operation of the system device. Furthermore, the technical solution of the present invention can add a step after completing the last step of the minus 1C operation, so that the original first step of the fine adjustment operation (for example, the +4F operation) has two update opportunities, further reducing the possibility of the phase detector's phase detection result being wrong.

[0052] Please refer to Figure 5 An embodiment of the present invention provides a delay phase-locked loop (DLL) circuit, which includes a controllable delay chain 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13 and a phase detector 14. The controllable delay chain 10 includes a coarse adjustment delay chain 10a and a fine adjustment delay chain 10b. The control circuit 12 is used to output a coarse adjustment code Coarse Code to control the delay of the coarse adjustment delay chain 10a. The control circuit 12 is also used to output a fine adjustment code Fine Code to control the delay of the fine adjustment delay chain 10b and implement the adjustment operation of the output CLK_out of the fine adjustment delay chain 10b. The unit coarse adjustment step of the coarse adjustment delay chain 10a is 1C (also called "minimum coarse adjustment step", representing the minimum delay that can be increased or decreased by the coarse adjustment delay chain 10a during the delay coarse adjustment process), and the unit coarse adjustment step of the fine adjustment delay chain 10b is 1F (also called "minimum fine adjustment step", representing the minimum delay that can be increased or decreased by the fine adjustment delay chain 10b during the delay fine adjustment process). Exemplarily, 1C=16F, and the adjustment operation implemented by the control circuit 12 on the output CLK_out of the fine adjustment delay chain 10b through the control code may include adding 1C operation, subtracting 1C operation, adding 4F operation, adding 1F operation, subtracting 1F operation, etc.

[0053] The coarse adjustment delay chain 10a is coupled to the control circuit 12. During the DLL locking process, the coarse adjustment delay chain 10a outputs the received external clock signal VCLK as two clock signals, namely, a first clock (e.g., an odd clock) even clk and a second clock (e.g., an even clock) odd clk, to the fine adjustment delay chain 10b according to the coarse adjustment code Coarse code output by the control circuit 12. The time difference between the two clock signals is a unit coarse adjustment step size 1C. The fine adjustment delay chain 10b receives the first clock even clk and the second clock odd clk output by the coarse adjustment delay chain 10a, and outputs the phase-adjusted clock signal CLK_out according to the fine adjustment code Fine code output by the control circuit 12. In one example, when the fine adjustment code Fine code is <0000> (i.e., the minimum value of the fine code), the first clock even clk is output as CLK_out. When the fine code is Fine code <1111> (i.e. the maximum value of the fine code), the second clock odd clk is output as CLK_out, and when the fine code Fine code is at an intermediate value, a clock signal located between the phases of the first clock even clk and the second clock odd clk is output as CLK_out.

[0054] An input terminal of the clock buffer circuit 11 is coupled to an output terminal of the fine delay chain 10 b for converting the output CLK_out of the fine delay chain 10 b into an internal clock DQS required for the operation of the internal circuit of the system device.

[0055] The replica clock buffer circuit 13 is a replica circuit of the clock buffer circuit 11. The input end of the replica clock buffer circuit 13 is coupled to the output end of the fine-tuning delay chain 10b, and is used to delay the output CLK_out of the fine-tuning delay chain 10b and output it as the feedback clock signal DQS. fb .

[0056] One input terminal of the phase detector 14 is coupled to VCLK and the input terminal of the coarse adjustment delay chain 10a, and the other input terminal of the phase detector 14 is coupled to the output terminal of the replica clock buffer circuit 13, and is used to identify the external clock signal VCLK and the feedback clock signal DQS. fb The phase difference between them is calculated and the phase detection result is output to the control circuit 12.

[0057] The control circuit 12 generates a corresponding coarse adjustment code Coarse Code according to the phase detection result of the phase detector 14 to control the length of the coarse adjustment delay chain 10a to increase or decrease, so as to increase or decrease the delay of the first clock even clk or the second clock odd clk relative to VCLK, and at the same time outputs a fine adjustment code Fine Code to control the length of the fine adjustment delay chain 10b to increase or decrease, so as to increase or decrease the delay of CLK_out relative to VCLK, and then adjust the phase difference between VCLK and the internal clock signal DQS output by the clock buffer circuit until the phase between VCLK and DQS is synchronized and the DLL circuit is locked. At this time, VCLK and DQS are aligned (i.e., synchronized).

[0058] In the delay phase-locked loop circuit of this embodiment, the process in which the control circuit 12 controls the controllable delay chain 10 to fine-tune the output CLK_out of the delay chain 10b by adding 1C (i.e., "+1C") is the same as that in the prior art, i.e., please refer to Figure 2 , assuming that when DLL locking starts, the initial state fine code Fine code = <0000> , the fine adjustment delay chain 10b selects the first clock even clk output, that is, CLK_out is even clk, when performing the plus 1C operation (i.e. "+1C"), there are: ① Fine adjustment code Fine code from <0000> Switch directly to <1111> , indicating that the fine-tuning delay chain 10b switches its output CLK_out from even clk to oddclk; ② The coarse-tuning code Coarse code switches, code2=code1+1, and the first clock even clk is adjusted, so that the output CLK_out of the fine-tuning delay chain 10b finally realizes the +1C operation function.

[0059] In the delay phase-locked loop circuit of this embodiment, the process in which the control circuit 12 controls the controllable delay chain 10 to fine-tune the output CLK_out of the delay chain 10b by 1C (i.e., "-1C") is different from the prior art. In one example, the control circuit 12 adds one step to the beginning of the CLK_out-1C operation (i.e., the first step -1C operation) to make DQS fb The delay change is consistent with the change of the control code output by the control circuit 12, reducing the possibility of error in the phase detection result of the phase detector 14, so that the DLL circuit can be locked normally.

[0060] In this example, the clock cycles of the fine control clock Fine clk of the fine delay chain 10b and the coarse control clock Coarse clk of the coarse delay chain 10a are both Xn*Tck, which means that the control circuit 12 updates the outputted fine code Fine code and coarse code Coarse code once every Xn*Tck. Therefore, in this example, the control circuit 12 optimizes the -1C operation of the first step and completes it in two steps (i.e., the -1C operation of the first step includes 2 Xn*Tck). In the -1C operation of the first step, the control circuit 12 updates the control code code once every Xn*Tck. Specifically, please refer to Figure 5 and Figure 6 , assuming that in the initial state, the control circuit 12 outputs the second coarse adjustment code code2 to the coarse adjustment delay chain 10a, and outputs the second fine adjustment code <1111> The fine adjustment delay chain 10b is given such that the fine adjustment delay chain 10b selects the second clock odd clk to output, that is, CLK_out=odd clk at this time. When performing the first step -1C operation of the output CLK_out of the fine adjustment delay chain 10b, the control circuit 12 is further configured as follows:

[0061] ①, when the first update timing Xn1_1 (i.e., the first Xn*Tck) is reached, the control circuit 12 keeps outputting the second fine adjustment code unchanged, and at the same time outputs the first coarse adjustment code code1 which is different from the second coarse adjustment code code2 to the coarse adjustment delay chain 10a, so as to first perform a 2C ("-2C") operation on the first clock even clk (or, the first clock even clk is first performed with -2C). At this time, the fine adjustment delay chain 10b still selects the second clock odd clk to output, i.e., the delay of CLK_out remains unchanged, and the phase detection result of the phase detector 14 remains unchanged (i.e., the output of the phase detector 14 remains unchanged). In one example, code1=code2-1 (i.e., the first coarse adjustment code code1 is the second coarse adjustment code code2 minus 1), and the second fine adjustment code is the maximum value of all fine adjustment codes that can be output by the control circuit 12, for example, <1111> .

[0062] ②. When the second update timing Xn1_2 (i.e., the second Xn*Tck) is reached, the control circuit 12 outputs the first fine adjustment code different from the second fine adjustment code to the fine adjustment delay chain 10b, and also outputs the zeroth coarse adjustment code code0 different from the second coarse adjustment code code2 and the first coarse adjustment code code1 to the coarse adjustment delay chain 10a. At this time, the fine adjustment delay chain 10b selects the first clock even clk output to implement the first step -1C operation of the output CLK_out of the fine adjustment delay chain 10b, that is, the delay of CLK_out is relative to ①-1C. In one example, code0=code1-1 (i.e., the zeroth coarse adjustment code code0 is the first coarse adjustment code code1 minus 1), and at this time, the second clock odd clk is subtracted by 2C ("-2C") (or, the second clock odd clk is again -2C). The second fine adjustment code is the minimum value of all fine adjustment codes that can be output by the control circuit 12, for example <0000> .

[0063] Afterwards, when performing the second step and subsequent -1C operations on CLK_out, the normal timing in the prior art may be followed.

[0064] Therefore, please refer to Figure 6 , when the +1C operation on CLK_out changes to -1C operation, the -1C operation implemented by the control circuit 12 is executed. Compared with the prior art, the first update opportunity Xn1_1 operation is executed more (i.e., one more step is executed such as Figure 6 ①) in the figure, CLK_out can be updated to a signal with a later phase in even clk and oddclk, and then the situation of CLK_out "first +1C, then -2C" will not occur during normal -1C operation. That is, in this embodiment, at the beginning of the first step -1C operation, a step is added, so that there are two update opportunities in the original first step -1C operation, thereby reducing the error of the phase detection result of the phase detector 14, thereby avoiding the situation that the subtraction 1C operation that should be executed once is executed multiple times due to the error of the phase detection result of the phase detector, so that the DLL circuit can be locked normally, ensuring the normal operation of the system device.

[0065] In another example, the clock periods of the fine control clock Fine clk of the fine control delay chain 10b and the coarse control clock Coarse clk of the coarse control delay chain 10a are both Xn*Tck, which means that the control circuit 12 updates the fine control code Fine code and the coarse control code Coarse code outputted by it every Xn*Tck. Therefore, in this example, the control circuit 12 optimizes the -1C operation of the first step and completes it in two steps (that is, the -1C operation of the first step includes 2 Xn*Tcks), and optimizes the first step fine adjustment operation Fine delay (whose step length is, for example, +4F) after the last step -1C operation to complete it in two steps (for example, the last step -1C operation is followed by the first step +4F operation, and the first step +4F operation includes 2 Xn*Tcks). In the first step -1C operation and the first step fine adjustment operation (for example, the first step +4F operation), the control circuit 12 updates the control code code every time an Xn*Tck is reached. Therefore, the control circuit 12 first performs a 1C subtraction operation on CLK_out (which can be executed in multiple working beats, that is, each working beat can be called a one-step 1C subtraction operation or a one-beat 1C subtraction operation), and then performs a fine-tuning operation (for example, a +4F operation, which can also be executed in multiple working beats, that is, each working beat can be called a one-step +4F operation or a one-beat +4F operation). The control circuit 12 increases one step at the beginning (that is, at the beginning of the first step -1C operation) and after the end (that is, after the last step -1C operation, or at the beginning of the first fine-tuning operation) of the -1C operation on CLK_out, and finally DQS fb The delay change of the control circuit 12 is consistent with the change of the control code output by the control circuit 12, and the possibility of error in the phase detection result of the phase detector 14 is reduced, so that the DLL circuit can be locked normally. Among them, when the output CLK_out of the fine adjustment delay chain 10b is subjected to the first step -1C operation, the configuration function of the control circuit 12 is as follows Figure 6 As described in S11 and S12 above, they will not be repeated here.

[0066] Please further combine Figure 5 and Figure 7 As shown, in the initial state after completing the last step -1C operation, the control circuit 12 outputs the zeroth coarse adjustment code code0 to the coarse adjustment delay chain 10a, and outputs the first fine adjustment code to the fine adjustment delay chain 10b, so that the fine adjustment delay chain 10b selects the first clock even clk output, and when the first step fine adjustment operation (for example, +4F operation) is performed on the output CLK_out of the fine adjustment delay chain 10b, the control circuit 12 is further configured as follows:

[0067] ①. When the first update timing Xn2_1 (i.e., the first Xn*Tck) is reached, the output of the first fine adjustment code is kept unchanged, and the first coarse adjustment code code1 is output to the coarse adjustment delay chain 10a. At this time, the fine adjustment delay chain 10b still selects the first clock evenclk output, that is, the delay of CLK_out remains unchanged, and the phase detection result of the phase detector 14 remains unchanged (i.e., the output of the phase detector 14 remains unchanged). At the same time, the second clock odd clk is added with 2C ("+2C").

[0068] ②, when the second update timing Xn2_2 (i.e., the second Xn*Tck) is reached, the first coarse adjustment code code1 is kept unchanged, and a third fine adjustment code different from the first fine adjustment code is output to the fine adjustment delay chain 10b, whereby the fine adjustment delay chain 10b performs a phase adjustment on its output CLK_out according to the third fine adjustment code, and adds a delay to CLK_out normally, thereby performing the first step of fine adjustment operation (e.g., +4F operation) on the output CLK_out of the fine adjustment delay chain 10b. In one example, the first fine adjustment code is <0000> , the third fine tuning code is <0100> .

[0069] Afterwards, when performing the second step and subsequent fine adjustment operations on CLK_out, the normal timing in the prior art may be followed.

[0070] Therefore, when CLK_out is changed from -1C operation to +4F operation, one more step is performed compared to the prior art. Figure 7 As shown in ①, CLK_out can be updated to the signal with the earlier phase in even clk and odd clk, so that CLK_out can be delayed normally afterwards to make DQS fb The delay change is consistent with the change of the control code output by the control circuit 13, further reducing the possibility of error in the phase detection result of the phase detector, which is conducive to faster phase alignment of VCLK and DQS and rapid locking of the DLL circuit.

[0071] It should be understood that the control circuit 12 of this embodiment can realize the above functional configuration by adding any appropriate hardware circuit design.

[0072] Optionally, refer to Figure 8 and Fig. 9The hardware circuit (i.e., the modified part) added to the control circuit 12 relative to the prior art includes a state widening circuit 121 and a fine adjustment code control circuit 122. The state widening circuit 121 is used to generate a fine adjustment gating signal Fine gating and a widening control signal -1Cctrl new according to the original control signal -1C ctrl and the update timing signal Xn clk, wherein the first edge of the widening control signal -1C ctrl new is aligned with the first edge of the original control signal -1C ctrl, and the second edge of the widening control signal -1C ctrl new is delayed relative to the second edge of the original control signal -1C ctrl. The fine code control circuit 122 is used to generate a fine code control signal Fine clk new according to the fine control clock Fine clk and the fine gating signal Fine gating. The fine code control signal Fine clk new is used to disable (gating) the fine control clock Fine clk at the beginning of the first -1C operation and after the last -1C operation (or at the beginning of the first +4F operation) of CLK_out, so as to freeze the fine code Fine code. In the control circuit 12, when the -1C operation is performed on CLK_out, -1C ctrl is valid, and the clock cycles of the fine control clock Fine clk and the coarse control clock Coarsecode are both Xn*Tck, which means that the fine code Fine code and the coarse code Coarsecode are updated every Xn*Tck; when -1C ctrl new fails, the valid signal of the +4F operation is triggered, and the normal +4F operation is performed on CLK_out.

[0073] As an example, see Figure 8The state widening circuit includes a first trigger U1, an XNOR logic circuit XNOR, a first AND logic circuit AND1 and a second AND logic circuit AND2. The clock terminal Clkb of the first trigger U1 is coupled to the update timing signal Xn clk, the input terminal D of the first trigger U1 is coupled to the original control signal -1C ctrl, and the output terminal Q of the first trigger U1 outputs a delay control signal -1C ctrl delay which is delayed relative to the original control signal -1C ctrl. The XNOR logic circuit XNOR can be an XNOR gate or other circuits constituting XNOR logic. The first input terminal of the XNOR logic circuit XNOR is coupled to the original control signal -1C ctrl, the second input terminal of the XNOR logic circuit XNOR is coupled to the delay control signal -1C ctrl delay, and the output terminal of the XNOR logic circuit XNOR outputs a fine-tuning gating signal Finegating. The first AND logic circuit AND1 can be an AND gate or other suitable circuits constituting AND logic. The first input end of the first AND logic circuit AND1 is coupled to the original control signal -1C ctrl, the second input end of the first AND logic circuit AND1 is coupled to the delay control signal -1C ctrl delay, and the output end of the first AND logic circuit AND1 outputs the widening control signal -1Cctrl new.

[0074] In one example, the fine-tuning code control circuit 122 includes a second AND logic circuit AND2, which can be an AND gate or any other suitable circuit constituting AND logic, a first input terminal of the second AND logic circuit AND2 is coupled to the fine-tuning gating signal Fine gating, a second input terminal of the second AND logic circuit AND2 is coupled to the fine-tuning control clock Fine clk, and an output terminal of the second AND logic circuit AND2 outputs the fine-tuning code control signal Fine clk new.

[0075] It should be understood that a state machine (not shown) may be provided in the control circuit 12, and the above-mentioned state widening circuit 121 and fine-tuning code control circuit 122 may be integrated in the state machine, and the state machine outputs corresponding coarse-tuning codes and fine-tuning codes according to the outputs of the state widening circuit 121 and the fine-tuning code control circuit 122 to control the controllable delay chain 10 to perform coarse-tuning operations such as +1C and -1C and fine-tuning operations such as +4F and +1F, until VCLK is aligned with DQS, and the state machine enters a locked state to complete the locking of the DLL circuit.

[0076] Based on the same invention concept, please refer to Figure 5 and Figure 8 This embodiment also provides a system device, which includes the delay phase-locked loop circuit as described in the present invention.

[0077] In one example, the system device is a memory chip (e.g., a DRAM chip), and the clock signal DQS output by the delay locked loop circuit is a data selection pulse signal of the memory chip. The delay locked loop circuit is used to adjust the phase difference between the external clock signal VCLK input to the memory chip and the data selection pulse signal DQS until the external clock signal VCLK and the data selection pulse signal DQS are phase-synchronized and locked. For the memory chip, the fast locking of the DLL circuit can ensure the correct implementation of operations such as reading and writing.

[0078] In summary, the delay phase-locked loop circuit and the system device having the delay phase-locked loop circuit provided by the present invention optimize the situation in the prior art where the subtraction 1C operation causes the DLL locking time to be prolonged. A step is added at the beginning of the first step of the subtraction 1C operation, so that the original first step of the subtraction 1C operation has two update opportunities, thereby avoiding the situation of "first adding 1C and then subtracting 2C" in the actual subtraction 1C operation, reducing the possibility of an error in the phase detection result of the phase detector, thereby avoiding the situation where the subtraction 1C operation that should be executed for one beat is executed multiple times due to an error in the phase detection result of the phase detector, so that the DLL circuit can be locked normally, and the normal operation of the system device is guaranteed.

[0079] In addition, the technical solution of the present invention can add a step after completing the last step of subtracting 1C operation, so that there are two update opportunities in the original first step of fine-tuning operation (for example, +4F operation), further reducing the possibility of error in the phase detection result of the phase detector, which is more conducive to achieving rapid locking of the DLL circuit.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A delay phase-locked loop circuit, comprising a controllable delay chain and a control circuit, wherein the controllable delay chain comprises a coarse adjustment delay chain and a fine adjustment delay chain, wherein the coarse adjustment delay chain is used to output a first clock and a second clock with a phase difference of 1C to the fine adjustment delay chain, wherein 1C is a unit coarse adjustment step length; characterized in that: The control circuit is used to output a coarse adjustment code to control the delay of the coarse adjustment delay chain and output a fine adjustment code to control the delay of the fine adjustment delay chain, and implement a 1C-subtraction operation of the output of the fine adjustment delay chain, wherein when performing the first step of the 1C-subtraction operation of the output of the fine adjustment delay chain, the control circuit is further configured as follows: Outputting a second coarse adjustment code to the coarse adjustment delay chain in an initial state, and outputting a second fine adjustment code to the fine adjustment delay chain at the same time, so that the fine adjustment delay chain selects the second clock output; When the first update timing is reached, the second fine adjustment code is kept output unchanged, so that the fine adjustment delay chain still selects the second clock output, and at the same time, a first coarse adjustment code different from the second coarse adjustment code is output to the coarse adjustment delay chain to perform a 2C subtraction operation on the first clock; When the second update timing is reached, a first fine adjustment code different from the second fine adjustment code is output to the fine adjustment delay chain, so that the fine adjustment delay chain selects the first clock output to implement the first step minus 1C operation of the output of the fine adjustment delay chain.

2. The delay phase-locked loop circuit according to claim 1, characterized in that: The first fine adjustment code is the minimum value of all fine adjustment codes that can be output by the control circuit, and the second fine adjustment code is the maximum value of all fine adjustment codes that can be output by the control circuit.

3. The delay phase-locked loop circuit according to claim 1, characterized in that: The control circuit is further configured to: when the second update timing arrives, while outputting the first fine adjustment code, also output a zeroth coarse adjustment code different from the first coarse adjustment code to the coarse adjustment delay chain to perform a 2C subtraction operation on the second clock.

4. The delay phase-locked loop circuit as claimed in claim 3, characterized in that: The first coarse adjustment code is the second coarse adjustment code minus 1, and / or the zeroth coarse adjustment code is the first coarse adjustment code minus 1.

5. The delay phase-locked loop circuit according to any one of claims 1 to 4, characterized in that: The control circuit is also used to start fine-tuning the output of the fine-tuning delay chain after completing the last step of subtracting 1C from the output of the fine-tuning delay chain.

6. The delay phase-locked loop circuit as claimed in claim 5, characterized in that: When performing the first step of fine adjustment operation on the output of the fine adjustment delay chain, the control circuit is further configured to: In an initial state, outputting the zeroth coarse adjustment code to the coarse adjustment delay chain, and outputting the first fine adjustment code to the fine adjustment delay chain, so that the fine adjustment delay chain selects the first clock output; When the first update timing is reached, the first fine adjustment code is kept output unchanged, so that the fine adjustment delay chain still selects the first clock output, and the first coarse adjustment code is output to the coarse adjustment delay chain to perform a 2C operation on the second clock; When the second update timing is reached, the output of the first coarse adjustment code is kept unchanged, and a third fine adjustment code different from the first fine adjustment code is output to the fine adjustment delay chain, so that the fine adjustment delay chain performs a phase adjustment on its output according to the third fine adjustment code, so as to implement the first step of fine adjustment operation on the output of the fine adjustment delay chain.

7. The delay phase-locked loop circuit according to claim 6, characterized in that: After completing the first step of fine adjustment operation, the output of the fine adjustment delay chain is updated to the clock signal with the earlier phase between the first clock and the second clock.

8. The delay phase-locked loop circuit according to any one of claims 1 to 4 and 6 to 7, characterized in that: The control circuit comprises: a state stretching circuit, configured to generate a fine-tuning gating signal and a stretching control signal according to an original control signal and an update timing signal, wherein a first edge of the stretching control signal is aligned with a first edge of the original control signal, and a second edge of the stretching control signal is delayed relative to a second edge of the original control signal; and The fine tuning code control circuit is used to generate a fine tuning code control signal according to a fine tuning control clock and the fine tuning gating signal, wherein the fine tuning code control signal is used to freeze the fine tuning code.

9. The delay phase-locked loop circuit according to claim 8, characterized in that: The state widening circuit comprises: A first trigger, whose clock terminal is coupled to the update timing signal, whose input terminal is coupled to the original control signal, and whose output terminal outputs a delayed control signal with a delay relative to the original control signal; an XOR logic circuit, a first input terminal of which is coupled to the original control signal, a second input terminal of which is coupled to the delay control signal, and an output terminal of which outputs the fine-tuning gating signal; and A first AND logic circuit, wherein a first input terminal thereof is coupled to the original control signal, a second input terminal thereof is coupled to the delay control signal, and an output terminal thereof outputs the stretch control signal; And / or, the fine-tuning code control circuit includes a second AND logic circuit, a first input terminal of which is coupled to the fine-tuning gating signal, a second input terminal of which is coupled to the fine-tuning control clock, and an output terminal of which outputs the fine-tuning code control signal.

10. The delay phase-locked loop circuit according to any one of claims 1 to 4, 6 to 7 and 9, characterized in that: Also includes: A clock buffer circuit, whose input end is coupled to the output end of the fine-adjustment delay chain, and is used to convert the output of the fine-adjustment delay chain into an internal clock required for the operation of the internal circuit of the system device; A clock replica buffer circuit, whose input end is coupled to the output end of the fine-adjustment delay chain, and is used to delay the output of the fine-adjustment delay chain and output it as a feedback clock signal; A phase detector has one input end coupled to the input end of the controllable delay chain and another input end coupled to the output end of the replica clock buffer circuit, and is used to identify the phase difference between the external clock signal received by the controllable delay chain and the feedback clock signal, and output the phase detection result to the control circuit.

11. A system device, characterized in that: The invention comprises a delay locked loop circuit as claimed in any one of claims 1 to 10.

12. The system device according to claim 11, characterized in that: The system device is a memory chip, and the clock signal output by the delay phase-locked loop circuit is a data selection pulse signal of the memory chip. The delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal input to the memory chip and the data selection pulse signal until the external clock signal and the data selection pulse signal are phase-synchronized and locked.

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