Single-level c-ADC circuit structure based on double-voltage compression signal and single reference voltage comparison and sampling method thereof
By using a single-level LC-ADC circuit structure based on the comparison of a dual-voltage scaled signal and a single reference voltage, the balance between low power consumption and high resolution of event-driven analog-to-digital converters is solved, realizing efficient and low-power sparse signal acquisition, which is particularly suitable for efficient acquisition of sparse signals such as electrocardiogram signals.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QINGDAO TIANZHUO TECHNOLOGY HOLDINGS INVESTMENT CO LTD
- Filing Date
- 2024-12-23
- Publication Date
- 2026-06-02
AI Technical Summary
Existing event-driven analog-to-digital converters struggle to balance low power consumption and high resolution. The conflict between dynamic power consumption and resolution, the limitation of static power consumption, and the impact of level errors on resolution make it difficult to optimize existing architectures.
A single-level LC-ADC circuit structure based on the comparison of a dual-voltage scaled signal and a single reference voltage is adopted, including a dual-voltage scaler module, an adaptive quantization resolution logic module, and an on-chip single-voltage reference circuit. By adaptively adjusting the quantization step size and common-mode voltage, the quantization step size is dynamically adjusted to match the signal change rate, and multiple pulse signals are generated to improve sampling efficiency.
It achieves efficient and low-power sparse signal acquisition, improves effective resolution, and reduces total power consumption. It is particularly suitable for efficient acquisition of sparse signals such as ECG signals and supports long-term low-power operation.
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Figure CN119814036B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog-to-digital converters, and more specifically, to a single-level C-ADC circuit structure and its sampling method based on the comparison of a dual-voltage scaled signal with a single reference voltage. Background Technology
[0002] An analog-to-digital converter (ADC) is a crucial component in electronic systems that converts analog signals into digital signals. It is widely used in medical devices, smart sensors, and wearable devices. Traditional ADC technology is based on the Nyquist sampling theorem, requiring a sampling frequency at least twice the highest frequency of the signal. Many real-world signals, such as electrocardiogram (ECG) and electroencephalogram (EEG) signals, exhibit sparse characteristics, meaning they remain stationary for extended periods, experiencing drastic changes only at a few specific points in time.
[0003] Traditional ADC designs typically employ a time-based uniform sampling method, as shown in Figure 1. This method is inefficient when processing sparse signals, increasing unnecessary dynamic power consumption and generating a large amount of redundant data, leading to increased complexity in subsequent processing. Therefore, in recent years, an event-driven analog-to-digital converter (LC-ADC) has been proposed. It performs non-uniform sampling by detecting significant changes in the signal (such as crossing a preset level), as shown in Figure 2. Since this type of ADC does not require a sampling clock, the power consumption increase caused by the clock circuit can be avoided. Furthermore, because the action is only triggered when the signal undergoes a significant change, fewer samples may be generated when processing sparse signals, thus reducing the circuit's dynamic power consumption. The significantly reduced sample size, i.e., the amount of data, alleviates the pressure on subsequent data processing and data transmission. Therefore, in principle, event-driven ADCs are very suitable for low-power acquisition of sparse signals. In addition to lower power consumption, event-driven ADCs also have advantages such as relatively simple circuit structure and alias-free operation.
[0004] Although the mainstream architectures of existing LC-ADCs, such as the "Clockless Flash" architecture, dual floating-level architecture, and dual fixed-level architecture, have achieved a certain degree of power consumption reduction, they still have the following shortcomings:
[0005] 1. Conflict between dynamic power consumption and resolution: Dynamic power consumption increases sharply with the increase of resolution, making it difficult to optimize both at the same time.
[0006] 2. Static power consumption is limited: As a source of static power consumption, comparators are required in existing architectures at least twice, which limits the space for power consumption optimization.
[0007] 3. Level error affects resolution: In a dual fixed-level architecture, the quantization step size is directly affected by the level error, which causes the effective resolution to be limited by the level accuracy.
[0008] In summary, existing technologies struggle to achieve a balance between low power consumption and high resolution, necessitating a novel architecture to overcome these limitations. This architecture requires novel event-driven analog-to-digital converter circuit designs and novel event-driven sampling methods. Summary of the Invention
[0009] To address the aforementioned problems, this invention provides a single-level LC-ADC sampling method and its circuit structure based on the comparison of a dual-scaled signal with a single reference voltage. Through innovation in the sampling method, optimized design of key modules, and the introduction of an adaptive control strategy, efficient and low-power sparse signal acquisition is achieved, while simultaneously improving the effective resolution.
[0010] According to one aspect of the present invention, a single-level C-ADC circuit structure based on the comparison of a dual-voltage scaled signal with a single reference voltage is proposed, comprising:
[0011] The dual voltage scaler module receives the input signal from the analog-to-digital converter and generates a scaled signal V that synchronously scales the two input signals. P1 and V P2 And make them have the same scaling factor and a constant common-mode voltage V respectively. CM1 and V CM2 It also receives the output pulse waveform from the control module, which is used to scale the signal V. P1 and V P2 Perform a reset.
[0012] A three-input comparator module is used to scale the signal V. P1 and V P2 Simultaneously with the single-level reference voltage V REF The comparison is used to detect whether any scaled signal crosses the single-level reference voltage V from below or above. REF If it crosses, output the corresponding output pulse signal.
[0013] The control logic module receives the output signal from the comparator module and outputs the reset signal RESET and the outputs CH and CL of the analog-to-digital converter respectively through the XOR logic gate and the buffer circuit.
[0014] The adaptive quantization resolution logic module controls the quantization step size of the analog-to-digital converter by monitoring the interval between adjacent pulses of the reset signal RESET.
[0015] An on-chip single-voltage reference circuit is used to generate a stable reference voltage V.REF This ensures that the quantization step size is independent of the level error.
[0016] Preferably, the adaptive quantization resolution logic module uses a time-to-voltage converter to convert the time interval between adjacent pulses in the RESET signal into a corresponding voltage.
[0017] Preferably, a gain code generator is used to generate gain codes based on the output voltage value of the time-voltage converter to control the dual voltage scaler to adjust the quantization step size.
[0018] Preferably, the common-mode voltage difference of the scaled signal is calculated according to the following formula:
[0019] V CM1 = V REF +r·V STEP V CM2 = V REF -r·V STEP
[0020] Where r is the scaling factor, and V STEP It is the quantization step size.
[0021] Preferably, the switched capacitor array of the dual voltage scaler consists of multiple parallel basic unit capacitors, each with a capacitance value of C0. By controlling the number of control capacitors, fine scaling can be achieved, further optimizing the dynamic range of the quantization step size.
[0022] Preferably, the capacitor material of the dual voltage scaler is a low-temperature drift dielectric, and a temperature compensation network is introduced in the circuit design to ensure the stability of the scaled signal over a wide temperature range.
[0023] Preferably, the three-input comparator adopts a rail-to-rail input structure, which supports a wider range of input signals while ensuring normal operation at extremely low supply voltages (0.6V).
[0024] Preferably, the input terminals of the three-input comparator adopt a self-biased circuit design, eliminating the need for an external bias circuit, thereby further simplifying the design and reducing static power consumption.
[0025] According to another aspect of the present invention, a sampling method based on the above-described circuit structure is provided, comprising the following steps:
[0026] Dual voltage scalers generate synchronous scaling signal V P1 and V P2 .
[0027] Detect scaling signal V P1 and V P2 Whether it crosses the reference voltage VREF and generates an output pulse signal when it does.
[0028] A reset signal is generated synchronously with the output pulse signal, and V is set to... P1 and V P2 Reset to common-mode signal V respectively CM1 With V CM2 .
[0029] The quantization step size is dynamically adjusted to match the rate of change of the signal.
[0030] Preferably, the adaptive resolution control logic adjusts the quantization step size in the following manner:
[0031] Increase or decrease the common-mode voltage of the scaled signal;
[0032] Dynamically change the number of activated cell capacitors in the capacitor array;
[0033] Adjust the output voltage of the on-chip reference circuit.
[0034] Preferably, the sampling method supports the simultaneous processing of multiple crossover events of the input signal, generating multiple pulse signals, which are used to adjust the scaling signal and record the timestamp, respectively.
[0035] Preferably, when the sparse signal remains stable for a long time, the control logic module enters a low-power sleep mode and is only reactivated when a rapid change in the signal is detected, thereby further saving energy.
[0036] Compared with the prior art, the present invention has the following advantages:
[0037] 1) Traditional ADC designs typically use a single input signal compared to a fixed reference voltage. This invention, however, introduces a dual voltage scaler module to generate two scaled signals (VP1 and VP2) with the same scaling factor but different common-mode voltages, which are then compared to a single reference voltage VREF. This not only improves the flexibility of signal processing but also helps to enhance the effective resolution and sampling efficiency of the ADC, achieving an effective resolution of over 8.5 bits.
[0038] 2) By monitoring the interval between adjacent pulses of the RESET signal, the adaptive quantization resolution logic module can dynamically adjust the quantization step size of the ADC, enabling the ADC to adjust its performance in real time according to the rate of change of the input signal, thereby reducing power consumption while ensuring accuracy.
[0039] 3) The sampling method supports simultaneous processing of multiple crossover events of the input signal and generates multiple pulse signals, which are used to adjust the scaling signal and record the timestamp, respectively. This design not only improves the parallel processing capability of the ADC but also helps to achieve more accurate time synchronization and signal analysis.
[0040] 4) This invention not only improves the performance and flexibility of the ADC, but also achieves low-power and efficient signal processing. Total power consumption is reduced to the nanowatt level, supporting long-term low-power operation. The single-level comparator and on-chip reference circuit reduce the number of circuit modules. It is particularly suitable for the efficient acquisition of sparse signals such as ECG signals. Attached Figure Description
[0041] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0042] Figure 1 A diagram illustrating the sampling method of existing clock-driven analog-to-digital converters;
[0043] Figure 2 A diagram illustrating the sampling methods of existing event-driven analog-to-digital converters;
[0044] Figure 3 This is a circuit block diagram of an embodiment of the present invention;
[0045] Figure 4 This is a sampling diagram of the signal in an example of the present invention;
[0046] Figure 5 This is a circuit design diagram of a dual-voltage scaling module in a preferred embodiment of the present invention;
[0047] Figure 6 This is a circuit diagram of a three-input comparator design in a preferred embodiment of the present invention;
[0048] Figure 7 This is a circuit diagram of the adaptive quantization resolution module in a preferred embodiment of the present invention;
[0049] Figure 8 This is a circuit diagram of the control logic module in a preferred example of the present invention.
[0050] Figure 9 This is a flowchart of a sampling method according to an example of the present invention. Detailed Implementation
[0051] The embodiments of the present invention are described in detail below: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.
[0052] Example 1:
[0053] This embodiment describes in detail the ultra-low power event-driven analog-to-digital converter of the present invention, and its structural schematic diagram is shown below. Figure 3As shown, it includes: a dual-voltage scaling circuit, a three-input comparator circuit, an adaptive margin control circuit, a control logic circuit, and an on-chip single-voltage reference circuit.
[0054] The signal sampling diagram in this example is shown in Figure 4. The dual-voltage scaling circuit generates corresponding scaling signals VP1 and VP2 based on the input signal VIN. These two signals are used by a three-input comparator circuit to compare with the reference voltage VREF generated by the on-chip single-voltage reference circuit. When VP1 crosses VREF from above or VP2 crosses VREF from below, the three-input comparator is triggered, generating an output pulse signal on CL or CH respectively through the output control logic, and generating a reset signal RESET through an XOR logic gate, resetting VP1 and VP2 to common-mode voltages VCM1 and VCM2 respectively. The resolution of the entire analog-to-digital converter is adaptively controlled by the adaptive resolution control circuit according to the pulse interval of the RESET signal.
[0055] In this embodiment, the dual voltage scaler generates synchronous scaling signals VP1 and VP2 through two sets of switched capacitor arrays, and its core circuit is shown in Figure 5. Each set of switched capacitor arrays contains three types of capacitors C1, C2, and C3, which are dynamically adjusted through a multiplexer. By redistributing the charge through the switched capacitor arrays, the final quantization step size of the analog-to-digital converter is C3 / C1·VDD, where VDD is the power supply voltage. The value of the capacitor in capacitor array C3 can be controlled through the adaptive resolution control module, thereby controlling the quantization step size.
[0056] In a preferred embodiment, the three-input comparator simultaneously compares the scaled signals VP1 and VP2 with a single reference voltage VREF and outputs a cross-through event detection signal. Its core circuit is shown in Figure 6. This circuit employs a rail-to-rail input structure, supporting a wider input signal range. Furthermore, the input terminals utilize a self-biasing circuit, eliminating the need for an additional biasing module and further reducing static power consumption.
[0057] In a preferred embodiment, the adaptive quantization resolution logic module circuit diagram is shown in Figure 7. The frequency of the RESET signal is converted into voltage using two current sources and a capacitor, and the gain encoding is adjusted by a counter. Due to the difference in size between the two current sources and the capacitor, they can be used to detect the upper and lower limits of the RESET signal frequency, respectively.
[0058] Example 2:
[0059] This embodiment describes in detail the ultra-low power event-driven analog-to-digital converter sampling method of the present invention, and its operation flowchart is as follows: Figure 8 As shown, it includes the following steps:
[0060] S11: Generate scaling signals VP1 and VP2 based on the input analog-to-digital converter signal and the quantization step size.
[0061] S12: Wait for VP1 or VP2 to cross the single-level reference voltage VREF.
[0062] S13: When VP1 or VP2 crosses the single-level reference voltage VREF, output the sampling signal and generate the reset signal RESET; otherwise, return to step S12.
[0063] S14: Adjust the quantization step size according to the frequency of the RESET signal, and return to step S11.
[0064] The above specific embodiments further illustrate the technical solution and evaluation effect of the present invention. Those skilled in the art should understand that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A single-level C-ADC circuit structure based on the comparison of a dual-voltage scaled signal and a single reference voltage, characterized in that, include: The dual voltage scaler circuit module is used to receive the input signal from the input analog-to-digital converter and generate two scaled signals VP1 and VP2 that synchronously track the input signal. The scaled signals VP1 and VP2 have the same scaling rate and constant common-mode voltages VCM1 and VCM2, respectively, to achieve a quantization step size independent of the quantization level VREF. It also receives the output pulse waveform finally output by the control module to reset the scaled signals VP1 and VP2. The three-input comparator module is used to compare the scaling signals VP1 and VP2 simultaneously with the single-level reference voltage VREF to detect whether either scaling signal crosses the single-level reference voltage VREF from below or above, and outputs the corresponding output pulse signal when a crossing is detected. The control logic module is used to receive the output signal of the three-input comparator module, and output the reset signal RESET and the output CH and CL of the analog-to-digital converter respectively through the XOR logic gate and the buffer circuit to control the reset of the scaling signal; An adaptive quantization resolution logic module is used to control the quantization step size of the analog-to-digital converter by monitoring the adjacent pulse interval time of the reset signal RESET, so as to achieve adaptive quantization resolution. An on-chip single-voltage reference circuit is used to generate a stable reference voltage VREF to ensure that the quantization step size is independent of the level error.
2. The single-level C-ADC circuit structure as described in claim 1, characterized in that, The dual voltage scaler circuit module includes two fully symmetrical switched capacitor arrays and a set of switch control logic blocks.
3. The single-level C-ADC circuit structure as described in claim 2, characterized in that, The switched capacitor array consists of multiple parallel basic unit capacitors, each with a capacitance value of C0. The scaling rate is adjusted by controlling the number of control capacitors to ensure that there is a predetermined difference in the common-mode voltages of VP1 and VP2 to generate a specified quantization step size.
4. The single-level C-ADC circuit structure as described in claim 1, characterized in that, The adaptive quantization resolution logic module includes: A time-to-voltage converter is used to convert the time interval between adjacent pulses in the RESET signal into a corresponding voltage. A gain code generator is used to generate gain codes based on the output voltage value of the time-to-voltage converter in order to control the dual voltage scaler to adjust the quantization step size.
5. The single-level C-ADC circuit structure as described in claim 1, characterized in that, The common-mode voltage difference of the scaled signal is calculated according to the following formula: V CM1 = V REF -r·V STEP V CM2 = V REF -r·V STEP Where r is the scaling factor, and V STEP It is the quantization step size.
6. The single-level C-ADC circuit structure as described in claim 1, characterized in that, The capacitor material of the dual voltage scaler is a low-temperature drift dielectric.
7. The single-level C-ADC circuit structure as described in claim 1, characterized in that, The control logic module consists of a buffer and an XOR gate to generate a corresponding output pulse signal when an input signal is detected crossing the VREF.
8. A sampling method based on the single-level C-ADC circuit structure according to any one of claims 1-7, characterized in that, Includes the following steps: The dual voltage scaler module generates two scaled signals VP1 and VP2 that synchronously track the input signal, and the scaled signals VP1 and VP2 have the same scaling rate and maintain a constant common-mode voltage. The scaled signal is compared using a single reference voltage VREF to detect whether the scaled signal VP1 or VP2 crosses the reference voltage VREF, and an output pulse signal is generated when a crossover is detected. When generating the output pulse signal, a reset signal is generated synchronously, and the scaling signals VP1 and VP2 are reset to the common-mode signals VCM1 and VCM2 respectively; The quantization step size of the scaling signal is dynamically adjusted according to the rate of change of the input signal to achieve adaptive quantization resolution.
9. The sampling method as described in claim 8, characterized in that, The adjustment of the quantization step size is achieved through the following steps: The rate of change of the input signal is estimated using the pulse interval of the reset signal; A gain-coded signal is generated based on the rate of change; The quantization step size of the dual-scaling signal is adjusted based on the gain-encoded signal.
10. The sampling method according to any one of claims 8 to 9, wherein the comparison and reset loop between the scaled signal and the single reference voltage is automatically repeated after each change of the input signal by a quantization step, thereby achieving continuous sampling.