Signal acquisition circuit and device

Abstract

The invention relates to the technical field of signal transmission, in particular to a signal acquisition circuit and device, and the circuit comprises an amplification module, a comparison module, a logic module, a processing module and a power supply end. The input end A of the amplification module is used for being connected with a signal acquisition point, the output end of the amplification module is connected to the input end of the comparison module, the output end of the comparison module is connected to the input end of the logic module, the output end of the logic module is connected to the signal detection end of the processing module, and the signal detection end of the processing module is connected to the signal acquisition point. The power supply end is used for supplying power to the circuit. According to the invention, the signal acquisition is more accurate.

Description

Technical Field

[0001] The present application relates to the technical field of signal transmission, and in particular to a signal acquisition circuit and device. Background Art

[0002] In electronic technology, after the signal is collected, it cannot be directly received and processed by the processor. Instead, the collected signal needs to be converted to meet the processing requirements of the processor.

[0003] In the related art, the collected current signal is converted into a voltage signal, and then the voltage signal is transmitted to the processor so that the collected signal can be processed. However, when the current signal is converted into a voltage signal, the interference signal therein will also be converted, and the interference signal will be mixed with the required signal. The signal received by the processor contains the interference signal, resulting in inaccurate collected signals. Summary of the invention

[0004] In order to make signal acquisition more accurate, the present application provides a signal acquisition circuit and device.

[0005] In the first aspect, the present application provides a signal acquisition circuit that adopts the following technical solution: A signal acquisition circuit comprises an amplification module, a comparison module, a logic module, a processing module and a power supply terminal; The input end A of the amplification module is used to connect to the signal collection point, the output end of the amplification module is connected to the input end of the comparison module, the output end of the comparison module is connected to the input end of the logic module, the output end of the logic module is connected to the signal detection end of the processing module, and the power supply end is used to power the circuit.

[0006] By adopting the above technical solution, the amplification module amplifies the signal collected by the collection point, and then outputs the amplified signal to the comparison module. The comparison module compares the signal with the reference voltage to obtain a signal that meets the requirements, and transmits the signal that meets the requirements to the logic module. The logic module widens the square wave of the signal and then transmits it to the processing module. The processing module collects the number of square waves to achieve signal collection. Compared with the related art, the collection method of converting current into voltage can reduce interference and achieve high-precision signal collection.

[0007] Optionally, the power supply end includes a first power supply end and a second power supply end, the amplification module includes an operational amplifier U1, a resistor R2, a resistor R3, a resistor R4, a capacitor C0, a capacitor C1 and a capacitor C2, the inverting input end of the operational amplifier U1 is connected to the input end A of the amplification module, the in-phase input end of the operational amplifier U1 is connected to the resistor R4, the other end of the resistor R4 is connected to the ground end, the inverting input end of the operational amplifier U1 is also connected to the resistor R2, the other end of the resistor R2 is connected to the output end of the operational amplifier U1, and the inverting input end of the operational amplifier U1 is also connected to the ground end. The capacitor C0, the other end of the capacitor C0 is connected to the output end of the operational amplifier U1, the positive power supply end of the operational amplifier U1 is connected to the first power supply end, the positive power supply end of the operational amplifier U1 is also connected to the capacitor C1, the other end of the capacitor C1 is connected to the ground end, the negative power supply end of the operational amplifier U1 is connected to the second power supply end, the negative power supply end of the operational amplifier U1 is also connected to the capacitor C2, the other end of the capacitor C2 is connected to the ground end, the output end of the operational amplifier U1 is connected to the resistor R3, and the other end of the resistor R3 is connected to the output end of the amplification module.

[0008] By adopting the above technical solution, the collected signal is amplified, thereby facilitating subsequent signal processing.

[0009] Optionally, the comparison module includes a reference voltage submodule and a comparator U3, the output end of the reference voltage submodule is connected to the comparator U3, the output end of the comparator U3 is connected to the output end of the comparison module, and the output end of the reference voltage submodule is also connected to the processing module.

[0010] By adopting the above technical solution, the amplification module amplifies the signal, and then the comparator U3 compares the amplified signal with the reference voltage output by the reference voltage submodule, thereby obtaining and outputting a signal that meets the requirements, and can filter out interference signals to make the signal more accurate.

[0011] Optionally, the reference voltage submodule includes a voltage reference chip U2, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C13, a resistor R7, and a resistor R8, wherein pin 1 of the voltage reference chip U2 is suspended, pin 2 of the voltage reference chip U2 is connected to a third power supply terminal, pin 2 of the voltage reference chip U2 is also connected to the capacitor C13, and the other end of the capacitor C13 is connected to the ground terminal, pin 3 of the voltage reference chip U2 is short-circuited with pin 2 of the voltage reference chip U2, pin 3 of the voltage reference chip U2 is also connected to the capacitor C7, and the other end of the capacitor C7 is connected to the ground terminal, pin 4 of the voltage reference chip U2 is connected to the ground terminal, and pin 5 of the voltage reference chip U2 is short-circuited with pin 2 of the voltage reference chip U2. The pins are suspended, the 6th pin of the voltage reference chip U2 is connected to the resistor R7, and the other end of the resistor R7 is connected to the output end of the reference voltage submodule, the capacitor C10 is connected to the output end of the reference voltage submodule, and the other end of the capacitor C10 is connected to the ground end, the resistor R8 is connected to the output end of the reference voltage submodule, and the other end of the resistor R8 is connected to the ground end, the capacitor C8 is connected to the 6th pin of the voltage reference chip U2, and the other end of the capacitor C8 is connected to the ground end, the capacitor C9 is connected to the 6th pin of the voltage reference chip U2, and the other end of the capacitor C9 is connected to the ground end, the 7th pin of the voltage reference chip U2 is suspended, and the 8th pin of the voltage reference chip U2 is suspended.

[0012] By adopting the above technical solution, the voltage reference chip U2 outputs a stable voltage value, so that the comparator U3 can better filter out interference signals when performing comparison.

[0013] Optionally, the logic module includes a logic chip U4, a resistor R10, a resistor R14, a resistor R16, a capacitor C12, a diode D1, and a MOS tube Q7, wherein the 10th pin of the logic chip U4 is connected to the resistor R10, and the other end of the resistor R10 is connected to the input end of the logic module, the 10th pin of the logic chip U4 is also connected to the cathode end of the diode D1, and the anode end of the diode D1 is connected to the ground end, the 11th pin of the logic chip U4 is connected to the ground end, the 16th pin of the logic chip U4 is connected to the capacitor C12, and the other end of the capacitor C12 is connected to the ground end, and the logic Pin 16 of the logic chip U4 is also connected to the third power supply terminal, pin 5 of the logic chip U4, pin 6 of the logic chip U4 and pin 7 of the logic chip U4 are short-circuited, pin 5 of the logic chip U4 is connected to the gate of the MOS tube Q7, the source of the MOS tube Q7 is connected to the ground terminal, the drain of the MOS tube Q7 is connected to the resistor R16, the other end of the resistor R16 is connected to the fourth power supply terminal, the drain of the MOS tube Q7 is also connected to the output end of the logic module, one end of the resistor R14 is connected to the gate of the MOS tube Q7, and the other end of the resistor R14 is connected to the ground terminal.

[0014] By adopting the above technical solution, the square wave of the signal is widened, so that the processing module can count the square waves more accurately, that is, precise measurement is achieved.

[0015] In the second aspect, the present application provides a signal acquisition device that adopts the following technical solution: A signal acquisition device comprises a signal acquisition circuit as described in the first aspect.

[0016] In summary, the present application includes at least one of the following beneficial technical effects: The amplification module amplifies the signal collected by the collection point, and then outputs the amplified signal to the comparison module. The comparison module compares the signal with the reference voltage to obtain a signal that meets the requirements, and transmits the signal that meets the requirements to the logic module. The logic module widens the square wave of the signal and then transmits it to the processing module. The processing module collects the number of square waves to achieve signal collection. Compared with the related art, the collection method of converting current into voltage can reduce interference and achieve high-precision signal collection. The amplification module amplifies the signal, and then the comparator U3 compares the amplified signal with the reference voltage output by the reference voltage submodule, thereby obtaining and outputting a signal that meets the requirements, and can filter out interference signals to make the signal more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is a block diagram of the overall connection of this embodiment.

[0018] Figure 2 Schematic diagram of the circuit of the processing module in this embodiment.

[0019] Figure 3 Schematic diagram of the circuit of the amplification module in this embodiment.

[0020] Figure 4 4 is a circuit diagram of the comparison module of this embodiment.

[0021] Figure 5 Schematic diagram of the logic module of this embodiment.

[0022] Explanation of the reference numerals: 1. Amplification module; 2. Comparison module; 21. Reference voltage submodule; 3. Logic module; 4. Processing module. DETAILED DESCRIPTION

[0023] The following is combined with Figure 1-5 This application is described in further detail.

[0024] The present application embodiment discloses a signal acquisition circuit. Figure 1 A signal acquisition circuit includes an amplification module 1, a comparison module 2, a logic module 3, a processing module 4 and a power supply end. The input end A of the amplification module 1 is used to connect a signal acquisition point, the output end of the amplification module 1 is connected to the input end of the comparison module 2, the output end of the comparison module 2 is connected to the input end of the logic module 3, the output end of the logic module 3 is connected to the signal detection end of the processing module 4, and the power supply end is used to power the circuit.

[0025] The signal at the signal acquisition point is amplified by the amplification module 1 and then transmitted to the comparison module 2. The comparison module 2 uses its own reference voltage to compare with the amplified signal and transmits the signal that meets the requirements to the logic module 3. The logic module 3 widens the transmitted signal square wave and then outputs it to the processing module 4. The processing module 4 collects the number of square waves.

[0026] Reference Figure 2 , wherein the processing module includes a processing chip U5, and the processing chip U5 can be a microcontroller of model STM32F103RET6. The peripheral circuit of the processing chip U5 is shown in the figure, and will not be described here.

[0027] The power supply end includes a first power supply end, a second power supply end, a third power supply end and a fourth power supply end. The first power supply end is used to output +5V, the second power supply end is used to output -5V, the third power supply end is used to output +5V, and the fourth power supply end is used to output 3.3V. The first power supply end and the third power supply end have the same output voltage and the same label in the accompanying drawings. Both are labeled VDD+5V. The respective names are for clearer description. The second power supply end is labeled VDD-5V in the accompanying drawings, and the fourth power supply end is labeled VCC.

[0028] Reference Figure 3 The amplification module 1 includes an operational amplifier U1, a resistor R2, a resistor R3, a resistor R4, a capacitor C0, a capacitor C1 and a capacitor C2. The inverting input terminal of the operational amplifier U1 is connected to the input terminal A of the amplification module 1. The non-inverting input terminal of the operational amplifier U1 is connected to the resistor R4. The other end of the resistor R4 is connected to the ground terminal. The inverting input terminal of the operational amplifier U1 is also connected to the resistor R2. The other end of the resistor R2 is connected to the output terminal of the operational amplifier U1. The inverting input terminal of the operational amplifier U1 is also connected to the capacitor C0. The other end of the capacitor C0 is connected to the output end of the operational amplifier U1, the positive power supply end of the operational amplifier U1 is connected to the first power supply end, the positive power supply end of the operational amplifier U1 is also connected to the capacitor C1, the other end of the capacitor C1 is connected to the ground end, the negative power supply end of the operational amplifier U1 is connected to the second power supply end, the negative power supply end of the operational amplifier U1 is also connected to the capacitor C2, the other end of the capacitor C2 is connected to the ground end, the output end of the operational amplifier U1 is connected to the resistor R3, and the other end of the resistor R3 is connected to the output end of the amplification module 1.

[0029] The operational amplifier may be ADA4530.

[0030] Reference Figure 4 The comparison module 2 includes a reference voltage submodule 21 and a comparator U3. The output end of the reference voltage submodule 21 is connected to the comparator U3. The output end of the comparator U3 is connected to the output end of the comparison module 2. The output end of the reference voltage submodule 21 is also connected to the processing module 4, that is, the output end of the reference voltage submodule 21 is connected to the 20 pin of the processing chip.

[0031] Specifically, the reference voltage submodule 21 includes a voltage reference chip U2, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C13, a resistor R7, and a resistor R8. Pin 1 of the voltage reference chip U2 is suspended, and pin 2 of the voltage reference chip U2 is connected to a third power supply terminal. Pin 2 of the voltage reference chip U2 is also connected to capacitor C13, and the other end of capacitor C13 is connected to the ground terminal. Pin 3 of the voltage reference chip U2 is short-circuited with pin 2 of the voltage reference chip U2. Pin 3 of the voltage reference chip U2 is also connected to capacitor C7, and the other end of capacitor C7 is connected to the ground terminal. Pin 4 of the voltage reference chip U2 is connected to the ground terminal. Pin 5 of the voltage reference chip U2 is suspended. Pin 6 of chip U2 is connected to resistor R7, and the other end of resistor R7 is connected to the output end of the reference voltage submodule 21, that is, the other end of resistor R7 is connected to pin 3 of comparator U3, capacitor C10 is connected to the output end of the reference voltage submodule 21, and the other end of capacitor C10 is connected to the ground end, resistor R8 is connected to the output end of the reference voltage submodule 21, and the other end of resistor R8 is connected to the ground end, capacitor C8 is connected to pin 6 of voltage reference chip U2, and the other end of capacitor C8 is connected to the ground end, capacitor C9 is connected to pin 6 of voltage reference chip U2, and the other end of capacitor C9 is connected to the ground end, pin 7 of voltage reference chip U2 is suspended, and pin 8 of voltage reference chip U2 is suspended.

[0032] The voltage reference chip U2 may be a REF192 series chip.

[0033] Pin 1 of the comparator U3 is connected to the first power supply terminal, and pin 1 of the comparator U3 is also connected to a capacitor C11, the other end of the capacitor C11 is connected to the ground terminal, pin 2 of the comparator U3 is connected to the input terminal of the comparison module 2, that is, pin 2 of the comparator U3 is connected to the resistor R3, pin 3 of the comparator U3 is connected to the output terminal of the reference voltage submodule 21, pins 4 and 8 of the comparator U3 are suspended, pin 5 of the comparator is short-circuited with pin 6 of the comparator U3, pin 6 of the comparator U3 is connected to the ground terminal, and pin 7 of the comparator U3 is connected to the output terminal of the comparison module 2. A resistor R9 is also connected between pins 7 and 2 of the comparator U3.

[0034] Among them, the comparator U3 can use an amplifier chip of model MAX9109ESA, and the circuit built by using the amplifier integrated inside the amplifier chip can be used as a comparator.

[0035] Reference Figure 5, the logic module 3 includes a logic chip U4, a resistor R10, a resistor R14, a resistor R16, a capacitor C12, a diode D1, and a MOS tube Q7. Pin 10 of the logic chip U4 is connected to the resistor R10, and the other end of the resistor R10 is connected to the input end of the logic module 3, that is, the other end of the resistor R10 is connected to pin 7 of the comparator U3. Pin 10 of the logic chip U4 is also connected to the cathode end of the diode D1, and the anode end of the diode D1 is connected to the ground end. Pin 11 of the logic chip U4 is connected to the ground end. Pin 16 of the logic chip U4 is connected to the capacitor C12, and the other end of the capacitor C12 is connected to the ground end. , pin 16 of the logic chip U4 is also connected to the third power supply terminal, pin 5 of the logic chip U4, pin 6 of the logic chip U4 and pin 7 of the logic chip U4 are short-circuited, pin 5 of the logic chip U4 is connected to the gate of the MOS tube Q7, the source of the MOS tube Q7 is connected to the ground terminal, the drain of the MOS tube Q7 is connected to the resistor R16, the other end of the resistor R16 is connected to the fourth power supply terminal, the drain of the MOS tube Q7 is also connected to the output end of the logic module 3, that is, the drain of the MOS tube Q7 is connected to pin 14 of the processing chip, one end of the resistor R14 is connected to the gate of the MOS tube Q7, and the other end of the resistor R14 is connected to the ground terminal.

[0036] The logic chip U4 may be a gate circuit chip of model 74HC4040D.

[0037] The implementation principle of a signal acquisition circuit in an embodiment of the present application is as follows: an amplification module amplifies the signal at a signal acquisition point, and transmits the amplified signal to a comparator U3; a reference voltage submodule is used to provide a stable reference voltage for the comparator U3, and compares the amplified signal with the reference voltage; the comparator U3 outputs a signal that meets the requirements; then the logic chip U4 receives the signal transmitted by the comparator U3 to implement a square wave widening process; finally, the logic chip U4 transmits the signal to a processing chip, and the processing chip collects the number of square waves to implement signal acquisition.

[0038] The embodiment of the present application also discloses a signal acquisition device, which includes a signal acquisition circuit as described in the above embodiment.

[0039] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A signal acquisition circuit, characterized in that: It includes an amplification module, a comparison module, a logic module, a processing module and a power supply terminal; The input end A of the amplification module is used to connect to the signal collection point, the output end of the amplification module is connected to the input end of the comparison module, the output end of the comparison module is connected to the input end of the logic module, the output end of the logic module is connected to the signal detection end of the processing module, and the power supply end is used to power the circuit.

2. A signal acquisition circuit according to claim 1, characterized in that: The power supply end includes a first power supply end and a second power supply end, the amplification module includes an operational amplifier U1, a resistor R2, a resistor R3, a resistor R4, a capacitor C0, a capacitor C1 and a capacitor C2, the inverting input end of the operational amplifier U1 is connected to the input end A of the amplification module, the in-phase input end of the operational amplifier U1 is connected to the resistor R4, the other end of the resistor R4 is connected to the ground end, the inverting input end of the operational amplifier U1 is also connected to the resistor R2, the other end of the resistor R2 is connected to the output end of the operational amplifier U1, and the inverting input end of the operational amplifier U1 is also connected to the resistor R2. The capacitor C0 has a positive power supply terminal connected to the first power supply terminal, a positive power supply terminal connected to the capacitor C1, a negative power supply terminal connected to the second power supply terminal, a negative power supply terminal connected to the capacitor C2, a negative power supply terminal connected to the capacitor C2, a negative power supply terminal connected to the ground terminal, an output terminal of the operational amplifier U1 is connected to the resistor R3, and a positive power supply terminal connected to the capacitor C1.

3. A signal acquisition circuit according to claim 1 or 2, characterized in that: The comparison module includes a reference voltage submodule and a comparator U3, the output end of the reference voltage submodule is connected to the comparator U3, the output end of the comparator U3 is connected to the output end of the comparison module, and the output end of the reference voltage submodule is also connected to the processing module.

4. A signal acquisition circuit according to claim 3, characterized in that: The reference voltage submodule includes a voltage reference chip U2, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C13, a resistor R7, and a resistor R8. Pin 1 of the voltage reference chip U2 is suspended, pin 2 of the voltage reference chip U2 is connected to a third power supply terminal, pin 2 of the voltage reference chip U2 is also connected to the capacitor C13, the other end of the capacitor C13 is connected to the ground terminal, pin 3 of the voltage reference chip U2 is short-circuited with pin 2 of the voltage reference chip U2, pin 3 of the voltage reference chip U2 is also connected to the capacitor C7, the other end of the capacitor C7 is connected to the ground terminal, pin 4 of the voltage reference chip U2 is connected to the ground terminal, and pin 5 of the voltage reference chip U2 is short-circuited with pin 2 of the voltage reference chip U2. The 6th pin of the voltage reference chip U2 is connected to the resistor R7, and the other end of the resistor R7 is connected to the output end of the reference voltage submodule. The capacitor C10 is connected to the output end of the reference voltage submodule, and the other end of the capacitor C10 is connected to the ground. The resistor R8 is connected to the output end of the reference voltage submodule, and the other end of the resistor R8 is connected to the ground. The capacitor C8 is connected to the 6th pin of the voltage reference chip U2, and the other end of the capacitor C8 is connected to the ground. The capacitor C9 is connected to the 6th pin of the voltage reference chip U2, and the other end of the capacitor C9 is connected to the ground. The 7th pin of the voltage reference chip U2 is suspended, and the 8th pin of the voltage reference chip U2 is suspended.

5. The signal acquisition circuit according to claim 1, characterized in that: The logic module includes a logic chip U4, a resistor R10, a resistor R14, a resistor R16, a capacitor C12, a diode D1, and a MOS tube Q7. Pin 10 of the logic chip U4 is connected to the resistor R10, and the other end of the resistor R10 is connected to the input end of the logic module. Pin 10 of the logic chip U4 is also connected to the cathode end of the diode D1, and the anode end of the diode D1 is connected to the ground end. Pin 11 of the logic chip U4 is connected to the ground end. Pin 16 of the logic chip U4 is connected to the capacitor C12, and the other end of the capacitor C12 is connected to the ground end. Pin 16 of the logic chip U4 is also connected to the third power supply terminal, pin 5 of the logic chip U4, pin 6 of the logic chip U4 and pin 7 of the logic chip U4 are short-circuited, pin 5 of the logic chip U4 is connected to the gate of the MOS tube Q7, the source of the MOS tube Q7 is connected to the ground terminal, the drain of the MOS tube Q7 is connected to the resistor R16, the other end of the resistor R16 is connected to the fourth power supply terminal, the drain of the MOS tube Q7 is also connected to the output end of the logic module, one end of the resistor R14 is connected to the gate of the MOS tube Q7, and the other end of the resistor R14 is connected to the ground terminal.

6. A signal acquisition device, characterized in that: It comprises a signal acquisition circuit as described in any one of claims 1 to 5.

Images