Method for testing MII port data of Ethernet PHY transceiver chip

Abstract

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an Ethernet PHY transceiver chip MII port data testing method. Comprising the following steps: S1, electrifying an Ethernet PHY transceiver chip, configuring an MII mode and a data rate, and sending an Ethernet data packet through TXD [7: 0]; s2, ATE double-edge acquisition of RXDV and RXD [7: 0] is carried out; s3, the RXDV is processed, and the data length is obtained, wherein the data length is data; s4, processing the RXD bus data bit by bit to obtain an array RXDdata; and S5, extracting four arrays from the RXDdata array, and converting the four arrays into a two-bit hexadecimal number. According to the invention, the problem that the data received by the Ethernet PHY chip in various MII modes is difficult to test on an integrated circuit test system is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit testing, and in particular relates to a method for testing MII port data of an Ethernet PHY transceiver chip. Background Art

[0002] When the 10 / 100 / 1000Mbps Ethernet PHY transceiver chip is tested on the integrated circuit test system (ATE), the function of sending and receiving data based on the MII port of the inner or outer ring of the chip is the key test item. Depending on the rate, various modes such as MII10 / 100, GMII10 / 100 / 1000, and RGMII10 / 100 / 1000 will be tested.

[0003] The characteristics of MII data in each mode are: first, the output is unstable, which is manifested in that when the chip is powered on again, repeatedly tested, or tested at different temperatures, the RX signal output time point is uncertain and the offset is large, and there is no regularity in the offset; second, the data flow is large and as the data rate increases, the RX data width becomes smaller and the error becomes larger. This error will also change in each test, and there is also a phase drift between data bits, making it difficult to directly compare the data. However, conventional mass production integrated circuit test systems do not have Ethernet protocols and test software, which means that the data sent by TX is known, but the data received by RX, that is, the data to be tested, is difficult to test. Summary of the invention

[0004] The object of the present invention is to provide a method for testing MII port data of an Ethernet PHY transceiver chip, so as to solve the problem that it is difficult to test data received in various MII modes of an Ethernet PHY chip on an integrated circuit test system.

[0005] In order to solve the above technical problems, the present invention provides a method for testing MII port data of an Ethernet PHY transceiver chip, comprising the following steps:

[0006] Step S1: Power on the Ethernet PHY transceiver chip, configure the MII mode and data rate, and send Ethernet data packets through TXD[7:0];

[0007] Step S2: ATE double-edge samples RX_DV and RXD[7:0];

[0008] Step S3: Process RX_DV to obtain the data length as datalength;

[0009] Step S4: Process the RXD bus data bit by bit to obtain an array RXD_data;

[0010] Step S5: Extract 4 arrays from the RXD_data array and convert them into two-digit hexadecimal numbers. The 4 arrays are:

[0011] RXD_dataA=RXD_data[i]*16+RXD_data[i+2];

[0012] RXD_dataB=RXD_data[i+1]*16+RXD_data[i+3];

[0013] RXD_dataC=RXD_data[i+2]*16+RXD_data[i+4];

[0014] RXD_dataD=RXD_data[i+3]*16+RXD_data[i+5];

[0015] Step S6: Circularly search and compare RXD_DataA, RXD_DataB, RXD_DataC, and RXD_DataD bit by bit respectively, find out the data that is equal to the first bit of the TXD[7:0] data bus, combine it with the datalength calculated by RX_DV, use this bit as the first bit of the datalength, compare it bit by bit with the TXD[7:0] data for consistency, and feedback the number of comparison errors in each group. Among these four arrays, if there is one or more groups with completely correct comparison, it means that the data received by RXD[7:0] is correct and the chip test PASS. If there is no group with correct comparison, the chip test FAIL.

[0016] Preferably, the step S1 specifically includes: implementing a hardware structure for sending and receiving data of an Ethernet PHY transceiver chip on an integrated circuit test system, and configuring the Ethernet PHY transceiver chip so that the Ethernet PHY transceiver chip can operate in an MII mode of a corresponding rate, and sending a data signal to be tested at the TXD[7:0] port. The length of the data is based on the test requirements, and an Ethernet data packet signal is used to send the data to the Ethernet PHY transceiver chip in the form of binary code and high and low level signals, and the data stream of TXD[7:0] is simplified bit by bit from binary to two-digit hexadecimal numbers according to the data bus rules to shorten the data volume and facilitate interpretation and subsequent comparison.

[0017] Preferably, step S2 specifically includes: after waiting for microseconds after TX sends data, synchronously collecting RX_DV and RXD[7:0] using the digital signal acquisition function on the integrated circuit test system, and using double-edge sampling within each data bit width, that is, collecting two level signals.

[0018] Preferably, step S3 specifically includes: obtaining the number of acquisition points, and converting the acquired high-level signal "H" and low-level signal "L" into binary digital signals "1" and "0" respectively, extracting a set of data from each signal of RX_DV and RXD[7:0] to form a binary array, and performing data processing operations; processing the array acquired by RX_DV, cyclically searching for the bit position startbit in the array that changes from "0" to "1", and cyclically searching for the bit position stopbit in the array that changes from "1" to "0", and the data length of RXD[7:0] to be tested is datalength=stopbit-startbit.

[0019] Preferably, the step S4 specifically includes: simplifying the 8 array data of RXD[7:0], performing base conversion processing bit by bit, converting the 8-bit data bus into an intuitive decimal number, and performing processing and calculation according to the following formula:

[0020] RXD_data=RXD[7][i]*128+RXD[6][i]*64+RXD[5][i]*32+RXD[4][i]*16+RX D[3][i]*8+RXD[2][i]*4+RXD[1][i]*2+RXD[0][i]*1.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention is based on the digital signal acquisition function of the integrated circuit test system, and collects RX-related output signals (including clock signal RX_CLK, output valid signal RX_DV, and data signal RXD[7:0]). It is impossible to use the traditional method of directly running the function vector and comparing with the expected time point for testing, because the expected time point is fixed; the present invention can solve the problem of absolute time introduction, and deal with the non-fixed output time of MII. The entire data processing and algorithm do not need to consider too many timing issues. The output of the MII data port RXD[7:0] is marked by the RX_DV signal output being high level. When the RX_DV output is high level, each bit of RXD starts to output Ethernet data. This method uses a dynamic algorithm to process the RX_DV signal, and can find the interval where RX_DV is high level. Data comparison test is performed within this interval, which finds the position where the RXD[7:0] data needs to be compared.

[0023] 2. The present invention also solves the test problem of the 8-bit data of RXD[7:0] itself. As the data rate of 10 / 100 / 1000Mbps increases, the data width error will become larger and the data will become irregular. The conventional fixed sampling method cannot find one or more sampling points to ensure that all the 8 bits of data are correctly judged. The present invention performs double-edge sampling, i.e., data collection at two points, on each bit of the 8-bit data, and takes into account the error in the data width and the phase jitter between the data bits, and extracts these two points and the following two points bit by bit to form 4 arrays, which are compared with the data array sent by TXD[7:0], thereby realizing the test of the data.

[0024] 3. The method of the present invention is applicable to the MII port data reception and transmission test of various types of Ethernet PHY transceiver chips on an integrated circuit test system, and is applicable to three rates of 10Mbps, 100Mbps, and 1000Mbps and different MII modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention is a flow chart of a method for testing MII port data of an Ethernet PHY transceiver chip.

[0026] Figure 2 It is a schematic diagram of MII signal data transmission of the present invention.

[0027] Figure 3 It is a schematic diagram of dual-edge signal acquisition of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0029] like Figures 1 to 3 As shown, an example of the present invention provides an Ethernet PHY transceiver chip MII port data testing method, which collects and processes Ethernet PHY transceiver chip MII port data on an integrated circuit test system, parses valid RXD[7:0] data to be tested, and compares it with the data sent by TXD[7:0] to achieve the purpose of testing whether the chip receives data correctly.

[0030] The specific steps include:

[0031] The first step is to implement the hardware structure of chip data transmission and reception on the integrated circuit test system, and configure the chip so that the chip can work in the MII mode of the corresponding rate, and send the data signal to be tested at the TXD[7:0] port. The length of the data depends on the test requirements, usually a large number of Ethernet data packet signals, which are sent to the chip in the form of binary code, high and low level signals, and the data stream of TXD[7:0] is simplified from binary to two-digit hexadecimal numbers bit by bit according to the data bus rules to shorten the data volume and facilitate interpretation and subsequent comparison;

[0032] In the second step, after the microsecond wait after TX sends the data, the digital signal acquisition function is used on the integrated circuit test system to synchronously acquire RX_DV and RXD[7:0], and double-edge sampling is used within each data bit width range, that is, two level signals are acquired;

[0033] The third step is to obtain the number of acquisition points, and convert the acquired high-level signal "H" and low-level signal "L" into binary digital signals "1" and "0" respectively, extract a set of data from each signal of RX_DV and RXD[7:0] to form a binary array for data processing operations;

[0034] Step 4: Process the array collected by RX_DV, loop through the array to find the startbit bit that changes from "0" to "1", and loop through the array to find the stopbit bit that changes from "1" to "0". The length of the RXD[7:0] data to be tested is datalength=stopbit-startbit.

[0035] The fifth step is to simplify the 8 array data of RXD[7:0], perform base conversion bit by bit, convert the 8-bit data bus into an intuitive decimal number, and perform processing according to the formula: RXD_data = RXD[7][i]*128+RXD[6][i]*64+RXD[5][i]*32+RXD[4][i]*16+RXD[3][i]*8+RXD[2][i]*4+RXD[1][i]*2+RXD[0][i]*1;

[0036] Step 6: Extract 4 arrays from the RXD_data array and convert them into two-digit hexadecimal numbers, which are:

[0037] RXD_dataA=RXD_data[i]*16+RXD_data[i+2];

[0038] RXD_dataB=RXD_data[i+1]*16+RXD_data[i+3];

[0039] RXD_dataC=RXD_data[i+2]*16+RXD_data[i+4];

[0040] RXD_dataD=RXD_data[i+3]*16+RXD_data[i+5];

[0041] In the seventh step, RXD_DataA, RXD_DataB, RXD_DataC, and RXD_DataD are searched and compared bit by bit in a loop to find the data that is equal to the first bit of the TXD[7:0] data bus. Combined with the datalength calculated by RX_DV, this bit is used as the first bit of the datalength, and the consistency with the TXD[7:0] data is compared bit by bit. The number of comparison errors in each group is fed back. Among these four arrays, if there is one or more groups with completely correct comparisons, it means that the data received by RXD[7:0] is correct and the chip test PASS. If there is no group with correct comparisons, the chip test FAIL.

[0042] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for testing MII port data of an Ethernet PHY transceiver chip, characterized in that: The steps include: Step S1: Power on the Ethernet PHY transceiver chip, configure the MII mode and data rate, and send Ethernet data packets through TXD[7:0]; Step S2: ATE double-edge samples RX_DV and RXD[7:0]; Step S3: Process RX_DV to obtain the data length as datalength; Step S4: Process the RXD bus data bit by bit to obtain an array RXD_data; Step S5: Extract 4 arrays from the RXD_data array and convert them into two-digit hexadecimal numbers. The 4 arrays are: RXD_dataA=RXD_data[i]*16+RXD_data[i+2]; RXD_dataB=RXD_data[i+1]*16+RXD_data[i+3]; RXD_dataC=RXD_data[i+2]*16+RXD_data[i+4]; RXD_dataD=RXD_data[i+3]*16+RXD_data[i+5]; Step S6: Circularly search and compare RXD_DataA, RXD_DataB, RXD_DataC, and RXD_DataD bit by bit respectively, find out the data that is equal to the first bit of the TXD[7:0] data bus, combine it with the datalength calculated by RX_DV, use this bit as the first bit of the datalength, compare it bit by bit with the TXD[7:0] data for consistency, and feedback the number of comparison errors in each group. Among these four arrays, if there is one or more groups with completely correct comparison, it means that the data received by RXD[7:0] is correct and the chip test PASS. If there is no group with correct comparison, the chip test FAIL.

2. The method for testing the MII port data of an Ethernet PHY transceiver chip according to claim 1, wherein: The step S1 specifically includes: implementing a hardware structure for the Ethernet PHY transceiver chip to send and receive data on the integrated circuit test system, configuring the Ethernet PHY transceiver chip so that the Ethernet PHY transceiver chip can operate in the MII mode of the corresponding rate, and sending the data signal to be tested at the TXD[7:0] port. The length of the data is based on the test requirements, and the Ethernet data packet signal is used to send it to the Ethernet PHY transceiver chip in the form of binary code and high and low level signals, and the data stream of TXD[7:0] is simplified bit by bit from binary to two-digit hexadecimal numbers according to the data bus rules to shorten the data volume and facilitate interpretation and subsequent comparison.

3. The method for testing the MII port data of an Ethernet PHY transceiver chip as claimed in claim 1, characterized in that: The step S2 specifically includes: after waiting for microseconds after TX sends data, synchronously collecting RX_DV and RXD[7:0] using the digital signal collection function on the integrated circuit test system, and using double-edge sampling within each data bit width range, that is, collecting two level signals.

4. The method for testing the MII port data of an Ethernet PHY transceiver chip as claimed in claim 1, characterized in that: The step S3 specifically includes: obtaining the number of acquisition points, and converting the acquired high-level signal "H" and low-level signal "L" into binary digital signals "1" and "0" respectively, extracting a set of data from each signal of RX_DV and RXD[7:0] to form a binary array, and performing data processing operations; processing the array acquired by RX_DV, cyclically searching for the bit position startbit in the array that changes from "0" to "1", and cyclically searching for the bit position stopbit in the array that changes from "1" to "0", and the data length of RXD[7:0] to be tested is datalength=stopbit-startbit.

5. The method for testing the MII port data of an Ethernet PHY transceiver chip as claimed in claim 1, characterized in that: The step S4 specifically includes: simplifying the 8-bit array data of RXD[7:0], performing base conversion processing bit by bit, converting the 8-bit data bus into an intuitive decimal number, and performing processing and calculation according to the following formula: RXD_data=RXD[7][i]*128+RXD[6][i]*64+RXD[5][i]*32+RXD[4][i]*16+RX D[3][i]*8+RXD[2][i]*4+RXD[1][i]*2+RXD[0][i]*1.

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