HPLC (High Performance Liquid Chromatography) communication device and clock synchronization method

Abstract

The invention relates to an HPLC (High Performance Liquid Chromatography) communication device and a clock synchronization method. The device comprises a signal acquisition module, a main control module and a signal coupling module which are connected in sequence, the signal acquisition module comprises a signal band-pass filtering unit connected with a power line of a low-voltage power grid; the signal coupling module comprises a signal amplification unit connected with the signal band-pass filtering unit; signals processed by the signal band-pass filtering unit are amplified by the signal amplification unit and then are synchronously coupled into a power line of a voltage power grid through the signal coupling module on one hand, on the other hand, the signals are sent to the signal acquisition module, and the master control module of the slave node obtains a clock from the signals received by the signal acquisition module and synchronizes the clock to the clock of the slave node. Compared with the prior art, the method has the advantages that the clock synchronization signal is propagated in a lossless manner, the signal coverage range of each node is automatically expanded, and the synchronization precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to an HPLC communication device and a clock synchronization method. Background Art

[0002] Low-voltage power line high-speed carrier communication, referred to as HPLC, is a stable and reliable communication method with fast communication rate and secure data transmission, which can use power lines for data transmission. At present, low-voltage power line high-speed carrier communication (HPLC) technology is widely used for low-voltage power information collection in low-voltage areas, where information collection includes both power user power consumption information and power information collection of facilities such as branch boxes and charging piles. Intelligent devices at the low-voltage side of power distribution, low-voltage outgoing lines, low-voltage branch boxes, low-voltage meter boxes, charging piles, low-voltage photovoltaic users, etc., form the same communication network through HPLC communication devices to realize centralized data collection.

[0003] At present, various intelligent devices in low-voltage power grids use the application layer time synchronization solution of unified time synchronization by concentrators. Time synchronization adopts the master-slave mode. There is only one master node and multiple slave nodes in the same network. Both the master node and the slave node contain HPLC communication devices, through which a high-speed carrier communication network is established and clock synchronization is achieved. The slave node obtains the clock from the node at the upper level to synchronize, which can achieve second-level or sub-second-level time synchronization between network devices, but cannot achieve millisecond-level or even microsecond-level clock synchronization, and cannot meet the application requirements of high-precision time synchronization.

[0004] How to achieve higher-precision clock synchronization between HPLC communication devices has become a technical problem that needs to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide a HPLC communication device and a clock synchronization method in order to overcome the defects of the above-mentioned prior art.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] According to one aspect of the present invention, a communication device based on HPLC is provided, which includes a signal acquisition module, a main control module and a signal coupling module connected in sequence; the signal acquisition module includes a signal bandpass filtering unit connected to the power line of the low-voltage power grid; the signal coupling module includes a signal amplifying unit connected to the signal bandpass filtering unit; the signal processed by the signal bandpass filtering unit is amplified by the signal amplifying unit on the one hand, and then synchronously coupled into the power line of the high-voltage power grid through the signal coupling module, and on the other hand, is sent to the signal acquisition module, and the main control module of the slave node obtains the clock from the signal received from the signal acquisition module and synchronizes it to its own clock.

[0008] Preferably, the signal bandpass filtering unit performs bandpass filtering on the signal from the power line of the low-voltage power grid to obtain a high-frequency alternating signal of a set frequency. Preferably, the signal amplification unit is only used for the output signal of the signal bandpass filtering unit.

[0009] More preferably, the signal acquisition module sends the high-frequency alternating signal to the main control module, and the main control module of the slave node decodes the received high-frequency alternating signal into a digital signal, obtains valid clock information therefrom, and synchronizes the obtained valid clock to its own clock.

[0010] More preferably, a delay compensation mechanism is introduced in the decoding process, wherein the delay compensation includes sending delay, transmission delay and receiving delay.

[0011] Preferably, the main control module of the master node generates a clock synchronization signal at a fixed time interval, and encodes it according to the set data time width to generate a high-frequency alternating signal, which is amplified by the signal amplification unit and output to the signal coupling module.

[0012] Preferably, the device also includes an external interface connected to the main control module.

[0013] Preferably, the master node receives an external time synchronization signal through the external interface, triggering the main control module to start time synchronization;

[0014] The slave node provides a clock signal to the external application through the external interface, and the external application actively obtains the clock in the main control module through the external interface.

[0015] According to another aspect of the present invention, a clock synchronization method for an HPLC communication device is provided, the method comprising a time synchronization process from a node, specifically:

[0016] Step S201, from the node, the signal in the power line enters the signal acquisition module, and obtains a high-frequency alternating signal with a fixed frequency through a signal bandpass filtering unit;

[0017] Step S202, the high-frequency alternating signal is sent to the signal coupling module, amplified by the signal amplification module, and then coupled into the power line of the low-voltage power grid by the signal coupling module; the signal acquisition module sends the high-frequency alternating signal to the main control module at the same time, and the main control module decodes the received signal and introduces a delay compensation mechanism to obtain effective clock information from the translated digital signal, and synchronizes the obtained effective clock to its own clock;

[0018] Step S203: the main control module provides a clock signal to the external application, or the external application actively obtains the clock in the main control module.

[0019] Preferably, the method also includes a time synchronization process of the master node, specifically:

[0020] Step S101: The master node receives an external time synchronization signal, triggering the main control module to start time synchronization;

[0021] Step S102, the main control module generates a clock synchronization signal at a fixed time interval, encodes it according to the set data time width, generates a high-frequency alternating signal, and outputs it to the signal coupling module;

[0022] Step S103, the high-frequency alternating signal is first amplified by the signal amplification module, and then coupled into the power line of the low-voltage power grid by the signal coupling module.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1) In the present invention, after the power line signal is collected, a special clock synchronization channel is used for processing, that is, it is directly coupled into the power line after passing through the signal bandpass filtering unit and the signal amplifying unit, rather than the traditional method of coupling into the power line through the signal acquisition module, the main control module and then the signal coupling module. After the improvement, synchronous amplification is performed during the transmission process, which reduces the process of collection and main control module processing. Therefore, the clock synchronization signal can cover the entire low-voltage network losslessly and synchronously, greatly reducing the transmission time of the time synchronization signal, thereby improving the accuracy of time synchronization.

[0025] 2) In the present invention, the power line signal outputs a high-frequency alternating signal of a set frequency after passing through the signal bandpass filtering unit. Through high-frequency signal transmission, the error introduced by the clock signal during encoding is small, thereby improving the accuracy of clock synchronization.

[0026] 3) In the present invention, the main control module introduces a delay compensation mechanism when decoding the high-frequency alternating signal, so as to further improve the timing error.

[0027] 4) The main control module of the master node in the present invention generates a clock synchronization signal at a fixed time interval and encodes it according to the set data time width to generate a high-frequency alternating signal. It does not require a special clock signal and is simple to output to the outside.

[0028] 5) Add a signal amplification unit that only processes high-frequency alternating signals to the signal coupling module, automatically expand the signal coverage range, and further reduce the time synchronization time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of the slave node clock synchronization device in the present invention;

[0030] Figure 1 (a) is a schematic diagram of the structure of the master node clock synchronization device in the present invention;

[0031] Figure 2 This is a schematic diagram of the master node timing process in the present invention;

[0032] Figure 3 This is a schematic diagram of the slave node timing process in the present invention;

[0033] Figure 4 It is a schematic diagram of the conversion rules between digital signals and high-frequency alternating signals in the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] In view of the above problems, the present invention improves the existing HPLC communication device and realizes the synchronization of clock signals at the data link layer, so that different HPLC communication devices have millisecond-level clock accuracy.

[0036] This embodiment relates to a HPLC communication device, such as Figure 1 The device used as a slave node includes a signal acquisition module 1, a signal coupling module 2, a main control module 3 and an external interface 4.

[0037] The signal acquisition module 1 includes a signal bandpass filtering unit 11. After the signal from the power line of the low-voltage power grid enters the signal bandpass filtering unit 11 for bandpass filtering, it is used by the signal acquisition module 1 on the one hand, and is synchronously output to the signal coupling module 2 on the other hand.

[0038] The signal coupling module 2 includes a signal amplifying unit 21 used only for bandpass filtering, which is used to amplify the signal after bandpass filtering and then synchronously couple it into the power line of the low-voltage power grid through the signal coupling module 2, thereby realizing synchronous collection and amplification.

[0039] It should be noted that the existing signal coupling module 2 includes a signal amplifying unit, which is used to amplify the signal output by the main control module 3 and then couple it into the power line through the signal coupling module 2 .

[0040] The time synchronization adopts the master-slave mode. There is only one master node in the same network. The main control module 3 of the master node generates a clock synchronization signal at a fixed time interval. The signal includes a synchronization signal and a clock signal.

[0041] like Figure 1 (a) is a schematic diagram of the structure of the master node clock synchronization device, which differs from the master node clock synchronization device in that it does not include a signal bandpass filtering unit 11.

[0042] The main control module 3 of the master node converts the clock synchronization signal into a signal that can be coupled into the power line of the low-voltage power grid, and couples it into the power line of the low-voltage power grid through the signal coupling module 2. The signal conversion method includes but is not limited to amplitude modulation, frequency modulation and phase modulation.

[0043] The slave node receives a time synchronization signal coupled into the low-voltage power grid, obtains a fixed-band signal through the signal bandpass filter unit 11, and the bandpass filtered signal is enhanced by the signal amplification module 21, and synchronously coupled into the low-voltage power grid by the signal coupling module 2 to amplify the signal.

[0044] The slave node receives the time synchronization signal coupled into the low-voltage power grid and converts it back into a digital signal to obtain the time synchronized by the master node. After error compensation, it performs time synchronization or provides the clock to other modules for use.

[0045] This embodiment relates to a clock synchronization method for an HPLC communication device, including a time synchronization method for a master node and a time synchronization method for a slave node.

[0046] The process of master node synchronization is as follows: Figure 2 , including the following steps:

[0047] Step S101, the master node receives an external time synchronization signal through the external interface 4, and the main control module 3 synchronizes the clock of the HPLC communication device.

[0048] In step S102, the main control module 3 generates a digital signal including a synchronization signal and a clock signal at a fixed time interval, encodes it according to the agreed data time width (such as the data time width of 1 bit of data), encodes it into a digital signal with high and low changes, and converts the digital signal into an alternating high-frequency signal (hereinafter referred to as a high-frequency alternating signal), and outputs it to the signal coupling module 2.

[0049] Step S103, after the signal coupling module 2 receives the high-frequency alternating signal, the high-frequency alternating signal is first amplified by the signal amplifying module 21 and then coupled into the power line of the low-voltage power grid.

[0050] The process of slave node synchronization is as follows Figure 3 , including the following steps:

[0051] Step S201 : The signal in the power line enters the signal acquisition module 1 , and passes through the signal bandpass filter unit 11 to obtain a high-frequency alternating signal with a fixed frequency.

[0052] Step S202 : The high-frequency alternating signal is sent to the signal coupling module 2 .

[0053] Step S203, the high-frequency alternating signal is enhanced by the signal amplification module 21, and the signal coupling module 2 then couples the high-frequency alternating signal into the low-voltage power grid to amplify the signal.

[0054] In step S204, the signal acquisition module 1 provides the high-frequency alternating signal to the main control module 3 for acquisition. The main control module 3 decodes the signal after acquiring it, introduces a delay compensation mechanism during decoding, translates the high-frequency alternating signal into a digital signal, and obtains valid clock information therefrom, and synchronizes the obtained valid clock to its own clock.

[0055] In step S205 , the main control module 3 provides a clock signal to the external application through the external interface 4 , and the external application can also actively obtain the clock in the main control module through the external interface 4 .

[0056] Example 3

[0057] This embodiment relates to the application of a clock synchronization method for an HPLC communication module.

[0058] First, the main control module 3 periodically sends an 8-byte message, which includes a 6-byte second count value and a 2-byte millisecond count. When sending, these digital signals need to be converted into high-frequency alternating signals. For example, if the frequency of the high-frequency signal is 2MHz, the error that may be introduced by the high-frequency signal is sub-microsecond level, which has no effect on the overall error.

[0059] The conversion rules between digital signals and high-frequency alternating signals are as follows: Figure 4 As shown, when there is a high-frequency alternating signal, it indicates a high level of the digital signal; when there is no high-frequency alternating signal, it indicates a low level of the digital signal.

[0060] Since there is no signal in the frequency band of this high frequency in the power grid under normal circumstances, it is a digital low level.

[0061] It is stipulated that a pulse width of 1 microsecond represents one digital bit, and two high levels are used as synchronization bits of the data.

[0062] The time data transmitted in the network is the time point at which the synchronization bit starts.

[0063] After the high-frequency alternating signal is coupled into the low-voltage power grid, the slave node receives the signal, and after bandpass filtering, it is coupled into the low-voltage power grid again, playing the role of signal amplification.

[0064] The slave node converts the received clock synchronization signal into a digital signal, parses the time in the synchronization signal, corrects the time in the synchronization signal according to the sending delay, transmission delay and receiving delay, and synchronizes its own time.

[0065] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A HPLC communication device, comprising a signal acquisition module (1), a main control module (3) and a signal coupling module (2) connected in sequence; characterized in that: The signal acquisition module (1) comprises a signal bandpass filtering unit (11) connected to the power line of the low-voltage power grid; the signal coupling module (2) comprises a signal amplifying unit (21) connected to the signal bandpass filtering unit (11); the signal processed by the signal bandpass filtering unit (11) is amplified by the signal amplifying unit (21) and then synchronously coupled into the power line of the high-voltage power grid through the signal coupling module (2), and is sent to the signal acquisition module (1) on the other hand. The main control module (3) of the slave node obtains a clock from the signal received from the signal acquisition module (1) and synchronizes it with its own clock.

2. A HPLC communication device according to claim 1, characterized in that: The signal bandpass filtering unit (11) performs bandpass filtering on the signal coming from the power line of the low-voltage power grid to obtain a high-frequency alternating signal of a set frequency.

3. A HPLC communication device according to claim 1, characterized in that: The signal amplifying unit (21) is only used for the output signal of the signal bandpass filtering unit (11).

4. A HPLC communication device according to claim 2, characterized in that: The signal acquisition module (1) sends a high-frequency alternating signal to a main control module (3), and the main control module (3) of the slave node decodes the received high-frequency alternating signal into a digital signal, obtains effective clock information therefrom, and synchronizes the obtained effective clock to its own clock.

5. A HPLC communication device according to claim 4, characterized in that: A delay compensation mechanism is introduced in the decoding process, wherein the delay compensation includes sending delay, transmission delay and receiving delay.

6. A HPLC communication device according to claim 1, characterized in that: The main control module (3) of the master node generates a clock synchronization signal at a fixed time interval, and encodes it according to the set data time width to generate a high-frequency alternating signal, which is amplified by the signal amplification unit (21) and then output to the signal coupling module (2).

7. A HPLC communication device according to claim 1, characterized in that: The device also includes an external interface (4) connected to the main control module (3).

8. A HPLC communication device according to claim 7, characterized in that: The master node receives an external time synchronization signal through the external interface (4), triggering the main control module (3) to start time synchronization; The slave node provides a clock signal to an external application via the external interface (4), and the external application actively obtains the clock in the main control module (3) via the external interface (4).

9. A clock synchronization method using the HPLC communication device according to any one of claims 1 to 8, the method comprising a time synchronization process from a node, specifically: Step S201, from the node, the signal in the power line enters the signal acquisition module (1), and passes through the signal bandpass filter unit (11) to obtain a high-frequency alternating signal with a fixed frequency; Step S202, the high-frequency alternating signal is sent to the signal coupling module (2), amplified by the signal amplification module (21), and then coupled into the power line of the low-voltage power grid through the signal coupling module (2); the signal acquisition module (1) simultaneously sends the high-frequency alternating signal to the main control module (3), the main control module (3) decodes the received signal, and introduces a delay compensation mechanism to obtain effective clock information from the translated digital signal, and synchronizes the obtained effective clock to its own clock; Step S203, the main control module (3) provides a clock signal to the external application, or the external application actively obtains the clock in the main control module.

10. The method according to claim 9, characterized in that The method also includes a time synchronization process of the master node, specifically: Step S101, the master node receives an external time synchronization signal, triggering the main control module (3) to start time synchronization; Step S102, the main control module (3) generates a clock synchronization signal at a fixed time interval, encodes it according to the set data time width, generates a high-frequency alternating signal, and outputs it to the signal coupling module (2); Step S103, the high-frequency alternating signal is first amplified by the signal amplification module (21), and then coupled into the power line of the low-voltage power grid through the signal coupling module (2).

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