Energy storage converter control circuit

Abstract

The invention relates to the technical field of energy storage control, and discloses an energy storage converter control circuit, which comprises a first DSP controller, an FPGA processor and an ARM processor, and is characterized in that the first DSP controller is used for controlling the operation of an energy storage converter; the FPGA processor is connected with the first DSP controller and the ARM processor and used for processing communication data transmitted by the ARM processor and caching a processing result, the first DSP controller controls the operation of the energy storage converter based on the processing result, and the ARM processor is used for carrying out data interaction with a preset external management system and obtaining communication data of the preset external management system. According to the invention, a DSP + FPGA + ARM topological architecture is constructed, and the FPGA processor carries out data preprocessing, so that the real-time control performance of the first DSP controller is ensured, and the real-time performance of the control of the energy storage converter is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of energy storage control, and in particular to an energy storage converter control circuit. Background Art

[0002] At present, most controllers in the energy storage industry adopt the DSP+CPLD topology. In this topology, the DSP and CPLD are connected through the SPI interface. Affected by the SPI communication upper limit rate of the DSP control chip, the system data transmission efficiency is low.

[0003] The related technology proposes to adopt the FPGA+DSP+ARM topology architecture, but the DSP and ARM use the IPC mechanism combined with shared memory to realize the communication between the DSP and ARM. In this way, the ARM needs to process the communication message and write the corresponding data into the shared memory, and then the DSP processes the data in the shared memory. When the amount of data increases dramatically, the DSP is forced to process a large amount of data, which affects the real-time control performance of the DSP and reduces the real-time control of the energy storage converter. Summary of the invention

[0004] In view of this, the present invention provides an energy storage converter control circuit to solve or partially solve the technical problem of low real-time performance of energy storage converter control in the prior art.

[0005] The technical solution proposed by the present invention is as follows:

[0006] The present invention provides an energy storage converter control circuit, comprising a first DSP controller, an FPGA processor and an ARM processor; the first DSP controller is used to control the operation of the energy storage converter; the FPGA processor is connected to the first DSP controller and the ARM processor respectively, and is used to process communication data transmitted by the ARM processor and cache the processing results, and the first DSP controller controls the operation of the energy storage converter based on the processing results; the ARM processor is used to exchange data with a preset external management system and obtain the communication data of the preset external management system.

[0007] An energy storage converter control circuit of the present invention constructs a DSP+FPGA+ARM topology architecture by sequentially connecting a first DSP controller, an FPGA processor and an ARM processor, and utilizes the FPGA processor to communicate with the first DSP controller and the ARM processor respectively, thereby improving the communication reliability of the energy storage converter control circuit, and obtaining communication data of an external preset external management system through the ARM processor, and the communication data is transmitted by the ARM processor to the FPGA processor for processing. When the amount of data increases, the FPGA processor performs data preprocessing to ensure the real-time control performance of the first DSP controller, thereby improving the real-time performance of the energy storage converter control.

[0008] Optionally, the first DSP controller and the FPGA processor are connected via a first EMIF bus, the FPGA processor and the ARM processor are connected via a second EMIF bus, a dual-port RAM is provided inside the FPGA processor, and the FPGA processor implements data interaction between the first EMIF bus and the second EMIF bus via the dual-port RAM.

[0009] The first DSP controller and the ARM processor are connected through the first EMIF bus and the second EMIF bus, and a dual-port RAM is set inside the FPGA processor to realize data interaction, thereby improving the efficiency and reliability of data transmission. At the same time, the design of the dual-port RAM allows the FPGA to process data from two different sources at the same time, thereby enhancing the parallel processing capability of the system.

[0010] Optionally, the first DSP controller is connected to a first AD sampling circuit, which collects first preset information through the first AD sampling circuit and sends the first preset information to the FPGA processor; the FPGA processor is connected to a third AD sampling circuit, which collects third preset information through the third AD sampling circuit; and the FPGA processor implements sampling redundancy control based on the first preset information and the second preset information.

[0011] By connecting the first DSP controller and the FPGA processor to corresponding sampling circuits respectively, redundant sampling can be achieved, thereby improving the reliability and fault tolerance of the system.

[0012] Optionally, the energy storage inverter control circuit also includes a second DSP controller and a second ADC sampling circuit, the second DSP controller is respectively connected to the second AD sampling circuit and the first DSP controller, the second DSP controller is used to collect second preset information through the second AD sampling circuit and monitor the operating status of the first DSP controller, and determine whether to shut down the energy storage inverter based on the second preset information and the operating status control of the first DSP controller.

[0013] In this method, a second DSP controller and a second ADC sampling circuit are added to collect second preset information and monitor the operating status of the first DSP controller, providing an additional monitoring and control layer, which can shut down the energy storage inverter when necessary, thereby improving the safety of the system.

[0014] Optionally, the first DSP controller is connected to an IO interface circuit, and reads state information of the energy storage converter through the IO interface circuit to control the energy storage converter.

[0015] The first DSP controller controls the energy storage converter through the IO interface circuit, which reduces control delay and improves control accuracy.

[0016] Optionally, the energy storage converter control circuit further includes a first isolation circuit, and the first DSP controller is connected to a plurality of CAN communication buses via the first isolation circuit.

[0017] By providing the first isolation circuit, communication interference can be reduced and communication quality can be improved.

[0018] Optionally, the FPGA processor is connected to an SRAM storage module, a fan control circuit, a PWM control circuit and a parallel IO circuit, the parallel IO circuit is connected to the parallel circuit via a second isolation circuit, and the parallel circuit uses a 485 interface chip.

[0019] A variety of control circuits are connected through the FPGA processor, including SRAM storage module, fan control circuit, PWM control circuit and parallel IO circuit, which simplifies the circuit structure and improves the integration and efficiency of the control circuit. The parallel signal adopts 485 interface chip, which can realize the single-ended to differential function, improve the parallel transmission efficiency, and reduce the risk of parallel failure when the parallel transmission data volume is large.

[0020] Optionally, the ARM processor is connected with a FLASH storage module and a TF card.

[0021] This method can improve the storage efficiency and storage capacity of communication data and collected data.

[0022] Optionally, the energy storage converter control circuit further includes a third isolation circuit and a fourth isolation circuit, the ARM processor is connected to an indicator light and / or a display screen via the third isolation circuit, and the ARM processor is connected to a plurality of 485 interface chips and a plurality of CAN buses via the fourth isolation circuit.

[0023] In this way, the ARM processor connects the indicator light, display screen, 485 interface chip and CAN bus through the third isolation circuit and the fourth isolation circuit, which improves the safety of the energy storage inverter control circuit, prevents electrical interference and fault propagation, and at the same time increases the communication interface, thereby improving the flexibility and scalability of the energy storage inverter control circuit.

[0024] Optionally, the energy storage converter control circuit further includes a PHY chip and a high-frequency transformer, and the ARM processor is connected to a plurality of Ethernet interfaces through the PHY chip and the high-frequency transformer in turn, and performs data exchange with a preset external management system through the plurality of Ethernet interfaces.

[0025] By expanding several Ethernet channels through PHY chips and high-frequency transformers, network port redundant communication and ring network communication functions are supported, improving the communication reliability of the energy storage inverter control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly express the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a principle block diagram of an energy storage converter control circuit according to an embodiment of the present invention;

[0028] Figure 2 is a circuit schematic diagram of a second isolation circuit in an embodiment of the present invention;

[0029] Figure 3 1 is a circuit schematic diagram of a parallel IO circuit in an embodiment of the present invention;

[0030] Figure 4 The figure is a working flow chart of the energy storage converter control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be noted that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two elements, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] At present, the energy storage converter control circuit has the following problems:

[0036] 1. Most controllers in the energy storage industry use the DSP+CPLD topology. In this topology, the DSP and CPLD are connected through the SPI interface. Affected by the SPI communication upper limit rate of the DSP control chip, the system data transmission efficiency is low;

[0037] 2. Multi-machine parallel communication is realized by DSP, and parallel communication is realized through IO interface + CAN. The IO interface realizes carrier synchronization and power frequency synchronization functions, and CAN realizes parallel communication. When the amount of parallel transmission data is large, it will lead to the risk of parallel failure;

[0038] 3. In actual use, the communication board is connected to the control board through the CAN bus. Since the upper limit of the CAN bus communication is only 1M, when the amount of CAN bus communication data increases, it is easy to cause the DSP and ARM communication data to be lost, affecting the communication efficiency of the whole device;

[0039] 4. The device usually uses a single network port for external communication. In this way, for a multi-machine parallel system, once a network storm causes the network port communication to be interrupted, the energy storage converter cannot respond to the EMS system dispatch in time, resulting in a failure to receive the dispatch command and the device refusing to operate;

[0040] 5. For the fault recording function, due to the low reading and writing speed of the external FLASH, it takes a long time to complete the writing of the recording data under the fault state. Therefore, it is necessary to add more supporting capacitors to the hardware to ensure the delayed operation of the control circuit after the device fails and stops, which increases the hardware cost.

[0041] 6. Traditional AD sampling is implemented by the AD sampling module of the DSP controller. Due to the limited number of AD sampling channels, it is difficult to meet the redundant sampling requirements. The energy storage device has high reliability requirements, and inaccurate sampling will cause the device to falsely alarm or shut down.

[0042] In order to solve one of the above problems, an embodiment of the present invention provides an energy storage converter control circuit.

[0043] like Figure 1 As shown, the energy storage converter control circuit of the embodiment of the present invention includes:

[0044] A first DSP controller, an FPGA processor and an ARM processor; the first DSP controller is used to control the operation of the energy storage inverter; the FPGA processor is connected to the first DSP controller and the ARM processor respectively, and is used to process the communication data transmitted by the ARM processor and cache the processing results, and the first DSP controller controls the operation of the energy storage inverter based on the processing results; the ARM processor is used to exchange data with a preset external management system and obtain the communication data of the preset external management system.

[0045] Specifically, the first DSP controller is used to implement the control of the energy storage converter. In one example, the first DSP controller has the functions of signal sampling, DI status reading and DO output control for the energy storage converter and 3-way external CAN communication.

[0046] The FPGA processor can process the communication data transmitted by the ARM processor. At the same time, the FPGA processor can also be used to realize PWM control of the energy storage inverter, fan circuit control and fan status reading, parallel IO circuit control, etc.

[0047] Specifically, the preset external management system is the Energy Management System (EMS), and the ARM processor realizes data interaction between the energy storage inverter control circuit and the energy management system. In addition, the ARM processor can also realize display screen / indicator light drive control, two-way 485 external communication, and two-way CAN external communication.

[0048] In one example, the first DSP controller uses a C2000 series chip, the FPGA processor uses a lattice chip, and the ARM processor uses an NXP 1180 series chip.

[0049] An energy storage inverter control circuit according to an embodiment of the present invention constructs a DSP+FPGA+ARM topology architecture by sequentially connecting a first DSP controller, an FPGA processor, and an ARM processor, and utilizes the FPGA processor to communicate with the first DSP controller and the ARM processor respectively, thereby improving the communication reliability of the energy storage inverter control circuit, and obtaining communication data of an external preset external management system through the ARM processor, and the communication data is transmitted by the ARM processor to the FPGA processor for processing. When the amount of data increases, the FPGA processor performs data preprocessing to ensure the real-time control performance of the first DSP controller, thereby improving the real-time control of the energy storage inverter.

[0050] Furthermore, the first DSP controller and the FPGA processor are connected via a first EMIF bus, the FPGA processor and the ARM processor are connected via a second EMIF bus, a dual-port RAM is provided inside the FPGA processor, and the FPGA processor implements data interaction between the first EMIF bus and the second EMIF bus via the dual-port RAM.

[0051] The first DSP controller and the ARM processor are connected via the first EMIF bus and the second EMIF bus, and a dual-port RAM is set inside the FPGA processor to realize data interaction, thereby improving the efficiency and reliability of data transmission between the first DSP controller and the FPGA processor. At the same time, the design of the dual-port RAM allows the FPGA to process data from two different sources at the same time, thereby enhancing the parallel processing capability of the system.

[0052] In some embodiments, the first DSP controller is connected to a first AD sampling circuit, which collects first preset information through the first AD sampling circuit and sends the first preset information to the FPGA processor; the FPGA processor is connected to a third AD sampling circuit, which collects third preset information through the third AD sampling circuit; the FPGA processor implements sampling redundancy control based on the first preset information and the second preset information.

[0053] Exemplarily, the first preset information includes any one or any combination of the internal battery voltage of the acquisition device, the positive half-bus voltage, the negative half-bus voltage, the DC current, the inverter voltage, the relay midpoint voltage, the grid voltage, the inverter current, the grid current, the board power supply voltage, the IGBT temperature, the leakage current, the insulation resistance, the ambient temperature and the capacitor temperature.

[0054] The third preset information includes any one or any combination of analog quantities such as copper busbar temperature, inverter voltage, inverter current, etc.

[0055] The FPGA processor compares the first preset information and the third preset information with the preset values ​​respectively to determine whether the energy storage converter works normally, and then controls the start and stop of the energy storage converter.

[0056] In addition, the embodiment of the present invention realizes AD sampling redundant control by respectively connecting the first AD sampling circuit and the third AD sampling circuit through the cooperation of the first DSP controller and the FPGA processor. The first DSP controller adopts a chip-built-in AD sampling channel, and the FPGA processor adopts a parallel port external expansion AD chip to realize AD sampling channel expansion. This method improves the sampling accuracy and the reliability and fault tolerance of the energy storage inverter control circuit, and reduces the probability of false alarm or false shutdown of the device due to inaccurate sampling.

[0057] In some embodiments, the energy storage inverter control circuit also includes a second DSP controller and a second ADC sampling circuit. The second DSP controller is respectively connected to the second AD sampling circuit and the first DSP controller. The second DSP controller is used to collect second preset information through the second AD sampling circuit and monitor the operating status of the first DSP controller, and determine whether to shut down the energy storage inverter based on the second preset information and the operating status control of the first DSP controller.

[0058] Specifically, the second DSP controller is used to monitor the operating status of the first DSP controller, and realize the reading of key analog data through the second AD sampling circuit, thereby realizing the functional safety protection of the device;

[0059] The second AD sampling circuit is used to collect second preset information, which is any one or more of analog quantities such as internal leakage current, insulation impedance, and external grid voltage of the energy storage converter device.

[0060] The second DSP controller adopts C2000 series chips. The processing performance of the second DSP controller is weaker than that of the third DSP controller, and a lower-cost DSP chip can be adopted.

[0061] In this method, a second DSP controller and a second ADC sampling circuit are added to collect second preset information and monitor the operating status of the first DSP controller, providing an additional monitoring and control layer to realize the safe shutdown function of the energy storage inverter under a fault state, thereby improving the safety of the energy storage system.

[0062] In some embodiments, the first DSP controller is connected to an IO interface circuit, and the state information of the energy storage converter is read through the IO interface circuit to control the energy storage converter.

[0063] The IO interface circuit is used to realize the DI state reading and DO output control of the energy storage converter.

[0064] The first DSP controller controls the energy storage converter through the IO interface circuit, which reduces control delay and improves control accuracy.

[0065] Furthermore, the energy storage converter control circuit also includes a first isolation circuit, and the first DSP controller is connected to a plurality of CAN communication buses via the first isolation circuit.

[0066] The first isolation circuit uses a digital isolator to achieve signal isolation. The digital isolator includes but is not limited to electromagnetic isolation devices, capacitive isolation devices, etc. A CAN communication bus is connected behind the first isolation circuit to achieve external communication.

[0067] By providing the first isolation circuit, communication interference can be reduced and communication quality can be improved.

[0068] In some embodiments, the FPGA processor is connected to an SRAM storage module, a fan control circuit, a PWM control circuit, and a parallel IO circuit. The parallel IO circuit is connected to the parallel circuit through a second isolation circuit. The parallel circuit uses a 485 interface chip.

[0069] The SRAM storage module is used to realize the temporary storage of device fault recording or communication data and sampling data.

[0070] The FPGA processor controls the fan equipment in the energy storage system through the fan control circuit and realizes PWM control through the PWM control circuit.

[0071] The parallel IO circuit uses a 485 interface chip to convert single-ended signals to differential signals, improving the anti-interference ability of the parallel signal. The 485 interface chip uses an RJ45 interface to meet the system parallel requirements and has a low cost.

[0072] There are multiple second isolation circuits and parallel IO circuits, and the second isolation circuits and parallel IO circuits are connected one-to-one.

[0073] In one example, if Figure 2 and Figure 3 As shown, the input end of the second isolation circuit is connected to the IO interface brought out by the FPGA processor, the IO interface connected to the input end of each group of second isolation circuits includes 485_TX pin, 485_RX pin, 485_TX_EN pin and 485_RX_EN pin, and the output end of each group of second isolation circuits is connected to the 485 interface chip, and the fast reception and transmission of signals are realized through the 485 interface chip.

[0074] At the same time, the second isolation circuit and the parallel IO circuit can also realize parallel carrier synchronization and power frequency synchronization, and can achieve high-speed and large-capacity data transmission.

[0075] Specifically, two sets of second isolation circuits and parallel IO circuits are additionally provided to respectively realize parallel carrier synchronization and power frequency synchronization. In the parallel IO circuit for realizing parallel carrier synchronization, and Figure 2 The difference is that the IO interface connected to the input end of the second isolation circuit includes the CARR_TX pin, the CARR_TX_EN pin, the CARR_RX_EN pin and the CARR_RX pin. In the parallel IO circuit for realizing parallel power frequency synchronization, and Figure 2 The difference is that the IO interface connected to the input end of the second isolation circuit includes a SYN_TX pin, a SYN_TX_EN pin, a SYN_RX_EN and a SYN_RX pin.

[0076] The embodiment of the present invention utilizes an FPGA processor to connect a variety of control circuits, including an SRAM storage module, a fan control circuit, a PWM control circuit, and a parallel IO circuit, thereby simplifying the circuit structure and improving the integration and efficiency of the control circuit. The parallel signal adopts a 485 interface chip to realize a single-ended to differential function, realize parallel carrier synchronization and power frequency synchronization, improve parallel transmission efficiency, and reduce the risk of parallel failure when the amount of parallel transmission data is large.

[0077] In some embodiments, the ARM processor is connected to a FLASH storage module and a TF card.

[0078] Specifically, the ARM processor is expanded with one FLASH storage module and one TF card. The ARM processor and the FLASH storage module are connected via an SPI interface, and the ARM processor and the TF card are connected via an SDIO interface.

[0079] The fault recording data fed back by the energy storage inverter to the first DSP controller is sent to the ARM processor through the first EMIF bus, the FPGA processor and the second EMIF bus. The ARM processor quickly stores the recording data in the TF card through the SDIO interface and can be quickly cached through the FLASH storage module, thereby improving the efficiency of data transmission, reducing data storage time, and thereby reducing the supporting capacitor value, saving hardware costs.

[0080] Furthermore, the energy storage converter control circuit also includes a third isolation circuit and a fourth isolation circuit. The ARM processor is connected to an indicator light and / or a display screen through the third isolation circuit. The ARM processor is connected to several 485 interface chips and several CAN buses through the fourth isolation circuit.

[0081] The third isolation circuit and the fourth isolation circuit use digital isolators, including but not limited to electromagnetic isolation devices and capacitive isolation devices.

[0082] The ARM processor is connected to the indicator light, the display screen, the 485 interface chip and several CAN buses through the third isolation circuit and the fourth isolation circuit to realize communication with the peripherals of the energy storage system.

[0083] Furthermore, the ARM processor is also connected to a number of Ethernet interfaces through the PHY chip and the high-frequency transformer, and performs data exchange with a preset external management system through the number of Ethernet interfaces.

[0084] Specifically, the Ethernet interface is an RJ45 interface with two channels.

[0085] By expanding two Ethernet interfaces through the PHY chip and high-frequency transformer, the ARM processor supports network port redundant communication and ring network communication functions, improving the communication reliability of the energy storage inverter control circuit.

[0086] In some embodiments, the working process of the energy storage converter control circuit is as follows: Figure 4 shown.

[0087] Before the energy storage converter control circuit is operated, each controller including the first DSP controller, the second DSP controller, the FPGA processor and the ARM processor performs self-check in turn to determine whether each controller is normal. If any controller fails the self-check, the energy storage converter control circuit issues a fault warning and shuts down.

[0088] After the controller passes the self-test, it is necessary to detect the EMIF bus status. If the first EMIF bus or the second EMIF bus is abnormal, the energy storage converter control circuit issues a fault warning and shuts down.

[0089] If the EMIF bus is normal, data communication detection needs to be performed between the first DSP controller, the FPGA processor and the ARM processor.

[0090] After the data communication between controllers is completed, the status of each controller's peripherals is collected. If the peripheral status is abnormal, an alarm shutdown command must be executed; if the peripheral status is normal, the control system is operated, the fan, AD sampling, PWM control and external communication functions are started, and the energy storage inverter control circuit is operated according to the software setting program to achieve normal operation of the energy storage inverter.

[0091] Although example embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and modifications to these embodiments without departing from the spirit and defined scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. A control circuit for an energy storage converter, characterized in that: It includes a first DSP controller, an FPGA processor and an ARM processor; The first DSP controller is used to control the operation of the energy storage converter; The FPGA processor is connected to the first DSP controller and the ARM processor respectively, and is used to process the communication data transmitted by the ARM processor and cache the processing results, and the first DSP controller controls the operation of the energy storage converter based on the processing results; The ARM processor is used to perform data interaction with a preset external management system and obtain communication data of the preset external management system.

2. The energy storage converter control circuit according to claim 1, characterized in that: The first DSP controller and the FPGA processor are connected via a first EMIF bus, the FPGA processor and the ARM processor are connected via a second EMIF bus, a dual-port RAM is provided inside the FPGA processor, and the FPGA processor implements data interaction between the first EMIF bus and the second EMIF bus via the dual-port RAM.

3. The energy storage converter control circuit according to claim 1, characterized in that: The first DSP controller is connected to a first AD sampling circuit, and collects first preset information through the first AD sampling circuit and sends the first preset information to the FPGA processor; The FPGA processor is connected to a third AD sampling circuit, and the third preset information is collected through the third AD sampling circuit; The FPGA processor implements sampling redundancy control based on the first preset information and the second preset information.

4. The energy storage converter control circuit according to claim 1, characterized in that: The energy storage inverter control circuit also includes a second DSP controller and a second ADC sampling circuit. The second DSP controller is connected to the second AD sampling circuit and the first DSP controller respectively. The second DSP controller is used to collect second preset information through the second AD sampling circuit and monitor the operating status of the first DSP controller, and determine whether to shut down the energy storage inverter based on the second preset information and the operating status control of the first DSP controller.

5. The energy storage converter control circuit according to claim 1, characterized in that: The first DSP controller is connected to an IO interface circuit, through which the state information of the energy storage converter is read and the energy storage converter is controlled.

6. The energy storage converter control circuit according to claim 1, characterized in that: The energy storage converter control circuit also includes a first isolation circuit, and the first DSP controller is connected to a plurality of CAN communication buses via the first isolation circuit.

7. The energy storage converter control circuit according to claim 1, characterized in that: The FPGA processor is connected to an SRAM storage module, a fan control circuit, a PWM control circuit and a parallel IO circuit. The parallel IO circuit is connected to the parallel circuit through a second isolation circuit. The parallel circuit uses a 485 interface chip.

8. The energy storage converter control circuit according to claim 1, characterized in that: The ARM processor is connected with a FLASH storage module and a TF card.

9. The energy storage converter control circuit according to claim 1, characterized in that: The energy storage converter control circuit also includes a third isolation circuit and a fourth isolation circuit. The ARM processor is connected to an indicator light and / or a display screen through the third isolation circuit. The ARM processor is connected to several 485 interface chips and several CAN buses through the fourth isolation circuit.

10. The energy storage converter control circuit according to claim 9, characterized in that: The energy storage converter control circuit also includes a PHY chip and a high-frequency transformer. The ARM processor is connected to a plurality of Ethernet interfaces through the PHY chip and the high-frequency transformer in turn, and performs data exchange with the preset external management system through the plurality of Ethernet interfaces.

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