Clock buffering device, clock buffering method and data transmission system

Abstract

The invention discloses a clock buffer device, a clock buffer method and a data transmission system, the device is arranged between a data transmission layer and a physical layer of a sending end, and the device comprises a configuration module used for configuring a buffer clock period and synchronously transmitted redundant data corresponding to the buffer clock period; the monitoring module is used for monitoring whether the data transmission sending state of the data transmission layer is switched from an idle state to a data transmission starting state or not; the buffer module is used for sending corresponding synchronously transmitted redundant data to a receiving end in the buffer clock period before the effective data of the data transmission layer is sent; wherein the frequency of the buffer clock period is lower than that of a normal clock period for synchronously transmitting the effective data.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a clock buffering device and a clock buffering method, and a data transmission system. Background Art

[0002] For data transmission that is performed by clock-to-data synchronous transmission, when the data transmission signal changes from "idle" to "busy", that is, when the data transmission state switches from the idle state to the start data transmission state, due to the influence of inter-code interference during transmission, the waveform of the first few clock transition signals sent by the transmitter after the start transition will be seriously deformed. This causes a significant change in the duty cycle of the first few clock signals that start transitioning sampled by the IO of the receiving end, and the receiving end cannot recognize the corresponding clock, thus losing the transitions of these clock signals. Accordingly, the synchronously transmitted data sampled by this clock at the receiving end is erroneous.

[0003] To solve the above problems, it is currently proposed to add a decision feedback equalizer (DFE) module at the receiving end to reduce the impact of inter-symbol interference on the signal; or to use the feedforward equalizer (FFE) function at the transmitting end to reduce inter-symbol interference by changing the driving strength of the IO output from maintaining the level unchanged to suddenly starting to jump during signal transmission.

[0004] However, the above method needs to add a corresponding analog circuit in the storage device, which not only complicates the circuit design, but also increases the design area of ​​the chip IO of the storage device and also increases the power consumption of the chip. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a clock buffering device, a clock buffering method, and a data transmission system to solve the problem of inter-symbol interference in data transmission of a storage device.

[0006] In order to solve the above technical problems, this specification is implemented as follows: In a first aspect, a clock buffer device is provided, which is applied to a transmitting end, and the device is arranged between a data transmission layer and a physical layer of the transmitting end, and the device includes: A configuration module, used for configuring a buffer clock cycle and redundant data for synchronous transmission corresponding to the buffer clock cycle; A monitoring module, used for monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; A buffer module is used to send redundant data corresponding to synchronous transmission to a receiving end in the buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data.

[0007] In a second aspect, a clock buffer device is provided, which is applied to a receiving end, and the device is arranged between a physical layer and a data transmission layer of the receiving end, and the device includes: A configuration module, configured to configure a first quantity based on the quantity of redundant data synchronously transmitted during a buffer clock cycle; A monitoring module, used for monitoring whether the receiving data transmission state of the physical layer switches from an idle state to a data transmission start state; The buffer module is used to remove the first quantity of data received first from the data received by the transmitting end at the physical layer.

[0008] In a third aspect, a clock buffering method is provided, which is applied to a transmitting end, and the method includes: Configure the buffer clock period and the redundant data corresponding to the synchronous transmission of the buffer clock period; Monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; Before sending the valid data of the data transmission layer, redundant data corresponding to the synchronous transmission is sent to the receiving end in the buffer clock cycle; wherein the frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle for synchronously transmitting the valid data.

[0009] In a fourth aspect, a clock buffering method is provided, which is applied to a receiving end, and the method includes: configuring a first quantity based on the quantity of redundant data synchronously transmitted during the buffer clock cycle; Monitoring whether the receiving data transmission state of the physical layer switches from an idle state to a data transmission start state; Among the data received by the physical layer from the transmitting end, the first quantity of data received first is removed.

[0010] In a fifth aspect, a data transmission system is provided, including a transmitting end and a receiving end. The transmitting end, upon monitoring that the data transmission state of the data transmission layer of the transmitting end switches from an idle state to a data transmission start state, sends redundant data corresponding to synchronous transmission to the receiving end in a configured buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data; When the receiving end detects that the receiving data transmission state of the physical layer of the receiving end switches from an idle state to a data transmission start state, the receiving end removes data on the number of redundant data first received and transmitted synchronously with the buffer clock cycle from the data received by the physical layer at the sending end.

[0011] In an embodiment of the present application, a clock buffer device arranged between a data transmission layer and a physical layer at a transmitting end includes: a configuration module for configuring a buffer clock cycle and redundant data for synchronous transmission corresponding to the buffer clock cycle; a monitoring module for monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; a buffer module for sending redundant data corresponding to synchronous transmission to a receiving end in a buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data, thereby allowing the inter-code interference in data transmission to affect only the burst jump signals of the first few buffer clock cycles, thereby avoiding the loss of valid data due to inter-code interference, so that the sent valid data can be completely transmitted to the receiving end, so that the receiving end can accurately sample the valid data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a schematic diagram of an application scenario of a data transmission system according to an embodiment of the present application.

[0013] Figure 2 It is a structural block diagram of the data transmission system of an embodiment of the present application.

[0014] Figure 3 It is a waveform diagram of a data transmission signal according to an embodiment of the present application.

[0015] Figure 4 It is a waveform diagram of a data transmission signal according to another embodiment of the present application.

[0016] Figure 5 It is a flowchart of the clock buffering method of the first embodiment of the present application.

[0017] Figure 6 It is a flowchart of the clock buffering method of the second embodiment of the present application.

[0018] Figure 7 It is a structural block diagram of a clock buffer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. The numbering of the drawings in this application is only used to distinguish the various steps in the scheme, and is not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0020] In order to solve the problems existing in the prior art, the embodiments of the present application provide a clock buffering device, a clock buffering method, and a data transmission system. Figure 1 It is a schematic diagram of an application scenario of a data transmission system according to an embodiment of the present application.

[0021] The data transmission system of the embodiment of the present application is suitable for data transmission with clock and data synchronous transmission. The sending end 10 sends data to the receiving end 20 by clock and data synchronous transmission. Correspondingly, the receiving end 20 receives data by clock and data synchronous transmission.

[0022] In one embodiment, the main control chip and the storage particles in the target storage device are the sending end 10 and the receiving end 20 of each other. Figure 1 As shown, when the main control chip serves as a transmitting end 10 and the storage particle serves as a receiving end 20, the main control chip sends data of an external device (not shown in the figure) to the storage particle through a transmission line 30 between the input / output (IO) of the transmitting end 10 and the input / output (IO) of the receiving end 20, so that the external device writes data to the storage particle through the main control chip; or, when the storage particle serves as a transmitting end 10 and the main control chip serves as a receiving end 20, the storage particle sends internally stored data to the main control chip through the transmission line 30, so that the external device reads data from the storage particle through the main control chip.

[0023] Figure 2 It is a structural block diagram of a data transmission system according to an embodiment of the present application. In this embodiment, the data transmission system includes a transmitting end 10 and a receiving end 20. The clock buffer device 100 provided in the embodiment of the present application is applied to the transmitting end 10, and the clock buffer device 200 provided in the embodiment of the present application is applied to the receiving end 20.

[0024] For the clock buffer device 100 applied to the transmitter 10, Figure 2As shown, the clock buffer device 100 is arranged between the data transmission layer 12 and the physical layer 14 of the sending end 10, and the clock buffer device 100 includes: a configuration module 120, used to configure the buffer clock cycle and the redundant data of the synchronous transmission corresponding to the buffer clock cycle; a monitoring module 140, used to monitor whether the data transmission state of the data transmission layer switches from the idle state to the start data transmission state; a buffer module 160, used to send the redundant data corresponding to the synchronous transmission to the receiving end in the buffer clock cycle before sending the valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle of the synchronous transmission of the valid data.

[0025] Combination Figure 2 The data transmission layer 12 of the sending end 10 is used to perform protocol conversion on the signal sent to the receiving end 20, and the physical layer 14 of the sending end 10 is used to convert the signal after the protocol conversion between digital / analog signals.

[0026] Specifically, for example, in the case where the main control chip is used as the transmitting end 10 and the storage particle is used as the receiving end 20, the data transmission layer 12 of the transmitting end 10 is used to convert the data received from the external device into the protocol of the storage device, and the physical layer 14 of the transmitting end 10 converts the data after the protocol conversion from digital to analog signals, obtains the valid data of the analog signal and transmits it to the physical layer of the receiving end 20. Correspondingly, the physical layer 24 of the receiving end 20 converts the received analog signal into a digital signal, and the data transmission layer 22 of the receiving end 20 performs protocol conversion on the converted digital signal and then stores it.

[0027] For the case where the storage chip serves as the transmitting end 10 and the main control chip serves as the receiving end 20, the principle is the same as above and will not be repeated here.

[0028] In order to avoid the situation where the first one or more clock transition signals sent by the transmitter 10 after the start of the transition are severely deformed and lost due to inter-code interference during transmission, the configuration module 120 can buffer the clock cycle and the corresponding redundant data of the synchronous transmission, so that the buffer module 160 can send the corresponding redundant data of the synchronous transmission to the receiving end 20 according to the configured buffer clock cycle before sending the valid data of the data transmission layer 12.

[0029] The number and frequency of the buffer clock cycles configured by the configuration module 120 can be predetermined through experiments, and the number can be one or more, as long as the signal loss of the buffer clock cycle can be avoided. In this way, even if the first few buffer clock cycles jump suddenly, since the frequency of the first few buffer clock cycles is low, even if the buffer clock signal is deformed due to the influence of inter-code interference during transmission, it will not be serious enough to lose the buffer clock signal at the receiving end 20. That is, the number of buffer clock cycles received by the receiving end 20 is consistent with the number of buffer clock cycles sent by the sending end 10.

[0030] Optionally, the configuration module 120 is specifically used to: configure the number of the buffer clock cycles to be multiple; and configure the frequencies of multiple buffer clock cycles to be the same and lower than the frequency of the normal clock cycle, or configure the frequencies of multiple buffer clock cycles to gradually increase from low to high and the frequency of the highest buffer clock cycle to be lower than the frequency of the normal clock cycle.

[0031] For the case where the frequencies of multiple buffer clock cycles are gradually increased from low to high, for example, 2 buffer clock cycles are used, and the corresponding frequencies from low to high are 1 / 4 and 1 / 2 of the frequencies of normal clock cycles, respectively. Or, for example, 4 buffer clock cycles are used, and the corresponding frequencies from low to high are 1 / 8, 1 / 8, 1 / 4, and 1 / 2 of the frequencies of normal clock cycles, respectively. The frequency of the buffer clock cycle that jumps at the beginning is the lowest, and then increases successively, and the last buffer clock cycle is adjacent to the first normal clock cycle, and the frequency of the last buffer clock cycle is still lower than the frequency of the first normal clock cycle.

[0032] In the embodiment of the present application, the monitoring module 140 is required to monitor the transmission data transmission state of the data transmission layer 12 of the transmitting end 10, and monitor whether data transmission has started between the transmitting end 10 and the receiving end 20, that is, whether the transmission data transmission state of the data transmission layer 12 has switched from the idle state to the start data transmission state. If it is monitored that the transmission data transmission state switches from the idle state to the start data transmission state, data transmission between the transmitting end 10 and the receiving end 20 begins.

[0033] When the transmitting end 10 or the receiving end 20 is a different device, the monitoring module 140 performs different functions.

[0034] In one embodiment, the transmitting end 10 is the main control chip of the storage device, the receiving end 20 is the storage particle of the storage device, and the monitoring module 140 is specifically used to: when monitoring that the level of the transmission bus of the data transmission layer jumps from a constant first level value to a second level value, determine that the sending data transmission state of the data transmission layer switches from an idle state to a start data transmission state, and the second level value is different from the first level value.

[0035] In this embodiment, the monitoring function can be implemented by the main control chip, for example, by monitoring through a control unit on the main control chip. If it is monitored that the level on the transmission line 30 changes from maintaining the level unchanged (a constant first level value) to suddenly starting to jump (a second level value), it is determined that the sending data transmission state of the data transmission layer 12 of the transmitting end 10 is switched from the idle state to the starting data transmission state. For example, when the main control chip receives a write request from an external device, it is monitored that the sending data transmission state of the data transmission layer 12 of the transmitting end 10 is switched from the idle state to the starting data transmission state.

[0036] In another embodiment, the transmitting end 10 is a storage particle of a storage device, the receiving end 20 is a main control chip of the storage device, and the monitoring module 140 is specifically used to: upon receiving a read command sent by the main control chip in the multiple buffer clock cycles, determine that the data transmission state of the data transmission layer is switched from an idle state to a start data transmission state, and the read command carries the number of valid data read from the storage particle and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle.

[0037] In this embodiment, the storage particle, as the transmitting end 10, does not have the function of actively monitoring the data transmission state. If the storage particle needs to switch from the idle state to the data transmission state, the main control chip actively sends a read command to the storage particle when receiving a read request from an external device, so that the storage particle monitors the data transmission state of the data transmission layer from the idle state to the data transmission state based on the read command, reads the internally stored data and sends it to the main control chip.

[0038] As described above, the buffer module 160 is used to send redundant data corresponding to synchronous transmission to the receiving end in the buffer clock cycle before sending the valid data of the data transmission layer 12 .

[0039] Before the transmitting end 10 sends the valid data of the data transmission layer 12 to the receiving end, that is, before sending the data read / written by the external device, the buffer module 160 first synchronously transmits the corresponding redundant data to the receiving end 20 with the buffer clock cycle configured by the configuration module 120 to avoid the situation where the transition signals of the first one or more clocks sent by the transmitting end after the transition starts are seriously deformed and lost due to inter-code interference during transmission. The frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle used for synchronous transmission of valid data. By first synchronously transmitting the redundant data with the buffer clock cycle with a frequency lower than the normal clock cycle before synchronously transmitting the valid data in the normal clock cycle, the idle state can be made to jump from the level of the idle state to the level of the buffer clock cycle first, and then switch to the level of the normal clock cycle.

[0040] Therefore, compared with directly jumping from the level of the idle state to the level of the normal clock cycle, by introducing a buffer clock cycle with a frequency lower than the normal clock cycle, the level jump difference between adjacent clock cycles can be reduced, thereby avoiding the situation where the front clock signal sent by the transmitter 10 is lost due to waveform deformation caused by inter-code interference.

[0041] refer to Figure 3 In the example, before the transmitting end 10 sends the valid data D0, D1, D2, ... synchronously transmitted corresponding to the normal clock cycle, the buffer module 160 inserts the waveform of two additional buffer clock cycles on the clock transmission line, and inserts the redundant data of synchronous transmission, including N0, N1, N2, N3, on the data transmission line. The frequency of transmitting the redundant data in the buffer clock cycle is different from the frequency of transmitting the valid data in the normal clock cycle, and the frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle.

[0042] For an embodiment in which the transmitting end 10 is a main control chip of a storage device and the receiving end 20 is a storage particle of the storage device, the buffer module 160 is specifically used to: obtain redundant data corresponding to synchronous transmission in each buffer clock cycle based on the number of redundant data configured by the configuration module, and send the redundant data to the storage particle based on the frequency of each buffer clock cycle configured by the configuration module 120; after the redundant data corresponding to synchronous transmission in the multiple buffer clock cycles are sent, receive valid data from the data transmission layer and send it to the storage particle.

[0043] In the above embodiment, the number and frequency of the buffer clock cycles sent by the main control chip and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle can be configured by the configuration module 120 of the main control chip. Figure 2 First, the configuration module 120 configures the buffer clock cycle and the corresponding redundant data, and the monitoring module 140 monitors the data transmission state of the data transmission layer 12 of the main control chip of the sending end 10. When it is monitored that the sending data transmission state of the data transmission layer 12 switches from the idle state to the start data transmission state, the buffer module 160 adds the corresponding configured buffer clock cycle and the corresponding redundant data according to the configuration between the data transmission layer 12 and the physical layer 14 of the main control chip before the main control chip sends the valid data of the data transmission layer 12, and sends it to the storage particles of the receiving end 20 through the physical layer 14 and the transmission line 30 based on the frequency of each buffer clock cycle.

[0044] After the redundant data corresponding to the synchronous transmission of the configured multiple buffer clock cycles is sent, the valid data of the data transmission layer 12 is received and sent to the storage particles of the receiving end 20.

[0045] For an embodiment in which the sending end 10 is a storage particle of a storage device and the receiving end 20 is a main control chip of the storage device, the configuration module 120 configures multiple buffer clock cycles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle based on the read command; the buffer module 160 obtains the redundant data synchronously transmitted corresponding to each buffer clock cycle, and sends it to the main control chip based on the frequency of each buffer clock cycle; and after the redundant data synchronously transmitted corresponding to the multiple buffer clock cycles are sent, the valid data of the data transmission layer 12 is received and sent to the main control chip.

[0046] In the above embodiment, the number and frequency of the buffer clock cycles sent by the storage particles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle can be configured based on the read command sent by the main control chip.

[0047] The main control chip can send a read command to the storage particle based on the number and frequency of multiple buffer clock cycles configured in advance. The read command carries the number of valid data to be read from the storage particle and the number of redundant data corresponding to each buffer clock cycle for synchronous transmission. The storage particle can return the configured number of redundant data based on the read command sent by the main control chip. The main control chip sends a read command to the storage particle, and the storage particle returns the read command and the corresponding number of redundant data. After the redundant data corresponding to the synchronous transmission of the configured multiple buffer clock cycles is sent, the storage particle can receive the valid data of the data transmission layer 12 based on the number of valid data required by the read command and send it to the main control chip of the receiving end 20.

[0048] The corresponding working principle can be found in Figure 2 As the storage particle of the transmitting end 10, the monitoring module 140 first monitors the data transmission state of the data transmission layer 12 switching from the idle state to the data transmission state based on the read command, and then the configuration module 120 configures the buffer clock cycle and the corresponding redundant data based on the read command, and the buffer module 160 adds the corresponding configured buffer clock cycle and the corresponding redundant data between the data transmission layer 12 and the physical layer 14 of the storage particle according to the configuration before the storage particle sends the valid data of the data transmission layer 12, and sends it to the main control chip of the receiving end 20 through the physical layer 14 and the transmission line 30 based on the frequency of each buffer clock cycle.

[0049] For each of the above embodiments, the number of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles is determined by the main control chip, specifically including: determining the number of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles based on the number of the multiple buffer clock cycles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle; or determining the number of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles based on the sum of the frequencies of the multiple buffer clock cycles, the frequency of the normal clock cycle, and the number of valid data synchronously transmitted corresponding to a normal clock cycle.

[0050] In one embodiment, the number of redundant data synchronously transmitted corresponding to the plurality of buffer clock cycles is related to the number of buffer clock cycles and the number of redundant data synchronously transmitted in each buffer clock cycle. Figure 3 For example, if the number of buffer clock cycles configured by the transmitter is 2, and the frequency of the redundant data synchronously transmitted in each buffer clock cycle is the same as the frequency of the buffer clock cycle, then the number of redundant data synchronously transmitted in each buffer clock cycle is 2, corresponding to Figure 3 The first buffer clock cycle synchronously transmits two redundant data N0 and N1, and the second buffer clock cycle thereafter synchronously transmits two redundant data N2 and N3. Each buffer clock cycle includes a high level and a low level, and each level synchronously transmits one redundant data.

[0051] In one embodiment, the number of redundant data synchronously transmitted corresponding to a plurality of buffer clock cycles can be determined based on the total frequency of a plurality of buffer clock cycles, the frequency of a normal clock cycle, and the number of valid data synchronously transmitted corresponding to a normal clock cycle. Figure 4 For example, the number of buffer clock cycles configured by the transmitter is still 2, and the frequencies of these 2 buffer clock cycles are 1 / 4 and 1 / 3 of the frequencies of the normal clock cycles respectively. If the number of valid data corresponding to a normal clock cycle to be synchronously transmitted is 2, such as valid data D0 and D1. Each normal clock cycle includes a high level and a low level, and each level synchronously transmits one valid data.

[0052] If the frequency of the redundant data synchronously transmitted in the buffer clock cycle is the same as the frequency of the normal clock cycle, then the total number of redundant data synchronously transmitted in these two buffer clock cycles is 7, that is, Figure 4 Because the redundant data is the data that the receiving end 20 needs to remove in the end, the amount and frequency of the redundant data can be determined in any way.

[0053] The buffer module 160 can obtain redundant data and transmit it synchronously in each buffer clock cycle. In one embodiment, the buffer module 160 obtains redundant data for synchronous transmission in each buffer clock cycle, including: determining the number of redundant data sent in the target buffer clock cycle; determining the data transmission width of each redundant data; based on the number of redundant data and the corresponding data transmission width, obtaining a corresponding number of serial data as redundant data for synchronous transmission in the target buffer clock cycle.

[0054] The target buffer clock cycle is any one of the multiple buffer clock cycles. After determining the amount of redundant data sent in the target buffer clock cycle, e.g. Figure 4 The first buffer clock cycle sends 4 redundant data N0~N3, and the data transmission width of each redundant data is determined respectively. If the data transmission width of each redundant data is 8 bits, 32 serial data can be obtained as redundant data. The serial data used as redundant data corresponding to multiple buffer clock cycles can be calculated according to the frequency and number of each buffer clock cycle and saved in a predetermined storage unit. When insertion is required, the corresponding number of serial data is obtained and sent according to the needs of the corresponding buffer clock cycle.

[0055] In an embodiment of the present application, a clock buffer device arranged between a data transmission layer and a physical layer at a transmitting end includes: a configuration module for configuring a buffer clock cycle and redundant data for synchronous transmission corresponding to the buffer clock cycle; a monitoring module for monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; a buffer module for sending redundant data corresponding to synchronous transmission to a receiving end in a buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data, thereby allowing the inter-code interference in data transmission to affect only the burst jump signals of the first few buffer clock cycles, thereby avoiding the loss of valid data due to inter-code interference, so that the sent valid data can be completely transmitted to the receiving end, so that the receiving end can accurately sample the valid data.

[0056] Optionally, the embodiment of the present application further provides a clock buffer device 200, Figure 2 In this embodiment, the clock buffer device 200 is arranged between the physical layer 24 and the data transmission layer 22 of the receiving end 20, and the clock buffer device 200 is applied to the receiving end 20.

[0057] like Figure 2As shown, the clock buffer device 200 includes: a configuration module 220, which is used to configure a first quantity based on the number of redundant data synchronously transmitted during the buffer clock cycle; a monitoring module 240, which is used to monitor whether the receiving data transmission state of the physical layer 24 switches from an idle state to a start data transmission state; and a buffer module 260, which is used to eliminate the first quantity of data received first from the data received by the transmitting end 10 at the physical layer 24.

[0058] In the embodiment of the present application, the receiving end 20 may be a storage device storage particle, and the sending end 10 may be a main control chip of the storage device. Alternatively, the receiving end 20 may be a main control chip of the storage device, and the sending end 10 may be a storage device storage particle.

[0059] The clock buffer device 200 of the receiving end 20 provided in the embodiment of this specification can achieve Figures 1 to 4 The clock buffer device 200 of the receiving end 20 in the embodiment of the present specification can implement the various processes implemented by the clock buffer device 200 of the transmitting end 10 provided in the embodiment of the present specification. Figures 1 to 4 In the embodiment of the present invention, the clock buffer device 100 of the transmitting end 10 implements various processes. To avoid repetition, they are not described here.

[0060] In one embodiment, when the main control chip is used as the receiving end 20 and the storage particles are used as the sending end 10, based on the description of the sending end in the above embodiment, it can be known that the configuration module 220 of the main control chip pre-configures the buffer clock cycle and the number of redundant data for the storage particles to send redundant data. Therefore, after the monitoring module 240 of the main control chip determines that the receiving data transmission state of the physical layer 24 switches from the idle state to the data transmission start state, the buffer module 260 of the main control chip first removes the redundant data transmitted synchronously with the configured buffer clock cycle received first from the data sent by the storage particles received by the physical layer 24.

[0061] After the storage particles send redundant data to the main control chip through the transmission line 30, the monitoring module 240 of the main control chip can monitor the received data transmission state stored in the physical layer 24 to switch from the idle state to the data transmission start state.

[0062] In one embodiment, optionally, the receiving end 20 is a storage particle of a storage device, the sending end 10 is a main control chip of the storage device, and the configuration module 220 is specifically used to: receive an initialization command sent by the main control chip, the initialization command carries the number of redundant data synchronously transmitted during the buffer clock cycle; and configure the number of data to be discarded based on the initialization command.

[0063] In this embodiment, as the storage particle of the receiving end 20, after the monitoring module 240 of the storage particle determines that the receiving data transmission state of the physical layer 24 switches from the idle state to the data transmission start state, the buffer module 260 of the storage particle removes the predetermined amount of data first received by the physical layer 24 according to the amount of data to be removed pre-configured by the configuration module 220 of the storage particle, that is, the amount of redundant data, before the physical layer 24 sends the received data to the data transmission layer 22. The main control chip can configure the buffer data of the storage particle, that is, the amount of redundant data, through the initialization command.

[0064] After the main control chip sends redundant data to the storage particle through the transmission line 30, the monitoring module 240 of the storage particle can monitor that the receiving data transmission state of the physical layer 24 switches from the idle state to the data transmission start state.

[0065] Combination Figure 3 After receiving the data, the receiving end 20 can remove the corresponding number of redundant data N0-N3 synchronously transmitted by the buffer clock cycle of the dotted part according to the configuration. Figure 4 After receiving the data, the receiving end 20 can remove the corresponding amount of redundant data transmitted synchronously by the buffer clock cycle of the dotted part according to the configuration. Figure 4 , the transmitting end 10 sends 7 redundant data on the corresponding data line within the two buffer clock cycles of the dotted line part, but since there are only 4 edges in the two buffer clock cycles, namely, two rising edges and two falling edges, the receiving end 20 can only sense the redundant data corresponding to the 4 edges, so the receiving end 20 samples 4 valid redundant data in the corresponding buffer clock cycle and is removed by the buffer module 260. Correspondingly, the configuration module 220 configures the first number according to the redundant number of synchronous transmissions that the receiving end 20 can actually sample in the corresponding buffer clock cycle.

[0066] In an embodiment of the present application, a clock buffer device arranged between a physical layer at a receiving end and a data transmission layer includes: a configuration module for configuring a first quantity based on the quantity of redundant data synchronously transmitted by a buffer clock cycle; a monitoring module for monitoring the receiving data transmission state of the physical layer switching from an idle state to a data transmission start state; and a buffer module for removing the first quantity of data received first from the data at the transmitting end received by the physical layer, thereby avoiding the loss of valid data due to inter-code interference during data transmission and ensuring accurate sampling of complete valid data.

[0067] Alternatively, if Figure 5 As shown, the first embodiment of the present application also provides a clock buffering method, which is applied to a transmitting end, and the method includes: Step 102, configuring a buffer clock cycle and redundant data for synchronous transmission corresponding to the buffer clock cycle; Step 104, monitoring whether the data transmission state of the data transmission layer is switched from an idle state to a data transmission start state; Step 106, before sending the valid data of the data transmission layer, sending the redundant data corresponding to the synchronous transmission to the receiving end in the buffer clock cycle; wherein the frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle of the synchronous transmission of the valid data.

[0068] The clock buffering method provided in the embodiment of the present application can achieve Figures 1 to 4 To avoid repetition, various processes implemented by the embodiment of the clock buffer device 100 applied to the transmitting end 10 are not described again here.

[0069] Alternatively, if Figure 6 As shown, the second embodiment of the present application further provides a clock buffering method, which is applied to a receiving end, and the method includes: Step 202, configuring a first quantity based on the quantity of redundant data synchronously transmitted in a buffer clock cycle; Step 204, monitoring whether the receiving data transmission state of the physical layer is switched from an idle state to a data transmission start state; Step 206: remove the first quantity of data received first from the data received by the transmitting end at the physical layer.

[0070] The clock buffering method provided in the embodiment of the present application can achieve Figures 1 to 4 To avoid repetition, various processes implemented by the embodiment of the clock buffer device 200 applied to the receiving end 20 will not be described again here.

[0071] Alternatively, if Figure 2 As shown, the embodiment of the present application further provides a data transmission system, including a transmitting end 10 and a receiving end 20, wherein the transmitting end 10, when monitoring that the transmitting data transmission state of the data transmission layer of the transmitting end switches from an idle state to a starting data transmission state, before sending valid data of the data transmission layer, sends redundant data corresponding to synchronous transmission to the receiving end in a configured buffer clock cycle; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data; When the receiving end 20 detects that the receiving data transmission state of the physical layer of the receiving end switches from an idle state to a data transmission start state, the receiving end 20 removes the data on the number of redundant data first received and synchronously transmitted by the buffer clock cycle from the data received by the physical layer at the sending end.

[0072] Alternatively, if Figure 7As shown, an embodiment of the present application also provides a clock buffering device 2000, including a processor 2400 and a memory 2200, and the memory 2200 stores programs or instructions that can be run on the processor 2400. When the program or instructions are executed by the processor 2400, the various steps of the above-mentioned clock buffering method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0073] The embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of any of the above-mentioned clock buffering method embodiments is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The readable storage medium includes a computer-readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0074] An embodiment of the present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. The computer program can be operated to enable a computer to implement the various processes of any of the above-mentioned clock buffering method embodiments when executed, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0075] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0076] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0077] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A clock buffer device, characterized in that: Applied to a transmitting end, the device is arranged between a data transmission layer and a physical layer of the transmitting end, and the device comprises: A configuration module, used for configuring a buffer clock cycle and redundant data for synchronous transmission corresponding to the buffer clock cycle; A monitoring module, used for monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; A buffer module is used to send redundant data corresponding to synchronous transmission to a receiving end in the buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data.

2. The device according to claim 1, characterized in that The configuration module is specifically used for: configuring the number of the buffer clock cycles to be multiple; and The frequencies of multiple buffer clock cycles are configured to be the same and lower than the frequency of the normal clock cycle, or the frequencies of multiple buffer clock cycles are configured to increase gradually from low to high and the frequency of the highest buffer clock cycle is lower than the frequency of the normal clock cycle.

3. The device according to claim 2, characterized in that The sending end is the main control chip of the storage device, and the receiving end is the storage particle of the storage device. The monitoring module is specifically used for: When it is monitored that the level of the transmission line of the data transmission layer jumps from a constant first level value to a second level value, it is determined that the sending data transmission state of the data transmission layer switches from an idle state to a start data transmission state, and the second level value is different from the first level value.

4. The device according to claim 3, characterized in that The buffer module is specifically used for: Based on the amount of redundant data configured by the configuration module, redundant data corresponding to synchronous transmission of each buffer clock cycle is acquired, and sent to the storage particle based on the frequency of each buffer clock cycle configured by the configuration module; After the redundant data synchronously transmitted corresponding to the multiple buffer clock cycles are sent, valid data of the data transmission layer is received and sent to the storage particle.

5. The device according to claim 2, characterized in that The sending end is a storage particle of a storage device, and the receiving end is a main control chip of the storage device. The monitoring module is specifically used for: Upon receiving a read command sent by the master control chip in the multiple buffer clock cycles, it is determined that the data transmission state of the data transmission layer is switched from an idle state to a start data transmission state, and the read command carries the number of valid data read from the storage particles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle.

6. The device according to claim 5, characterized in that The configuration module configures a plurality of buffer clock cycles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle based on the read command; The buffer module obtains the redundant data of synchronous transmission corresponding to each buffer clock cycle, and sends it to the main control chip based on the frequency of each buffer clock cycle; and after the redundant data of synchronous transmission corresponding to the multiple buffer clock cycles are sent, receives the valid data of the data transmission layer and sends it to the main control chip.

7. The device according to claim 4 or 6, characterized in that The number of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles is determined by the main control chip, specifically including: Determine the number of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles based on the number of the multiple buffer clock cycles and the number of redundant data synchronously transmitted corresponding to each buffer clock cycle; or The amount of redundant data synchronously transmitted corresponding to the multiple buffer clock cycles is determined based on the total frequency of the multiple buffer clock cycles, the frequency of the normal clock cycle, and the amount of valid data synchronously transmitted corresponding to one normal clock cycle.

8. The device according to claim 4 or 6, characterized in that The buffer module obtains redundant data corresponding to synchronous transmission of each buffer clock cycle, including: determining the amount of redundant data sent in a target buffer clock cycle; Determine the data transmission width of each redundant data; Based on the amount of the redundant data and the corresponding data transmission width, a corresponding amount of serial data is acquired as redundant data synchronously transmitted corresponding to the target buffer clock cycle.

9. A clock buffer device, characterized in that: Applied to a receiving end, the device is arranged between a physical layer and a data transmission layer of the receiving end, and the device comprises: A configuration module, configured to configure a first quantity based on the quantity of redundant data synchronously transmitted during a buffer clock cycle; A monitoring module, used for monitoring whether the receiving data transmission state of the physical layer switches from an idle state to a data transmission start state; The buffer module is used to remove the first quantity of data received first from the data received by the transmitting end at the physical layer.

10. The device according to claim 9, characterized in that The receiving end is a storage device's storage particle, and the sending end is the storage device's main control chip. The configuration module is specifically used for: Receiving an initialization command sent by the main control chip, wherein the initialization command carries the amount of redundant data synchronously transmitted during the buffer clock cycle; The first number is configured based on the initialization command.

11. A clock buffering method, characterized in that: Applied to the sending end, the method includes: Configure the buffer clock period and the redundant data corresponding to the synchronous transmission of the buffer clock period; Monitoring whether the data transmission state of the data transmission layer switches from an idle state to a data transmission start state; Before sending the valid data of the data transmission layer, redundant data corresponding to the synchronous transmission is sent to the receiving end in the buffer clock cycle; wherein the frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle for synchronously transmitting the valid data.

12. A clock buffering method, characterized in that: Applied to the receiving end, the method includes: configuring a first quantity based on the quantity of redundant data synchronously transmitted during the buffer clock cycle; Monitoring whether the receiving data transmission state of the physical layer switches from an idle state to a data transmission start state; Among the data received by the physical layer from the transmitting end, the first quantity of data received first is removed.

13. A data transmission system, characterized in that: Including the sending end and the receiving end, The transmitting end, upon monitoring that the data transmission state of the data transmission layer of the transmitting end switches from an idle state to a data transmission start state, sends redundant data corresponding to synchronous transmission to the receiving end in a configured buffer clock cycle before sending valid data of the data transmission layer; wherein the frequency of the buffer clock cycle is lower than the frequency of a normal clock cycle for synchronously transmitting the valid data; When the receiving end detects that the receiving data transmission state of the physical layer of the receiving end switches from an idle state to a data transmission start state, the receiving end removes data on the number of redundant data first received and transmitted synchronously with the buffer clock cycle from the data received by the physical layer at the sending end.

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