Solid-state imaging device

Abstract

A solid-state imaging device includes: a pixel section including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; an AD conversion unit that converts a pixel signal from the pixel unit into a digital signal; a holding circuit provided between the pixel section and the AD conversion section and holding a pixel signal; and a selection circuit selectively connecting the pixel portion or the holding circuit to the AD conversion portion to transfer a pixel signal from the pixel portion or the holding circuit to the AD conversion portion, the holding circuit including a first amplification transistor, the pixel portion further including first, second, and third transfer gate portions, a floating diffusion portion connected to the pixel portion via the first transfer gate portion, and a second transfer gate portion connected to the second transfer gate portion via the third transfer gate portion. And a capacitor and a second amplification transistor connected to a second end of the second transfer gate portion, the third transfer gate portion being disposed between the floating diffusion portion and a first end of the second transfer gate portion, a first end and a second end of the second amplification transistor being connected to the floating diffusion portion and the first amplification transistor, respectively, and outputting a pixel signal from the second end.

Description

[0001] This application is a divisional application of patent application No. 202280012900.0, with the filing date of January 20, 2022 and the invention name of “Solid-state imaging element”. Technical Field

[0002] The present disclosure relates to a solid-state imaging element. Background Art

[0003] There is a complementary metal oxide semiconductor (CMOS) image sensor (hereinafter, also referred to as CIS) that performs analog-to-digital (AD) conversion on an analog pixel signal by comparing the pixel signal with a linearly varying reference signal using a comparator and counting the time until the reference signal crosses the pixel signal. In order to expand the dynamic range of the comparator, the AD converter of the CIS can change the sensitivity or conversion efficiency of the pixel and perform AD conversion on the pixel charge multiple times.

[0004] Citation list

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-175345 Summary of the invention

[0007] Technical Problems to be Solved by the Invention

[0008] However, since AD ​​conversion requires a settling period to be performed after the voltage of the floating diffusion layer is stabilized, it takes a long time to perform a plurality of AD conversions while changing the sensitivity or conversion efficiency of the same pixel.

[0009] Therefore, there is provided a solid-state image pickup element capable of performing AD conversion on a pixel signal of a wide dynamic range in a short time.

[0010] Solutions to technical problems

[0011] According to one aspect of the present disclosure, a solid-state imaging device includes: a pixel unit, the pixel unit including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; an AD conversion unit, the AD conversion unit converts the pixel signal from the pixel unit into a digital signal; a first holding circuit, the first holding circuit is arranged between the pixel unit and the AD conversion unit and holds the pixel signal; a second holding circuit, the second holding circuit is arranged between the pixel unit and the AD conversion unit and holds the pixel signal; and a selection circuit, the selection circuit is capable of connecting either the first holding circuit and the second holding circuit to the AD conversion unit, and selectively transmitting the pixel signal held in the first holding circuit or the second holding circuit to the AD conversion unit.

[0012] The solid-state imaging device also includes a bypass signal line, which is arranged between the pixel unit and the AD conversion unit and transmits the pixel signal as is, and the selection circuit is capable of connecting any one of the first holding circuit, the second holding circuit and the bypass signal line to the AD conversion unit, and selectively transmitting the pixel signal held in the first holding circuit, the pixel signal held in the second holding circuit, or the pixel signal transmitted through the bypass signal line to the AD conversion unit.

[0013] The first holding circuit includes: a first capacitor, one end of which is connected to the pixel portion, and the first capacitor is capable of accumulating the pixel signal; and a first transistor, a gate of which is connected to the other end of the first capacitor, and a drain of which is connected to a current source and the selection circuit; and the second holding circuit includes: a second capacitor, one end of which is connected to the pixel portion, and the second capacitor is capable of accumulating the pixel signal; and a second transistor, a gate of which is connected to the other end of the second capacitor, and a drain of which is connected to a current source and the selection circuit.

[0014] The first holding circuit includes: a first switch provided between the first capacitor and the pixel portion;

[0015] A second switch connected between the drain of the first transistor and the one end of the first capacitor; and a third switch connected between the drain of the first transistor and the other end of the first capacitor; and the second holding circuit includes: a fourth switch arranged between the second capacitor and the pixel portion; a fifth switch connected between the drain of the second transistor and the one end of the second capacitor; and a sixth switch connected between the drain of the second transistor and the other end of the second capacitor.

[0016] When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch and the third switch enter a conductive state and the second switch is in a non-conductive state; when the first capacitor holds the pixel signal, the first switch and the third switch enter a non-conductive state and the second switch enters a conductive state; when the pixel signal is sampled from the pixel portion to the second capacitor, the fourth switch and the sixth switch enter a conductive state, and the fifth switch is in a non-conductive state; and when the second capacitor holds the pixel signal, the fourth switch and the sixth switch enter a non-conductive state, and the fifth switch enters a conductive state.

[0017] The first holding circuit and the second holding circuit sample the pixel signal at different times.

[0018] During a period in which the first holding circuit holds a first pixel signal in the pixel signal and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion unit, the second holding circuit samples a second pixel signal in the pixel signal; and during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion unit, the first holding circuit samples another pixel signal in the pixel signal.

[0019] The first holding circuit includes: a first capacitor, one end of which is connected to the pixel portion and the other end is connected to a reference voltage source, and the first capacitor is capable of accumulating the pixel signal; a first transistor, a gate of which is connected to the one end of the first capacitor and a source of which is connected to a current source and the selection circuit; and the second holding circuit includes: a second capacitor, one end of which is connected to the pixel portion and the other end is connected to the reference voltage source, and the second capacitor is capable of accumulating the pixel signal; and a second transistor, a gate of which is connected to the one end of the second capacitor and a source of which is connected to the current source and the selection circuit.

[0020] The first holding circuit includes a first switch provided between the one end of the first capacitor and the pixel portion; and the second holding circuit includes a second switch provided between the one end of the second capacitor and the pixel portion.

[0021] When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch enters a conductive state; when the first capacitor holds the pixel signal, the first switch enters a non-conductive state; when the pixel signal is sampled from the pixel portion to the second capacitor, the second switch enters a conductive state, and when the second capacitor holds the pixel signal, the second switch enters a non-conductive state.

[0022] The first capacitor and the second capacitor sample the pixel signal at different times.

[0023] During a period in which the first holding circuit holds a first pixel signal in the pixel signal and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion unit, the second holding circuit samples a second pixel signal in the pixel signal; and during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion unit, the first holding circuit samples another pixel signal in the pixel signal.

[0024] The solid-state imaging device also includes a negative capacitance circuit, which is connected to a first signal line, and the first signal line is connected between the pixel portion and the first holding circuit and the second holding circuit and transmits the pixel signal, and the negative capacitance circuit includes: an amplifier, the input terminal of the amplifier is connected to the first signal line; and a capacitor, the capacitor is connected between the input terminal and the output terminal of the amplifier.

[0025] Each pixel of the pixel portion includes a first photoelectric conversion element and a second photoelectric conversion element having different light receiving areas.

[0026] Each pixel of the pixel portion includes: a first floating diffusion layer and a second floating diffusion layer, each of the first floating diffusion layer and the second floating diffusion layer accumulating charges from the photoelectric conversion element; an amplifying transistor, the amplifying transistor outputting the pixel signal based on the potential of the first floating diffusion layer; and a seventh switch, the seventh switch being provided between the first floating diffusion layer and the second floating diffusion layer; when the seventh switch enters a non-conducting state, the amplifying transistor outputs the pixel signal based on the potential of the first floating diffusion layer, and when the seventh switch enters a conducting state, the amplifying transistor outputs the pixel signal based on the potential of a region coupling the first floating diffusion layer and the second floating diffusion layer.

[0027] The first holding circuit further includes a third transistor and an eighth switch connected in series between a power supply and a drain of the first transistor, and the second holding circuit further includes a fourth transistor and a ninth switch connected in series between the power supply and the drain of the second transistor.

[0028] The third transistor and the eighth switch are connected in parallel with the current source, and the fourth transistor and the ninth switch are connected in parallel with the current source.

[0029] The solid-state imaging device further includes a voltage generating circuit which applies a predetermined first voltage to the gates of the third transistor and the fourth transistor, and when the eighth switch is in an on state, the third transistor sets the drain of the first transistor to a clamping voltage corresponding to the first voltage, and when the ninth switch is in an on state, the fourth transistor sets the drain of the second transistor to the clamping voltage.

[0030] In the automatic zeroing operation in which the pixel signal held by the first holding circuit and compared in the AD conversion unit is equal to the reference signal, the eighth switch enters the on state, and in the automatic zeroing operation in which the pixel signal held by the second holding circuit and compared in the AD conversion unit is equal to the reference signal, the ninth switch enters the on state. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration example of a solid-state imaging element according to the first embodiment.

[0032] Figure 2 : is a conceptual diagram showing an example of a solid-state imaging element in which a semiconductor chip of a pixel portion and a semiconductor chip of a processing circuit are stacked.

[0033] Figure 3 is a circuit diagram showing a configuration example of a unit pixel arranged in a pixel array section.

[0034] Figure 4 It is the timing diagram of horizontal synchronization signal and driving signal.

[0035] Figure 5 It is the timing diagram of horizontal synchronization signal and driving signal.

[0036] Figure 6 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the first embodiment.

[0037] Figure 7 : is a timing chart showing an operation example of the SH section in the AD conversion operation.

[0038] Figure 8 : is a timing chart showing an operation example of the SH section in the AD conversion operation according to the first modification example.

[0039] Fig. 9 : is a timing chart showing an operation example of the SH section in the AD conversion operation according to the second modification example.

[0040] Fig.10 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the second embodiment.

[0041] Fig.11 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the third embodiment.

[0042] Fig.12 is a circuit diagram showing a configuration example of the SH portion according to the fourth embodiment.

[0043] Fig.13is a circuit diagram showing a configuration example of the SH portion according to the fifth embodiment.

[0044] Fig.14 is a circuit diagram showing a configuration example of the SH portion according to the sixth embodiment.

[0045] Fig.15 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0046] Fig.16 1 is a diagram showing an example of the installation position of the imaging unit.

[0047] Fig.17 is a block diagram showing a configuration example of a solid-state imaging device according to a seventh embodiment.

[0048] Fig.18 is a circuit diagram showing a configuration example of the SH portion according to the seventh embodiment.

[0049] Fig.19 : is a timing chart showing an operation example of detecting a reset signal by the first holding circuit and the comparator according to the seventh embodiment.

[0050] Fig. 20 is a timing chart showing the relationship between the voltage of the output voltage and the reference signal.

[0051] Fig.21 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the eighth embodiment.

[0052] Fig. 22 : is a timing chart showing an operation example of detecting a reset signal and a data signal by the first and second holding circuits and the comparator according to the eighth embodiment.

[0053] Fig.23 is a timing chart showing the relationship between the output voltage and the reference signal.

[0054] Fig.24 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the ninth embodiment.

[0055] Fig.25 is a circuit diagram showing a configuration example of a pixel, an SH portion, and a comparator according to the tenth embodiment.

[0056] Fig.26 is a circuit diagram showing a configuration example of the SH portion according to the eleventh embodiment. DETAILED DESCRIPTION

[0057] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual, and the proportions of the various parts, etc. are not necessarily the same as the actual ones. In the specification and the accompanying drawings, elements similar to those previously described with reference to the previously described drawings are represented by the same reference numerals, and their detailed descriptions are appropriately omitted.

[0058] (First embodiment)

[0059] Figure 1 1 is a block diagram showing a configuration example of a solid-state imaging device 100 according to the first embodiment. The solid-state imaging device 100 includes a pixel portion 101, a timing control circuit 102, a vertical scanning circuit 103, a digital-to-analog converter (DAC) 104, a sampling and holding (SH) portion 125, an analog-to-digital converter (ADC) group 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0060] In the pixel section 101, unit pixels (hereinafter, also simply referred to as pixels) are arranged in a matrix form, and each unit pixel includes a photoelectric conversion element that photoelectrically converts incident light into an amount of charge (pixel signal) corresponding to the amount of light of the incident light. Figure 2 The specific circuit structure of the unit pixel is described below. In addition, in the pixel unit 101, the pixel drive line 109 is wired for each row along the left-right direction in the figure (the pixel array direction of the pixel row / horizontal direction), and the vertical signal line 110 is wired for each column along the up-down direction in the figure (the pixel array direction of the pixel column / vertical direction) relative to the pixel array in the matrix. One end of the pixel drive line 109 is connected to the output end of the vertical scanning circuit 103 corresponding to the row. Note that although Figure 1 Although one pixel driving line 109 is shown for each pixel row, two or more pixel driving lines 109 may be provided for each pixel row.

[0061] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. The timing control circuit 102 performs drive control of the vertical scanning circuit 103, the DAC 104, the ADC group 105, the horizontal transfer scanning circuit 106, etc. based on various timing signals generated by the timing generator, etc., based on a control signal supplied from the outside.

[0062] The vertical scanning circuit 103 includes a shift register, an address decoder, etc. Although a specific configuration is not shown here, the vertical scanning circuit 103 includes a readout scanning system and a sweep scanning system.

[0063] The readout scanning system sequentially performs selective scanning on the unit pixels from which the signal is read out in units of rows. At the same time, the sweeping scanning system performs a sweeping scan on the readout row on which the readout scanning is performed by the readout scanning system at a time corresponding to the shutter speed before the readout scanning to sweep (reset) unnecessary charges from the photoelectric conversion elements of the unit pixels of the readout row. The unnecessary charges are swept (reset) by the sweeping scanning system, thereby performing the so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discharging the optical charge of the photoelectric conversion element and restarting exposure (starting to accumulate optical charge). The signal read out by the readout operation of the readout scanning system corresponds to the amount of light incident after the immediately preceding readout operation or the electronic shutter operation. Then, the period from the readout moment of the immediately preceding readout operation or the sweeping moment of the electronic shutter operation to the readout moment of the current readout operation is the optical charge accumulation time (exposure time) of the unit pixel.

[0064] Pixel signals (analog signals) output from unit pixels of a pixel row selectively scanned by the vertical scanning circuit 103 are supplied to the SH section 125 and the ADC group 105 via a plurality of vertical signal lines 110 corresponding to the columns.

[0065] The SH section 125 is provided between the pixel section 101 and the ADC group 105, receives a pixel signal via the vertical signal line 110, and holds the pixel signal. The SH section 125 outputs the held pixel signal to the comparator 121 of the ADC group 105 at a desired timing.

[0066] The DAC 104 as a reference signal generating unit generates a reference signal RAMP as a signal having a linearly changing ramp waveform, and supplies the reference signal RAMP to the ADC group 105. The DAC 104 is commonly connected to a plurality of comparators 121 via a reference signal line 114, and supplies the same reference signal RAMP to the plurality of comparators 121. The reference signal line 114 transmits the reference signal RAMP to the plurality of comparators 121.

[0067] The ADC group 105 includes a plurality of comparators 121, a plurality of counters 122, and a plurality of latch circuits 123. The ADC group 105 converts a pixel signal (analog signal) from the pixel portion 101 into a digital signal.

[0068] One comparator 121 , one counter 122 , and one latch circuit 123 are provided corresponding to the pixel columns of the pixel portion 101 , respectively, and constitute an ADC.

[0069] The comparator 121 compares the voltage of a signal obtained by adding a pixel signal output from each pixel and a reference signal RAMP through a capacitor with a predetermined reference voltage, and supplies an output signal indicating a comparison result to the counter 122 .

[0070] The counter 122 counts the time until the magnitude relationship between the pixel signal and the reference signal RAMP is reversed based on the output signal of the comparator 121. Thus, the analog pixel signal is converted into a digital pixel signal represented by the count value. The counter 122 supplies the count value to the latch circuit 123.

[0071] The latch circuit 123 holds the count value supplied from the counter 122. Also, the latch circuit 123 performs correlated double sampling (CDS) by taking a difference between a data signal count value corresponding to a pixel signal at a signal level and a reset signal count value corresponding to a pixel signal at a reset level.

[0072] The horizontal transfer scanning circuit 106 includes a shift register, an address decoder, etc., and sequentially performs selective scanning on the circuit portion corresponding to the pixel column of the ADC group 105. Through the selective scanning of the horizontal transfer scanning circuit 106, the digital pixel signal held in the latch circuit 123 is sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0073] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch circuit 123 , and supplies the amplified digital pixel signal to the signal processing circuit 108 .

[0074] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signal supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 corrects vertical line defects or dot defects, clamps the signal, or performs digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a subsequent device.

[0075] Notice, Figure 1 The solid-state imaging device 100 shown may be constructed as a whole as one semiconductor chip, or may be composed of a plurality of semiconductor chips. In the case where the solid-state imaging device 100 is constructed as a plurality of semiconductor chips, the pixel portion 101 and other processing circuits may be formed as separate semiconductor chips 511 and 512, and the semiconductor chips 511 and 512 may be stacked.

[0076] For example, Figure 2 1 is a conceptual diagram showing an example of a solid-state imaging device 100 in which a semiconductor chip 511 of a pixel portion 101 and a semiconductor chip 512 of a processing circuit are stacked. Figure 2As shown, the solid-state imaging device 100 includes two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0077] The semiconductor chip 511 includes a pixel portion 101 formed on a semiconductor substrate. The semiconductor chip 512 includes an ADC group 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 includes a timing control circuit 102, a vertical scanning circuit 103, a DAC 104, a horizontal transfer scanning circuit 106, etc. The peripheral circuit 517 includes a processing circuit 108, etc.

[0078] Each pixel of the pixel portion 101 of the semiconductor chip 511 and the elements of the processing circuit (105, 516 and 517) of the semiconductor chip 512 can be electrically connected by using through electrodes such as through silicon vias (TSVs) provided in the through hole regions 513 and 514. The ADC group 105 can send signals to the pixel portion 101 and receive signals from the pixel portion 101 via the TSV. In addition, the two semiconductor chips can be bonded (Cu-Cu bonding) so that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are in contact with each other. In addition, although not shown, a portion of the pixel portion 101 and the processing circuit (105, 516 and 517) can be constructed as one semiconductor chip 511, and the other components can be constructed as another semiconductor chip 512.

[0079] (Circuit Configuration of Unit Pixel PX)

[0080] Figure 3 is a circuit diagram showing a configuration example of a unit pixel PX arranged in the pixel array section 11 .

[0081] The unit pixel PX includes a first photoelectric conversion portion PD11a, a second photoelectric conversion portion PD11b, first to fourth transfer gate portions T12a to T12d, a reset gate portion T13, a charge accumulation portion C14, a first floating diffusion (FD) portion FD15a, a second floating diffusion (FD) portion FD15b, an amplification transistor T16, and a selection transistor T17.

[0082] In addition, for the unit pixel PX, a plurality of driving lines are used as Figure 1 The pixel drive lines 109 in the embodiment are wired for each pixel row, for example. Figure 1 The vertical scanning circuit 103 in the embodiment supplies various driving signals TGL, FCG, FDG, TGS, RST and SEL via a plurality of driving lines. Since each transistor of the unit pixel PX is an NMOS transistor, these driving signals are pulse signals that enter an active state in a high level state (e.g., a power supply voltage VDD) and enter an inactive state in a low level state (e.g., a negative potential).

[0083] The first photoelectric conversion portion PD11a includes, for example, a PN junction photodiode. The first photoelectric conversion portion PD11a generates and accumulates electric charges corresponding to the light amount of received light.

[0084] Similar to the first photoelectric conversion portion PD11a, the second photoelectric conversion portion PD11b includes, for example, a PN junction photodiode. The second photoelectric conversion portion PD11b generates and accumulates electric charges corresponding to the light amount of received light.

[0085] Comparing the first photoelectric conversion portion PD11 a and the second photoelectric conversion portion PD11 b , the first photoelectric conversion portion PD11 a has a larger light receiving surface area than the second photoelectric conversion portion PD11 b , and has higher sensitivity.

[0086] The first transmission gate portion T12a is connected between the first photoelectric conversion portion PD11a and the first FD portion FD15a. A driving signal TGL is applied to the gate electrode of the first transmission gate portion T12a. When the driving signal TGL enters an active state, the first transmission gate portion T12a enters a conductive state, and the charge accumulated in the first photoelectric conversion portion PD11a is transferred to the first FD portion FD15a via the first transmission gate portion T12a.

[0087] The second transmission gate portion T12b is connected between the charge accumulation portion C14 and the second FD portion FD15b. A drive signal FCG is applied to the gate electrode of the second transmission gate portion T12b. When the drive signal FCG enters an active state, the second transmission gate portion T12b enters a conductive state, and the potentials of the charge accumulation portion C14 and the second FD portion FD15b are coupled.

[0088] The third transmission gate portion T12c is connected between the first FD portion FD15a and the second FD portion FD15b. A driving signal FDG is applied to the gate electrode of the third transmission gate portion T12c. When the driving signal FDG enters an active state, the third transmission gate portion T12c enters a conductive state, and the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled.

[0089] The fourth transfer gate portion T12d is connected between the second photoelectric conversion portion PD11b and the charge accumulation portion C14. A drive signal TGS is applied to the gate electrode of the fourth transfer gate portion T12d. When the drive signal TGS enters an active state, the fourth transfer gate portion T12d enters a conductive state, and the charge accumulated in the second photoelectric conversion portion PD11b is transferred to the charge accumulation portion C14 via the fourth transfer gate portion T12d.

[0090] In addition, the region under the gate electrode of the fourth transfer gate portion T12d has a slightly deeper potential, and an overflow path is formed to transfer the charge exceeding the saturation charge amount of the second photoelectric conversion portion PD11b and overflowing from the second photoelectric conversion portion PD11b to the charge accumulation portion C14. Note that hereinafter, the overflow path formed in the region under the gate electrode of the fourth transfer gate portion T12d is simply referred to as the overflow path of the fourth transfer gate portion T12d.

[0091] The reset gate portion T13 is connected between a power supply (hereinafter, the power supply may also be referred to as VDD) that supplies the power supply voltage VDD and the second FD portion FD15b. A drive signal RST is applied to the gate electrode of the reset gate portion T13. When the drive signal RST enters an activated state, the reset gate portion T13 enters a conductive state. Therefore, for example, the potential of the region where the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled or the potential of the region where the potentials of the charge accumulation portion C14, the first FD portion FD15a and the second FD portion FD15b are coupled is reset to the level of the power supply voltage VDD.

[0092] The charge accumulation portion C14 includes, for example, a capacitor, and the opposite electrodes of the charge accumulation portion C14 are connected between the power supply VDD. The charge accumulation portion C14 accumulates the charge transferred from the second photoelectric conversion portion PD11b.

[0093] The first FD portion FD15a and the second FD portion FD15b convert the charge charge-voltage in the first photoelectric conversion portion PD11a or the second photoelectric conversion portion PD11b into a voltage signal, and output the voltage signal. The capacitance of the entire FD portion of the pixel PX can be switched by electrically connecting or disconnecting the first FD portion FD15a and the second FD portion FD15b. Switching the capacitance of the FD portion of the pixel PX enables the pixel PX to output a pixel signal with multiple charge-voltage conversion efficiencies.

[0094] The amplifying transistor T16 has a gate electrode connected to the first FD portion FD15a and a drain electrode connected to the power supply VDD, and serves as an input unit of a readout circuit (so-called source follower circuit) that reads out the charge held in the first FD portion FD15a. That is, the amplifying transistor T16 has a source electrode connected to the vertical signal line 110 via the selecting transistor T17, thereby constituting a source follower circuit together with a constant current source CS18 connected to one end of the vertical signal line 110.

[0095] The selection transistor T17 is connected between the source electrode of the amplifying transistor T16 and the vertical signal line 110. A driving signal SEL is applied to the gate electrode of the selection transistor T17. When the driving signal SEL enters an activated state, the selection transistor T17 enters a conducting state, and the unit pixel PX enters a selected state. Therefore, the pixel signal output from the amplifying transistor T16 is output to the vertical signal line 110 via the selection transistor T17.

[0096] Note that, hereinafter, making each drive signal enter an activated state is also referred to as turning on each drive signal, and making each drive pulse signal enter an inactivated state is also referred to as turning off each drive signal. In addition, hereinafter, making each gate portion or each transistor enter a conductive state is also referred to as turning on each gate portion or each transistor, and making each gate portion or each transistor enter a non-conductive state is also referred to as turning off each gate portion or each transistor.

[0097] (Operation of unit pixel PX)

[0098] (Operation example when exposure of unit pixel PX starts)

[0099] First, refer to Figure 4 The timing diagram of FIG. 1 illustrates an example of operation when exposure of the unit pixel PX starts. For example, the process is performed for each pixel row of the pixel array section 11 or for each plurality of pixel rows in a predetermined scanning order. Note that Figure 4 A timing diagram of the horizontal synchronization signal XHS and the driving signals SEL, RST, FDG, TGL, TGS and FCG is shown.

[0100] First, at time t1 , a horizontal synchronization signal XHS is input, and an exposure process of the unit pixel PX starts.

[0101] Next, at time t2, the drive signals RST and FDG are turned on, and the reset gate portion T13 and the third transfer gate portion T12c are turned on. Therefore, the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.

[0102] Next, at time t3, the driving signal TGL is turned on, and the first transfer gate portion T12a is turned on. Therefore, the charges accumulated in the first photoelectric conversion portion PD11a are transferred to the potential coupling region of the first FD portion FD15a and the second FD portion FD15b via the first transfer gate portion T12a, and the first photoelectric conversion portion PD11a is reset.

[0103] Next, at time t4, the driving signal TGL is turned off, and the first transfer gate portion T12a is turned off. Therefore, charge accumulation in the first photoelectric conversion portion PD11a is started, and an exposure period is started.

[0104] Next, at time t5, the drive signals TGS and FCG are turned on, and the fourth transfer gate portion T12d and the second transfer gate portion T12b are turned on. Therefore, the potentials of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b are coupled. In addition, the charge accumulated in the second photoelectric conversion portion PD11b is transferred to the coupling region via the fourth transfer gate portion T12d, and the second photoelectric conversion portion PD11b and the charge accumulation portion C14 are reset.

[0105] Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate portion T12d is turned off. Thus, charge accumulation in the second photoelectric conversion portion PD11b is started.

[0106] Next, at time t7, the drive signal FCG is turned off, and the second transfer gate portion T12b is turned off. Therefore, the charge accumulation portion C14 starts accumulating the charge overflowing from the second photoelectric conversion portion PD11b and transferred via the overflow path of the fourth transfer gate portion T12d.

[0107] Next, at time t8, the driving signals RST and FDG are turned off, and the reset gate portion T13 and the third transmission gate portion T12c are turned off.

[0108] Then, at time t9, the horizontal synchronization signal XHS is input.

[0109] (Operation Example When Reading Unit Pixel PX)

[0110] Next, we will refer to Figure 5 The timing diagram of FIG. 1 illustrates an operation example when the pixel signal of the unit pixel PX is read out. For example, when executing Figure 4 After a predetermined time from the time of the processing, the processing is performed for each pixel row of the pixel array section 11 or for each plurality of pixel rows in a predetermined scanning order. Note that Figure 5 A timing diagram of the horizontal synchronization signal XHS and the driving signals SEL, RST, FDG, TGL, TGS and FCG is shown.

[0111] First, at time t21 , the horizontal synchronization signal XHS is input, and the readout period of the unit pixel PX starts.

[0112] Next, at time t22, the drive signals SEL, RST and FDG are turned on, and the selection transistor T17, the reset gate portion T13 and the third transmission gate portion T12c are turned on. Therefore, the unit pixel PX enters a selected state. In addition, the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.

[0113] Next, at time t23 , the driving signal RST is turned off, and the reset gate portion T13 is turned off.

[0114] Next, at a time ta between time t23 and time t24, a signal NH2 based on the coupling potential of the first FD portion FD15a and the second FD portion FD15b is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal NH2 is detected by using the coupling region of the first FD portion FD15a and the second FD portion FD15b. Figure 3 A signal obtained by resetting the first photoelectric conversion portion PD11a, the FD portion FD15a, and the FD portion FD15b.

[0115] Note that, hereinafter, the signal NH2 is also referred to as a high-sensitivity reset signal NH2.

[0116] Next, at time t24, the driving signal FDG is turned off, and the third transfer gate portion T12c is turned off. Therefore, the potential coupling between the first FD portion FD15a and the second FD portion FD15b is released.

[0117] Next, at time tb between time t24 and time t25, a signal NH1 based on the potential of the first FD portion FD15a is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal NH1 is detected by using the first FD portion FD15a. Figure 3 The signal is obtained by resetting the first photoelectric conversion portion PD11a and the first FD portion FD15a.

[0118] Note that, hereinafter, the signal NH1 is also referred to as a high-sensitivity reset signal NH1.

[0119] Next, at time t25, the driving signal TGL is turned on, and the first transfer gate portion T12a is turned on. Therefore, the charges generated and accumulated in the first photoelectric conversion portion PD11a during the exposure period are transferred to the first FD portion FD15a via the first transfer gate portion T12a.

[0120] At time t25 , readout of the pixel signal starts, and the exposure period ends.

[0121] Next, at time t26, the driving signal TGL is turned off, and the first transfer gate portion T12a is turned off. Therefore, the charge transfer from the first photoelectric conversion portion PD11a to the first FD portion FD15a is stopped.

[0122] Next, at time tc between time t26 and time t27, a signal SH1 based on the potential of the first FD portion FD15a is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal SH1 is a signal based on the potential of the first FD portion FD15a when the charges generated in the first photoelectric conversion portion PD11a during the exposure period are accumulated in the first FD portion FD15a.

[0123] Note that, hereinafter, the signal SH1 is also referred to as a high-sensitivity data signal SH1 .

[0124] Next, at time t27, the drive signals FDG and TGL are turned on, and the third transfer gate portion T12c and the first transfer gate portion T12a are turned on. Therefore, the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled, and the charge that has not been transmitted from time t25 to time t26 and remains in the first photoelectric conversion portion PD11a is transmitted to the coupling region via the first transfer gate portion T12a. Note that when reading out the high-sensitivity data signal SH1, the capacitance used for charge-voltage conversion is small relative to the amount of charge to be processed, so there is no problem even if the charge remains in the first photoelectric conversion portion PD11a. The charge retained in the first photoelectric conversion portion PD11a only needs to be able to be transmitted when the high-sensitivity data signal SH2 is read out, and the charge in the first photoelectric conversion portion PD11a will not be wasted.

[0125] Next, at time t28, the drive signal TGL is turned off, and the first transfer gate portion T12a is turned off, thereby stopping the charge transfer from the first photoelectric converter PD11a to the potential-coupled region of the first FD portion FD15a and the second FD portion FD15b.

[0126] Next, at time td between time t28 and time t29, a signal SH2 based on the potential of the region where the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal SH2 is a signal based on the potential of the coupling region of the first FD portion FD15a and the second FD portion FD15b when the charges generated in the first photoelectric conversion portion PD11a during the exposure period are accumulated in the coupling region of the first FD portion FD15a and the second FD portion FD15b. Therefore, the capacitance used for charge-voltage conversion when reading out the signal SH2 is the total capacitance of the first FD portion FD15a and the second FD portion FD15b, and is greater than the capacitance when the high-sensitivity data signal SH1 is read out at time tc.

[0127] Note that, hereinafter, the signal SH2 is also referred to as a high-sensitivity data signal SH2.

[0128] Next, at time t29, the drive signal RST is turned on, and the reset gate portion T13 is turned on. Therefore, the potential of the region where the potentials of the first FD portion FD15a and the second FD portion FD15b are coupled is reset to the level of the power supply voltage VDD.

[0129] Next, at time t30, the driving signal SEL is turned off, and the selection transistor T17 is turned off. Therefore, the unit pixel PX enters a non-selected state.

[0130] Next, at time t31 , the driving signal RST is turned off, and the reset gate portion T13 is turned off.

[0131] Next, at time t32, the drive signals SEL, TGS, and FCG are turned on, and the selection transistor T17, the fourth transmission gate portion T12d, and the second transmission gate portion T12b are turned on. Therefore, the unit pixel PX enters a selected state. In addition, the potentials of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b are coupled, and the charge accumulated in the second photoelectric conversion portion PD11b is transferred to the coupling region. Therefore, the charge accumulated in the second photoelectric conversion portion PD11b and the charge accumulation portion C14 during the exposure period is accumulated in the coupling region.

[0132] Next, at time t33, the drive signal TGS is turned off, and the fourth transfer gate portion T12d is turned off. Therefore, the charge transfer from the second photoelectric conversion portion PD11b is stopped.

[0133] Next, at time te between time t33 and time t34, a signal SL based on the potential of the coupling region of the charge accumulation section C14, the first FD section FD15a, and the second FD section FD15b is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal SL is a signal based on the potential of the coupling region of the charge accumulation section C14, the first FD section FD15a, and the second FD section FD15b when the charges generated in the second photoelectric conversion section PD11b and accumulated in the second photoelectric conversion section PD11b and the charge accumulation section C14 are accumulated in the coupling region. Therefore, the capacitance used for charge-voltage conversion when reading out the signal SL is the total capacitance of the charge accumulation section C14, the first FD section FD15a, and the second FD section FD15b. This capacitance is larger than the capacitance when the high-sensitivity data signal SH1 is read out at time tc and the capacitance when the high-sensitivity data signal SH2 is read out at time td.

[0134] Note that, hereinafter, the signal SL is also referred to as a low-sensitivity data signal SL.

[0135] Next, at time t34, the driving signal RST is turned on, and the reset gate portion T13 is turned on. Therefore, the coupling region of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b is reset.

[0136] Next, at time t35, the drive signals SEL and FCG are turned off, and the selection transistor T17 and the second transfer gate portion T12b are turned off. Therefore, the unit pixel PX enters a non-selected state. In addition, the potential of the charge accumulation portion C14 is separated from the potential of the first FD portion FD15a and the second FD portion FD15b.

[0137] Next, at time t36, the driving signal RST is turned off, and the reset gate portion T13 is turned off.

[0138] Next, at time t37, the drive signals SEL and FCG are turned on, and the selection transistor T17 and the second transfer gate portion T12b are turned on. Therefore, the unit pixel PX enters a selected state. In addition, the potential of the charge accumulation portion C14 is coupled with the potential of the first FD portion FD15a and the second FD portion FD15b.

[0139] Next, at time tf between time t37 and time t38, a signal NL based on the potential of the coupling region of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b is output to the vertical signal line 110 via the amplification transistor T16 and the selection transistor T17. The signal NL is a signal based on the potential in the coupling region of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b in a reset state.

[0140] Note that, hereinafter, the signal NL is also referred to as a low-sensitivity reset signal NL.

[0141] Next, at time t38, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor T17, the third transfer gate portion T12c, and the second transfer gate portion T12b are turned off. Therefore, the unit pixel PX enters a non-selected state. In addition, the potential coupling between the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b is released.

[0142] Next, at time t39 , the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel PX ends.

[0143] The ADC group 105 performs AD conversion on the pixel signal from such a pixel PX having a high dynamic range (HDR). In this case, when one pixel signal is read out, the ADC group 105 sequentially performs AD conversion on the high sensitivity reset signal NH2, the high sensitivity reset signals NH1 and NL, the high sensitivity data signals SH1 and SH2, the low sensitivity data signal SL, and the low sensitivity reset signal NL.

[0144] In order to realize HDR in each such pixel, it is necessary to perform AD conversion on the reset signal and the data signal each time the conversion efficiency (capacitance of the FD unit) or the sensitivity (area of ​​the photoelectric conversion unit) of the pixel changes. One AD conversion mainly includes a period (settling period) until the potential of the FD unit stabilizes and a period (conversion period) for performing AD conversion on the pixel signal. Therefore, in the case of performing multiple AD conversions, the settling period and the AD conversion period are repeated alternately for each AD conversion. Therefore, in a pixel with HDR, the number of AD conversions of the ADC group 105 is increased, the readout time is increased, and the frame rate is reduced.

[0145] Therefore, in the present technology, a plurality of SH sections 125 are provided between the pixel section 101 and the ADC group 105, and the settling period and the AD conversion period of a plurality of signals are simultaneously performed in parallel. Hereinafter, a more detailed configuration and operation of the SH section 125 will be described.

[0146] (Configuration of SH section 125)

[0147] Figure 6 1 is a circuit diagram showing a configuration example of a pixel PX, an SH portion 125, and a comparator 121 according to the first embodiment. The pixel PX is as described above. Note that, Figure 6 1 shows a selected pixel PX in the pixel section 101. Figure 6 The configuration of the SH portion 125 and the comparator 121 corresponding to one vertical signal line 110 for one column is shown.

[0148] The SH section 125 includes a first holding circuit SHC1 , a second holding circuit SHC2 , a bypass signal line BP, and a multiplexer MUX. The input of the SH section 125 is connected to the pixel PX via the vertical signal line 110 , and the output thereof is connected to the input of the comparator 121 of the ADC group 105 .

[0149] (Configuration and Function of First Holding Circuit SHC1)

[0150] The first holding circuit SHC1 is provided between the pixel section 101 and the comparator 121, and is configured to sample and hold a pixel signal. The first holding circuit SHC1 includes a capacitor Cp1, a transistor Tr1, switches Sw1 to Sw3, and a constant current source Cs1.

[0151] One end of the capacitor Cp1 as a first capacitor is connected to the pixel PX via the switch Sw1, and the capacitor Cp1 can accumulate a pixel signal. The other end of the capacitor Cp1 is connected to the gate of the transistor Tr1.

[0152] The gate (node ​​Ng1) of the transistor Tr1 as the first transistor is connected to the other end of the capacitor Cp1. The drain (node ​​Nshc1) of the transistor Tr1 is connected to the constant current source Cs1 and the multiplexer MUX, and its source is connected to the ground (reference voltage source) GND. The constant current source Cs1 is connected between the power supply VDD and the node Nshc1, and causes a constant current to flow to the drain of the transistor Tr1. The transistor Tr1 causes a current depending on the potential of the gate (node ​​Ng1) to flow between the drain and the source. Therefore, the drain (node ​​Nshc1) of the transistor Tr1 has a potential corresponding to the potential of the gate (node ​​Ng1) of the transistor Tr1. The node Nshc1 is connected to the multiplexer MUX, and the voltage of the node Nshcl is output as the output signal OUTshc1 of the first holding circuit SHC1.

[0153] The switch Sw1 is connected between the capacitor Cp1 and the pixel PX. The switch Sw2 is connected between the drain of the transistor Tr1 (node ​​Nshc1) and one end of the capacitor Cp1. The switch Sw3 is connected between the drain of the transistor Tr1 (node ​​Nshc1) and the other end of the capacitor Cp1.

[0154] When the first holding circuit SHC1 samples the pixel signal from the pixel PX to the capacitor Cp1, the switches Sw1 and Sw3 are turned on (conduction state). At this time, the switch Sw2 is turned off (non-conduction state). Therefore, the pixel signal is transmitted to one end of the capacitor Cp1, and therefore, the capacitor node on the opposite side of the gate of the transistor Tr1 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switches Sw1 and Sw3 are turned off and the switch Sw2 is turned on. Therefore, the pixel signal accumulated in the capacitor Cpl is held. At this time, the transistor Tr1 enters a conduction state (analog state) corresponding to the pixel signal, and the drain (node ​​Nshc1) of the transistor Tr1 is maintained at a potential corresponding to the pixel signal. Therefore, the first holding circuit SHC1 outputs the output signal OUTshc1 corresponding to the pixel signal from the node Nshc1 to the multiplexer MUX.

[0155] (Configuration and Function of Second Holding Circuit SHC2)

[0156] Similar to the first holding circuit SHC1, the second holding circuit SHC2 is provided between the pixel portion 101 and the comparator 121, and is configured to sample and hold the pixel signal. The second holding circuit SHC2 includes a capacitor Cp2, a transistor Tr2, switches Sw4 to Sw6, and a constant current source Cs2. The second holding circuit SHC2 samples the pixel signal from the same pixel PX as the first holding circuit SHC1 at different times. Therefore, the first holding circuit SHC1 and the second holding circuit SHC2 can sample and hold a plurality of pixel signals having different sensitivities or conversion efficiencies from the same pixel PX.

[0157] One end of the capacitor Cp2 as the second capacitor is connected to the pixel PX via the switch Sw4, and the capacitor Cp1 can accumulate the pixel signal. The other end of the capacitor Cp2 is connected to the gate of the transistor Tr2.

[0158] The gate (node ​​Ng2) of transistor Tr2 as the second transistor is connected to the other end of capacitor Cp2. The drain (node ​​Nshc2) of transistor Tr2 is connected to constant current source Cs2 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source Cs2 is connected between power supply VDD and node Nshc2, and causes constant current to flow to the drain of transistor Tr2. Transistor Tr2 causes a current depending on the potential of the gate (node ​​Ng2) to flow between the drain and the source. Therefore, the drain (node ​​Nshc2) of transistor Tr2 has a potential corresponding to the potential of the gate (node ​​Ng2) of transistor Tr2. Node Nshc2 is connected to multiplexer MUX, and the voltage of node Nshc2 is output as output signal OUTshc2 of second holding circuit SHC2.

[0159] The switch Sw4 is connected between the capacitor Cp2 and the pixel PX. The switch Sw5 is connected between the drain of the transistor Tr2 (node ​​Nshc2) and one end of the capacitor Cp2. The switch Sw6 is connected between the drain of the transistor Tr2 (node ​​Nshc2) and the other end of the capacitor Cp2.

[0160] When the second holding circuit SHC2 samples the pixel signal from the pixel PX to the capacitor Cp2, the switches Sw4 and Sw6 are turned on. At this time, the switch Sw5 is turned off. Therefore, the pixel signal is transmitted to one end of the capacitor Cp2, and therefore, the capacitor node on the opposite side of the gate of the transistor Tr2 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp2 holds the pixel signal, the switches Sw4 and Sw6 are turned off, and the switch Sw5 is turned on. Therefore, the pixel signal accumulated in the capacitor Cp2 is held. At this time, the gate (node ​​Ng2) of the transistor Tr2 enters a conduction state (analog state) corresponding to the pixel signal, and the drain (node ​​Nshc2) of the transistor Tr2 is maintained at a potential corresponding to the pixel signal. Therefore, the second holding circuit SHC2 outputs the output signal OUTshc2 corresponding to the pixel signal from the node Nshc2 to the multiplexer MUX.

[0161] As described above, each of the first holding circuit SHC1 and the second holding circuit SHC2 is configured as an active element. Therefore, the first holding circuit SHC1 and the second holding circuit SHC2 resist fluctuations in the voltage of the ground GND and the power supply VDD, and can eliminate characteristic variations of the transistors Tr1 and Tr2.

[0162] (Configuration and Function of Bypass Signal Line BP)

[0163] The bypass signal line BP is provided between the pixel PX and the comparator 121 of the ADC group 105, and transmits the pixel signal from the pixel PX as it is via the multiplexer MUX. The bypass signal line BP directly outputs the output signal OUTbp via the multiplexer MUX without holding the pixel signal through a capacitor or the like. Therefore, the noise caused by the capacitors Cp1 and Cp2 and the transistors Tr1 and Tr2 is not mixed into the pixel signal. That is, in the case where the signal degradation component applied by the holding circuits SHC1 and SHC2 cannot be tolerated, for example, in the case where the noise near the dark signal needs to be minimized with high conversion efficiency, the bypass signal line BP can be used.

[0164] (Multiplexer MUX)

[0165] The multiplexer MUX is connected between the first holding circuit SHC1, the second holding circuit SHC2, and the bypass signal line BP and the comparator 121. The multiplexer MUX as a selection circuit can selectively connect any one of the first holding circuit SHC1, the second holding circuit SHC2, and the bypass signal line BP to the comparator 121 of the ADC group 105. Therefore, the multiplexer MUX can selectively transmit the pixel signal OUTshc1 held in the first holding circuit SHC1, the pixel signal OUTshc2 held in the second holding circuit SHC2, or the pixel signal OUTbp transmitted through the bypass signal line BP to the comparator 121. The multiplexer MUX selects the holding circuit SHC1, the holding circuit SHC2, or the bypass signal line BP to be connected to the comparator 121 based on the selection signal SEL2. The selection signal SEL2 is received from the vertical scanning circuit 103. The selection signal SEL2 only needs to be set to select one of the holding circuit SHC1, the holding circuit SHC2 and the bypass signal line BP according to the control signals TGL, TGS, FDG, FCG and SEL of the pixel PX. The multiplexer MUX only needs to be composed of any switch circuit capable of performing the above operation.

[0166] (Configuration and Function of Comparator 121)

[0167] The comparator 121 includes an input comparison circuit 121 a and an output circuit 121 b .

[0168] The input comparison circuit 121 a includes p-type transistors Tp1 and Tp2 , n-type transistors Tn1 to Tn3 , capacitors Cvs1 and Cref, and an AZ switch SwAZ.

[0169] One ends of the capacitors Cvs1 and Cref are respectively connected to the output of the SH section 125 and the reference signal line 114. The other ends of the capacitors Cvs1 and Cref are commonly connected to the gate of the transistor Tp1.

[0170] The transistors Tn1, Tp1, and Tn2 are connected in series in sequence between a power source VDD and a ground GND.

[0171] The drain of the transistor Tn1 is connected to the power supply VDD, and the source thereof is connected to the source of the transistor Tp1. The transistor Tn1 functions as a low dropout (LDO) linear regulator.

[0172] As described above, the gate of transistor Tp1 is commonly connected to the other end of capacitors Cvsl and Cref. The source of transistor Tp1 is connected to the source of transistor Tn1, and the drain of transistor Tp1 is connected to the drain of transistor Tn2 and the gate of transistor Tp2. When the output signal (any one of OUTbp, OUTshc1 and OUTshc2) of the multiplexer MUX from the SH section 125 and the added signal of the reference signal RAMP from the DAC 104 exceed the threshold voltage, transistor Tp1 changes from the conducting state to the non-conducting state, and the voltage level of the gate of transistor Tp2 is reversed from the high level to the low level. That is, transistor Tp1a is used as an amplifier that amplifies and detects the level of the output signal from the multiplexer MUX.

[0173] The gate of transistor Tp2 is connected to the drain of transistor Tp1. The source of transistor Tp2 is connected to the source of transistor Tn1 together with the source of transistor Tp1. The drain of transistor Tp2 is connected to the drain of transistor Tn2. When transistor Tp1 changes from a conducting state to a non-conducting state, transistor Tp2 changes from a non-conducting state to a conducting state inversely, and the drain voltage of transistor Tp2 is reversed from a low level to a high level.

[0174] The transistor Tn2 is connected between the drain of the transistor Tp1 and the ground GND, and functions as a constant current source for causing a constant current to flow through the transistor Tp1. The transistor Tn3 is connected between the drain of the transistor Tp2 and the ground GND, and functions as a constant current source for causing a constant current to flow through the transistor Tp2.

[0175] The AZ switch SwAZ is connected between the gate of the transistor Tp1 and the gate of the transistor Tp2 , and performs an auto-zero operation by making the potential between the gate and the drain of the transistor Tp1 equal before the output signal of the SH section 125 is detected.

[0176] Output circuit 121b includes p-type transistors Tp3 and Tp4 and n-type transistors Tn4 and Tn5. Transistor Tp3 is connected between power supply VDD and output terminal OUT121 of comparator 121. Transistor Tn5 is connected between source of transistor Tn4 and ground GND. The gates of transistors Tp3 and Tn5 are connected in common. Transistors Tp3 and Tn5 have the effect of fixing output OUT121 to high level in the period outside the counting period. Transistors Tp4 and Tn4 are connected in series between power supply VDD and drain of transistor Tn5. The node between transistor Tp4 and transistor Tn4 is output terminal OUT121. The gates of transistors Tp4 and Tn4 are connected in common to the output (drain of transistor Tp2) of input comparison circuit 121a. Transistors Tp4 and Tn4 are used as inverter circuits.

[0177] When the drain voltage of the transistor Tp2 is inverted from low level to high level, the output terminal OUT121 of the comparator 121 is inverted from high level to low level through the transistors Tp4 and Tn4. The inversion of the voltage level of the output terminal OUT121 serves to stop the operation of the counter 122. This enables AD conversion.

[0178] (Configuration of Negative Capacitance Circuit 310)

[0179] The negative capacitance circuit 310 includes n-type transistors Tn6 to Tn8, a capacitor C310, and a constant current source Cs310. The gate of the transistor Tn8 is connected to the vertical signal line 110. The drain of the transistor Tn8 is connected to the power supply VDD, and its source is connected to the constant current source Cs310. Therefore, the transistor Tn8 and the constant current source Cs310 act as a source follower, and its gain is less than "1".

[0180] One end of the capacitor C310 is connected to the gate of the transistor Tn8 via the transistor Tn6. The other end of the capacitor C310 is connected to the source of the transistor Tn8. Therefore, the same polarity signal obtained by dividing the vertical signal line 110 by the gain of the transistor Tn6 appears at the source of the transistor Tn6, and the signal obtained by multiplying the fluctuation of the vertical signal line 110 by the gain of the source follower appears on the source side of the transistor Tn8. Therefore, at both ends of the capacitor C310, a relatively large gain of the same polarity is applied to the source side of the transistor Tn8 relative to the source side of the transistor Tn6. Therefore, the circuit 310 is used as a negative capacitance circuit.

[0181] The transistor Tn7 is connected between one end of the capacitor C310 and the ground GND. The transistor Tn6 is connected between one end of the capacitor C310 and the vertical signal line 110. The transistor Tn7 serves as a constant current source for the vertical signal line 110.

[0182] Parasitic capacitance is generated in the vertical signal line 110. Assume that a voltage of +Vs is applied to the parasitic capacitance of the vertical signal line 110.

[0183] In this case, in the negative capacitance circuit 310, when the gain of the transistor Tn8 and the constant current source Cs310 used as a source follower is set to "0.9" and the gain from the source to the drain of the transistor Tn6 is set to "10", 0.1×Vs is applied to the terminal of the capacitor C310 on the vertical signal line 110 side, and 0.9×Vs is applied to the terminal on the opposite side. Therefore, when the potential (0.9×Vs) on the opposite side of the vertical signal line 110 is set as a reference, a voltage of -0.8×Vs is applied to the capacitor C310. Therefore, +Vs is applied to the parasitic capacitance of the vertical signal line 110, and -0.8×Vs is applied to the capacitor C310. Therefore, compared with the case where the negative capacitance circuit 310 is not provided, the wiring capacitance of the vertical signal line 110 is reduced.

[0184] Note that although the transistor Tn8 serving as a source follower and the constant current source Cs310 are used in the present disclosure, other configurations capable of non-inverting amplification may be used as long as the influence of the parasitic capacitance of the vertical signal line 110 can be sufficiently reduced.

[0185] (Operation of SH section 125)

[0186] Figure 7 : is a timing chart showing an operation example of the SH section 125 in the AD conversion operation. Figure 7 Shown with Figure 5 The readout operation of the pixel PX in FIG. 1 corresponds to the operation of the SH section 125. Note that Figure 7 In the upper part of FIG. 1 , the voltage VSL of the vertical signal line 110 and the reference signal RAMP corresponding to the signals to be read out (NH2, NH1, SH1, SH2, SL, and NL) are shown. Figure 7 SHC1 and SHC2 in FIG. 1 represent states of the first holding circuit SHC1 and the second holding circuit SHC2 , respectively.

[0187] The selection signals SEL_BP, SEL_SHC1 and SEL_SHC2 are signals input to the multiplexer MUX as the selection signal SEL2. The selection signals SEL_BP, SEL_SHC1 and SEL_SHC2 are control signals for selecting one of the bypass signal line BP, the first holding circuit SHC1 and the second holding circuit SHC2, and the plurality of selection signals SEL_BP, SEL_SHC1 and SEL_SHC2 are not activated at the same time (do not reach a high level).

[0188] The selection signal SEL_BP is a signal for selecting the bypass signal line BP. When the selection signal SEL_BP reaches a high level, the multiplexer MUX outputs the pixel signal transmitted to the bypass signal line BP to the comparator 121. The selection signal SEL_SHC1 is a signal for selecting the first holding circuit SHC1. When the selection signal SEL_SHC1 reaches a high level, the multiplexer MUX outputs the pixel signal transmitted to the first holding circuit SHC1 to the comparator 121. When the selection signal SEL_SHC2 reaches a high level, the multiplexer MUX outputs the pixel signal transmitted to the second holding circuit SHC2 to the comparator 121.

[0189] The pixel PX, the SH portion 125 and the comparator 121 sequentially read out the high sensitivity reset signal NH2 , the high sensitivity reset signal NH1 , the high sensitivity data signal SH1 , the high sensitivity data signal SH2 , the low sensitivity data signal SL and the low sensitivity reset signal NL as pixel signals.

[0190] First, at time t21, the horizontal synchronization signal XHS is input, and the readout period of the unit pixel PX starts. Figure 5 As described above, the high-sensitivity reset signal NH2 based on the coupled potential of the first FD portion FD15 a and the second FD portion FD15 b is read out from the pixel PX.

[0191] From t21 to t24, the switches Sw1 and Sw3 of the first holding circuit SHC1 are turned on, and the switch Sw2 is turned off. Therefore, the first holding circuit SHC1 samples the high-sensitivity reset signal NH2. At this time, the first holding circuit SHC1 maintains the sampling state until the potential of the first FD portion FD15a and the second FD portion FD15b is stabilized. Hereinafter, the period from when the pixel transistor is operated until the potential of the FD is stabilized is also referred to as a settling period.

[0192] Note that at t21, the pixel signal from the second holding circuit SHC2 in the previous readout period is output from the multiplexer MUX, and the pixel signal is AD-converted. Therefore, from t21 to t24, the selection signal SEL_SHC2 reaches a high level.

[0193] Next, at time t24, the end Figure 3 The third transfer gate portion T12c is electrically disconnected from the first FD portion FD15a and the second FD portion FD15b. A high-sensitivity reset signal NH1 based on the potential of the first FD portion FD15a is read out from the pixel PX.

[0194] At this time, the selection signal SEL_SHC2 reaches a low level, and the selection signal SEL_BP reaches a high level. Therefore, from t24 to t25, the bypass signal line BP is selectively connected to the comparator 121. The high-sensitivity reset signal NH1 is transmitted to the comparator 121 via the bypass signal line BP. The high-sensitivity reset signal NH1 is AD-converted in the ADC group 105.

[0195] On the other hand, the switches Sw1 and Sw3 of the first holding circuit SHC1 are turned off, and the switch Sw2 is turned on. Therefore, the first holding circuit SHC1 holds the sampled high-sensitivity reset signal NH2.

[0196] Next, at time t25, the charge generated and accumulated in the first photoelectric conversion portion PD11a during the exposure period is transferred to the first FD portion FD15a. The high-sensitivity data signal SH1 is a pixel signal based on the potential of the first FD portion FD15a in a state where the charge generated in the first photoelectric conversion portion PD11a is accumulated. The high-sensitivity data signal SH1 based on the potential of the first FD portion FD15a is read out from the pixel PX. Therefore, as Figure 7 As shown, the voltage VSL of the vertical signal line 110 becomes a voltage corresponding to the light amount of the incident light.

[0197] At this time, also from t25 to t27, the bypass signal line BP is selectively connected to the comparator 121. The high sensitivity data signal SH1 is transmitted to the comparator 121 via the bypass signal line BP. The high sensitivity data signal SH1 is AD converted in the ADC group 105. Note that the first holding circuit SHC1 continues to hold the high sensitivity reset signal NH2.

[0198] Next, at time t27, the Figure 3 The third transfer gate T12c of the first photoelectric conversion unit PD11a is connected, and the first FD unit FD15a and the second FD unit FD15b are connected. Therefore, the charge generated and accumulated in the first photoelectric conversion unit PD11a during the exposure period is accumulated in the coupling capacitance of the first FD unit FD15a and the second FD unit FD15b. Therefore, the high-sensitivity data signal SH2 is a pixel signal based on the potential of the coupling capacitance when the charge generated in the first photoelectric conversion unit PD11a is accumulated in the coupling capacitance of the first FD unit FD15a and the second FD unit FD15b. That is, the high-sensitivity data signal SH2 is read out from the pixel PX.

[0199] At this time, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned on, and the switch Sw5 is turned off. Therefore, the second holding circuit SHC2 samples the high-sensitivity data signal SH2. At this time, the second holding circuit SHC2 maintains the sampling state during the settling period until the potentials of the first FD portion FD15a and the second FD portion FD15b are stabilized.

[0200] On the other hand, at t27, the selection signal SEL_BP reaches a low level, and the selection signal SEL_SHC1 reaches a high level. Therefore, the multiplexer MUX disconnects the bypass signal line BP from the comparator 121, and selectively connects the first holding circuit SHC1 to the comparator 121. When the first holding circuit SHC1 is connected to the comparator 121, the high-sensitivity reset signal NH2 held in the first holding circuit SHC1 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the high-sensitivity reset signal NH2 is AD-converted in the ADC group 105.

[0201] Next, refer to Figure 5 At t29, the potentials of the first FD portion FD15a and the second FD portion FD15b are reset to the power supply voltage VDD.

[0202] Next, at time t32, Figure 3 While the third transmission gate portion T22c of the photoelectric converter PD11b remains turned on, the fourth transmission gate portion T12d and the second transmission gate portion T12b are further turned on. Therefore, the charges generated in the second photoelectric converter PD11b during the exposure period are accumulated in the coupling capacitance of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b. Therefore, the low-sensitivity data signal SL is a pixel signal based on the potential of the coupling capacitance when the charges generated in the second photoelectric converter PD11b are accumulated in the coupling capacitance of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b. That is, the low-sensitivity data signal SL is read out from the pixel PX.

[0203] At this time, the switches Sw1 and Sw3 of the first holding circuit SHC1 are turned on, and the switch Sw2 is turned off. Therefore, the first holding circuit SHC1 samples the low-sensitivity data signal SL. In addition, during the settling period (t32 to t37) until the potentials of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b are stabilized, the first holding circuit SHC1 maintains the sampling state.

[0204] On the other hand, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned off, and the switch Sw5 is turned on. Therefore, from t32 to t37, the second holding circuit SHC2 holds the high-sensitivity data signal SH2 sampled from t27 to t32.

[0205] In addition, at t32, the selection signal SEL_SHC1 reaches a low level, and the selection signal SEL_SHC2 reaches a high level. Therefore, the multiplexer MUX disconnects the first holding circuit SH1 from the comparator 121, and selectively connects the second holding circuit SHC2 to the comparator 121. When the second holding circuit SHC2 is connected to the comparator 121, the high-sensitivity data signal SH2 held in the second holding circuit SHC2 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the high-sensitivity data signal SH2 is AD-converted in the ADC group 105.

[0206] Next, refer to Figure 5 At t34, the potentials of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b are reset to the power supply voltage VDD.

[0207] Next, at time t37, Figure 3 The third transfer gate portion T12c is turned on, and the fourth transfer gate portion T12d is turned off while the second transfer gate portion T12b is turned on. Therefore, the potential in the reset state based on the coupling capacitance of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b is read out from the pixel PX.

[0208] At this time, the switches Sw4 and Sw6 of the second hold circuit SHC2 are turned on, and the switch Sw5 is turned off. Therefore, the second hold circuit SHC2 samples the low-sensitivity reset signal NL.

[0209] On the other hand, the switches Sw1 and Sw3 of the first holding circuit SHC1 are turned off, and the switch Sw2 is turned on. Therefore, from t37 to t39, the first holding circuit SHC1 holds the low-sensitivity data signal SL sampled from t32 to t37.

[0210] At t37, the selection signal SEL_SHC2 reaches a low level, and the selection signal SEL_SHC1 reaches a high level. Therefore, the multiplexer MUX disconnects the second holding circuit SH2 from the comparator 121, and selectively connects the first holding circuit SHC1 to the comparator 121. When the first holding circuit SHC1 is connected to the comparator 121, the low sensitivity data signal SL held in the first holding circuit SHC1 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the low sensitivity data signal SL is AD-converted in the ADC group 105.

[0211] Next, refer to Figure 5At t39, the potentials of the charge accumulation portion C14, the first FD portion FD15a, and the second FD portion FD15b are reset to the power supply voltage VDD.

[0212] At time t39 , the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel PX ends.

[0213] Note that AD conversion of the low-sensitivity reset signal NL sampled by the second holding circuit SHC2 from t37 to t39 is performed in the readout period of the next unit pixel. Figure 7 The dotted box shown by t21 to t24 in FIG. 1 is the readout period of the next unit pixel, then during the readout period of the next unit pixel, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned off, and the switch Sw5 is turned on. Therefore, the second holding circuit SHC2 holds the low-sensitivity reset signal NL sampled immediately before. At this time, the second holding circuit SHC2 is connected to the comparator 121, and the low-sensitivity reset signal NL held in the second holding circuit SHC2 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the low-sensitivity reset signal NL is AD-converted in the ADC group 105.

[0214] Then, by repeating a similar cycle (one horizontal period), the ADC group 105 can perform AD conversion on the pixel signal from the pixel portion 101 .

[0215] As described above, the solid-state imaging device 100 according to the present disclosure includes the SH section 125 between the pixel section 101 and the ADC group 105. Each SH section 125 includes a bypass signal line BP, a first holding circuit SHC1, a second holding circuit SHC2, and a multiplexer MUX. The multiplexer MUX selectively outputs any one of the pixel signals output from the bypass signal line BP, the first holding circuit SHC1, and the second holding circuit SHC2 to the ADC group 105.

[0216] like Figure 7As shown, during the period when the multiplexer MUX outputs the first pixel signal held in the first holding circuit SHC1 to the ADC group 105, the second holding circuit SHC2 samples the second pixel signal as another signal and stabilizes the second pixel signal. Conversely, during the period when the multiplexer MUX outputs the second pixel signal held in the second holding circuit SHC2 to the ADC group 105, the first holding circuit SHC1 samples the first pixel signal as another signal and stabilizes the first pixel signal. In this way, the first holding circuit SHC1 and the second holding circuit SHC2 alternately repeat the sampling (and stabilization) and holding (and outputting) of the pixel signal. Therefore, during the period when one of the first holding circuit SHC1 and the second holding circuit SHC2 holds (and outputs) a pixel signal, the other pixel signal can be sampled (and stabilized) in parallel.

[0217] In the case where the SH unit 125 is not provided, a plurality of pixel signals are processed in series in sequence. For example, the first pixel signal undergoes AD conversion after a stable period. After the first pixel signal is AD-converted, the next second pixel signal also undergoes AD conversion after a stable period. After the second pixel signal is AD-converted, the next third pixel signal also undergoes AD conversion after a stable period. In this way, a plurality of pixel signals undergo AD conversion while the stable period and the AD conversion period are sequentially repeated in series. Therefore, it takes a long time to perform AD conversion on a plurality of pixel signals from one pixel PX. In particular, the stable period is generally longer than the AD conversion period, and therefore, when AD conversion is performed on a plurality of pixel signals in each pixel PX, the frame rate is extended.

[0218] On the other hand, in the present disclosure, during a period in which one of the first holding circuit SHC1 and the second holding circuit SHC2 holds (and outputs) a pixel signal, the other can sample (and settle) another pixel signal in parallel. Therefore, AD conversion processing of a plurality of pixel signals can be performed in parallel at the same time, and the frame rate can be shortened.

[0219] Furthermore, in the present disclosure, in addition to the first holding circuit SHC1 and the second holding circuit SHC2, a bypass signal line BP is provided. Therefore, in the case where the noise of the first holding circuit SHC1 and the second holding circuit SHC2 is not desired to be mixed in the pixel signal, the multiplexer MUX only needs to select the bypass signal line BP and directly transmit the pixel signal to the ADC group 105 via the bypass signal line BP. Therefore, the solid-state imaging device 100 can perform AD conversion on the reset signal and the digital signal in the case where the reset signal and the data signal are sensitive to noise and use high conversion efficiency, and the reset signal and the data signal are not affected by the noise of the first holding circuit SHC1 and the second holding circuit SHC2.

[0220] Note that, in order to shorten the frame rate, the SH section 125 only needs to include the first holding circuit SHC1 and the second holding circuit SHC2, and the bypass signal line BP is not necessary. However, in order to obtain a noise suppression effect, it is preferable to provide the bypass signal line BP.

[0221] Furthermore, in the present disclosure, the negative capacitance circuit 310 is connected to the vertical signal line 110. Therefore, the parasitic capacitance of the vertical signal line 110 can be eliminated, and the settling period of the potential of the vertical signal line 110 can be shortened.

[0222] In addition, the comparator 121 according to the present disclosure only needs to have a configuration capable of sequentially performing AD conversion on pixel signals one by one, and does not need to have a special and complex configuration capable of performing AD conversion on multiple pixel signals at the same time. That is, according to the present disclosure, although the pixel PX with HDR is used, the circuit scale of the ADC group 105 can be reduced by providing the SH unit 125.

[0223] (First Modification)

[0224] Figure 8 1 is a timing diagram showing an operation example of the SH unit 125 in the AD conversion operation according to the first modification. In this modification, after time t39, the short-time high-sensitivity reset signal NH2DOL and the short-time high-sensitivity data signal SH2DOL are read out. The short-time high-sensitivity reset signal NH2DOL and the short-time high-sensitivity data signal SH2DOL are respectively a high-sensitivity reset signal and a high-sensitivity data signal obtained by shortening the exposure time of the pixel PX. Shortening the exposure time makes it possible to suppress the saturation of the first photoelectric conversion unit PD11a and further expand the dynamic range.

[0225] The operation from t21 to t39 may be the same as that in the first embodiment.

[0226] Then, make Figure 3 The coupling capacitance of the first FD portion FD15a and the second FD portion FD15b in is reset. At time t39, Figure 3 The pixel PX in the state enters the same state as when the high-sensitivity reset signal NH2 is read out. The short-time high-sensitivity reset signal NH2DOL based on the coupling potential of the first FD portion FD15a and the second FD portion FD15b is read out from the pixel PX.

[0227] From t39 to t40, the switches Sw1 and Sw3 of the first holding circuit SHC1 are turned on, and the switch Sw2 is turned off. Therefore, the first holding circuit SHC1 samples the short-time high-sensitivity reset signal NH2DOL. At this time, the first holding circuit SHC1 maintains the sampling state until the potentials of the first FD portion FD15a and the second FD portion FD15b are stabilized.

[0228] On the other hand, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned off, and the switch Sw5 is turned on. Therefore, the second holding circuit SHC2 holds the low-sensitivity reset signal NL sampled from t37 to t39.

[0229] At this time, the selection signal SEL_SHC1 reaches a low level, and the selection signal SEL_SHC2 reaches a high level. Therefore, the multiplexer MUX disconnects the first holding circuit SHC1 from the comparator 121, and selectively connects the second holding circuit SHC2 to the comparator 121. When the second holding circuit SHC2 is connected to the comparator 121, the low sensitivity reset signal NL held in the second holding circuit SHC2 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the low sensitivity reset signal NL is AD-converted in the ADC group 105.

[0230] Next, at time t40, Figure 3 The pixel PX in the exposure period enters the same state as when the high-sensitivity data signal SH2 is read out. Therefore, the charge generated and accumulated in the first photoelectric conversion portion PD11a during the exposure period is accumulated in the coupling capacitance of the first FD portion FD15a and the second FD portion FD15b. The exposure period is shorter than the exposure period of the high-sensitivity data signal SH2. At the same time, a short-time high-sensitivity data signal SH2DOL based on the potential of the first FD portion FD15a and the second FD portion FD15b is read out from the pixel PX.

[0231] At this time, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned on, and the switch Sw5 is turned off. Therefore, the second holding circuit SHC2 samples the short-time high-sensitivity data signal SH2DOL. At this time, the second holding circuit SHC2 maintains the sampling state during the settling period until the potentials of the first FD portion FD15a and the second FD portion FD15b are stabilized.

[0232] On the other hand, at t40, the selection signal SEL_SHC2 reaches a low level, and the selection signal SEL_SHC1 reaches a high level. Therefore, the multiplexer MUX disconnects the second holding circuit SHC2 from the comparator 121, and selectively connects the first holding circuit SHC1 to the comparator 121. When the first holding circuit SHC1 is connected to the comparator 121, the short time high sensitivity reset signal NH2DOL held in the first holding circuit SHC1 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the short time high sensitivity reset signal NH2DOL is AD converted in the ADC group 105.

[0233] Note that in the readout period of the next unit pixel, the short-time high-sensitivity data signal SH2DOL sampled by the second holding circuit SHC2 from t40 to t41 is AD-converted. Figure 8 As shown in t21 to t24 of FIG. 1 , in the readout period of the next unit pixel, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned off, and the switch Sw5 is turned on. Therefore, the second holding circuit SHC2 holds the short-time high-sensitivity data signal SH2DOL sampled immediately before. At this time, the second holding circuit SHC2 is connected to the comparator 121, and the short-time high-sensitivity data signal SH2DOL held in the second holding circuit SHC2 is transmitted to the comparator 121 via the multiplexer MUX. Therefore, the short-time high-sensitivity data signal SH2DOL is AD-converted in the ADC group 105.

[0234] As described above, AD conversion is performed on a plurality of pixel signals in which not only the sensitivity and conversion efficiency of the pixels PX are changed but also the exposure time is changed, so that the dynamic range of the pixels PX is further expanded.

[0235] The configuration and other operations of this modification example may be the same as those of the first embodiment. Therefore, this modification example can obtain effects similar to those of the first embodiment.

[0236] (Second Modification)

[0237] Fig. 9 1 is a timing diagram showing an operation example of the SH section 125 in the AD conversion operation according to the second modification. In the second modification, the bypass signal line BP is omitted, the first holding circuit SHC1 and the second holding circuit SHC2 operate complementarily, and the pixel signal is repeatedly sampled and held alternately. That is, during a period in which one of the first holding circuit SHC1 and the second holding circuit SHC2 holds (and outputs) a pixel signal, the other can sample (and settle) another pixel signal in parallel. Therefore, AD conversion processing of a plurality of pixel signals can be performed in parallel at the same time, and the frame rate can be shortened.

[0238] The configuration and other operations of the second modification are similar to those of the first embodiment. Therefore, the second modification can also obtain similar effects to those of the first embodiment. In addition, the second modification can be combined with the first modification.

[0239] (Second embodiment)

[0240] Fig.10 1 is a circuit diagram showing a configuration example of a pixel PX, an SH unit 125, and a comparator 121 according to a second embodiment. In the second embodiment, the configuration of the comparator 121 is different from that of the first embodiment. The other configurations of the second embodiment may be similar to those of the first embodiment.

[0241] In the second embodiment, the input comparison circuit 121a includes p-type transistors Tp2, Tp11, and Tp12, n-type transistors Tn3, Tn11, and Tn12, capacitors Cvs1 and Cref, AZ switches SwAZ1 and SwAZ2, and a constant current source Cs121a.

[0242] One ends of the capacitors Cvs1 and Cref are respectively connected to the output of the SH section 125 and the reference signal line 114. The other ends of the capacitors Cvs1 and Cref are respectively connected to the gates of the transistors Tn11 and Tn12.

[0243] Transistors Tn11, Tn12, Tp11 and Tp12 and a constant current source Cs121a constitute a differential circuit, and output a voltage difference between a pixel signal (OUTbp, OUTshc1 or OUTshc2) from the SH portion 125 and a reference signal RAMP. Transistors Tp11 and Tp12 constitute a current mirror circuit, and make a current corresponding to a predetermined mirror ratio flow through transistors Tn11 and Tn12, respectively. Transistors Tn11 and Tn12 receive a pixel signal and a reference signal at the gate, respectively, and output a voltage difference from a node N121a. The constant current source Cs121a maintains a total current flowing through transistors Tn11 and Tn12 at a predetermined value.

[0244] The AZ switch SwAZ1 is connected between the gate and drain of the transistor Tn11 , and performs an auto-zero operation by making the potential between the gate and drain of the transistor Tn11 equal before detecting the output signal of the SH section 125 .

[0245] The AZ switch SwAZ2 is connected between the gate and drain of the transistor Tn12 , and performs an auto-zero operation by making the potential between the gate and drain of the transistor Tn12 equal before detecting the output signal of the SH section 125 .

[0246] The transistor Tp2 is used as an amplifier, which receives a voltage difference from the node N121a at the gate, amplifies the voltage difference, and outputs the voltage difference to the output circuit 121b. The transistor Tn3 is used as a constant current source to determine the current flowing through the transistor Tp2. The capacitor C121a is connected between the power supply VDD and the node N121a, and suppresses noise by reducing the operating frequency band of the comparator 121.

[0247] The output circuit 121b includes a p-type transistor Tp4 and an n-type transistor Tn4. The transistors Tp4 and Tn4 function as inverter circuits, invert the output voltage level from the input comparison circuit 121a, and output the inverted output voltage level from the output terminal OUT121 of the comparator 121. As described above, a conventional differential amplifier circuit can be used for the configuration of the comparator 121.

[0248] The other configurations and operations of the second embodiment may be similar to those of the first embodiment. Therefore, the second embodiment can obtain similar effects to those of the first embodiment.

[0249] (Third Implementation Method)

[0250] Fig.11 1 is a circuit diagram showing a configuration example of a pixel PX, an SH unit 125, and a comparator 121 according to a third embodiment. In the third embodiment, the configuration of the comparator 121 is different from that of the first embodiment. Other configurations of the third embodiment may be similar to those of the first embodiment.

[0251] The comparator 121a includes p-type transistors Tp2, Tp11, and Tp12, n-type transistors Tn3, Tn11, and Tn12, capacitors Cvs1, Cref, and C1a, AZ switches SwAZ1 and SwAZ2, and a constant current source Cs121a.

[0252] One end of the capacitors Cvs1 and Cref is connected to the output of the SH section 125 and the reference signal line 114, respectively. The other ends of the capacitors Cvs1 and Cref are commonly connected to the gate of the transistor Tp11. When the voltage level of the added signal of the pixel signal VSL and the reference signal RAMP exceeds the reference voltage, the transistor Tp11 switches between the conducting state and the non-conducting state.

[0253] Transistors Tn11, Tn12, Tp11 and Tp12 and constant current source Cs121a constitute a differential circuit. When transistor Tp11 switches between a conducting state and a non-conducting state, transistor Tp12 causes a predetermined current to flow similarly to transistor Tp11, so that the voltage level of node N121a between transistor Tp12 and transistor Tn12 is reversed. That is, when the voltage level of the added signal of the pixel signal and the reference signal exceeds the reference voltage, the comparator 121a reverses the voltage level of node N121a. Transistors Tn11 and Tn12 constitute a current mirror circuit, and cause a current corresponding to a predetermined mirror ratio to flow through transistors Tp11 and Tp12, respectively. Constant current source Cs121a maintains the total current flowing through transistors Tp11 and Tp12 at a predetermined value.

[0254] The capacitor C1a is connected between the gate of the transistor Tp12 and a predetermined voltage source, and sets the gate voltage of the transistor Tp12 to an auto-zero potential.

[0255] The AZ switch SwAZ1 is connected between the gate and drain of the transistor Tp11 , and performs an auto-zero operation by making the potential between the gate and drain of the transistor Tp11 equal before detecting the output signal of the SH section 125 .

[0256] The AZ switch SwAZ2 is connected between the gate and drain of the transistor Tp12 , and performs an auto-zero operation by making the potential between the gate and drain of the transistor Tp12 equal before detecting the output signal of the SH section 125 .

[0257] The transistor Tn3 functions as an amplifier that receives the potential of the node N121a at the gate, amplifies its voltage level, and outputs the amplified voltage level to the output circuit 121b. The transistor Tp2 functions as a constant current source that determines the current flowing through the transistor Tn3.

[0258] The output circuit 121b includes p-type transistors Tp3 to Tp5 and n-type transistors Tn4 to Tn6. Transistors Tp4 and Tn4 are used as inverter circuits, and transistors Tp5 and Tn6 are also used as inverter circuits. The gates of transistors Tp3 and Tn5 are connected in common and are at a low level when counting, but the output terminal OUT121 is fixed to a high level when not counting. Therefore, the output circuit 121b inverts the output signal from the input comparison circuit 121a twice through two inverter circuits, and outputs the inverted signal.

[0259] When the voltage level of the output of the input comparison circuit 121a is inverted, the voltage level of the output terminal OUT121 of the comparator 121 is inverted via the transistors Tp4 and Tn4 and the transistors Tp5 and Tn6. The inversion of the output terminal OUT121 serves to stop the operation of the counter 122. This enables AD conversion.

[0260] The other configurations and operations of the third embodiment may be similar to those of the first embodiment. Therefore, the third embodiment can obtain similar effects to those of the first embodiment.

[0261] (Fourth Implementation Method)

[0262] Fig.12 1 is a circuit diagram showing a configuration example of the SH portion 125 according to the fourth embodiment. The fourth embodiment is different from the other embodiments in the configuration of the SH portion 125. The configuration of the fourth embodiment other than the SH portion 125 may be similar to that of the other embodiments. Fig.12 In FIG. 1 , only the structure of the SH portion 125 is shown, and illustration of other structures is omitted.

[0263] (Configuration and Function of First Holding Circuit SHC1)

[0264] The first holding circuit SHC1 includes a capacitor Cp1, a transistor Tr1, a switch Sw1, and a constant current source Cs1.

[0265] One end of the capacitor Cp1 is connected to the pixel PX via the switch Sw1, and the capacitor Cp1 can accumulate a pixel signal. In addition, one end of the capacitor Cp1 is connected to the gate of the transistor Tr1. The other end of the capacitor Cp1 is connected to the ground GND.

[0266] The gate of transistor Tr1 is connected to one end of capacitor Cp1. The drain of transistor Tr1 is connected to power supply VDD, and its source (node ​​Nshc1) is connected to constant current source Cs1 and multiplexer MUX. Constant current source Cs1 is connected between the source (node ​​Nshc1) of transistor Tr1 and ground GND, and causes a constant current to flow through transistor Tr1. Transistor Tr1 causes a current depending on the potential of the gate (node ​​Ng1) to flow between the drain and the source. Therefore, the source (node ​​Nshc1) of transistor Tr1 has a potential corresponding to the potential of the gate (node ​​Ng1) of transistor Tr1. Node Nshc1 is connected to multiplexer MUX, and the voltage of node Nshc1 is output as an output signal OUTshc1 of the first holding circuit SHC1. Transistor Tr1 is used as a source follower circuit.

[0267] The switch Sw1 is connected between one end (node ​​Ng1) of the capacitor Cp1 and the pixel PX. When the first holding circuit SHC1 samples the pixel signal from the pixel PX to the capacitor Cp1, the switch Sw1 is turned on. Therefore, the pixel signal is accumulated in the capacitor Cpl, and therefore, the gate (node ​​Ng1) of the transistor Tr1 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switch Sw1 is turned off. Therefore, the pixel signal is accumulated and held in the capacitor Cpl. At this time, the transistor Tr1 enters a conduction state corresponding to the pixel signal, and the drain (node ​​Nshc1) of the transistor Tr1 is maintained at a potential corresponding to the pixel signal. Therefore, the first holding circuit SHC1 outputs the output signal OUTshc1 corresponding to the pixel signal from the node Nshc1 to the multiplexer MUX.

[0268] (Configuration and Function of Second Holding Circuit SHC2)

[0269] The configuration of the second holding circuit SHC2 may be the same as that of the first holding circuit SHC1. With respect to the description of the first holding circuit SHC1 of the fourth embodiment, it is only necessary to replace the capacitor Cp1 with the capacitor Cp2, replace the transistor Tr1 with the transistor Tr2, replace the switch Sw1 with the switch Sw2, replace the constant current source Cs1 with the constant current source Cs2, replace the node Ng1 with the node Ng2, and replace the node Nshc1 with the node Nshc2.

[0270] When the second holding circuit SHC2 samples the pixel signal from the pixel PX to the capacitor Cp2, the switch Sw2 is turned on. Therefore, the pixel signal is accumulated in the capacitor Cp2, and therefore, the gate (node ​​Ng2) of the transistor Tr2 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp2 holds the pixel signal, the switch Sw2 is turned off. Therefore, the pixel signal is accumulated and held in the capacitor Cp2. At this time, the transistor Tr2 enters a conduction state corresponding to the pixel signal, and the drain (node ​​Nshc2) of the transistor Tr2 is maintained at a potential corresponding to the pixel signal. Therefore, the second holding circuit SHC2 outputs the output signal OUTshc2 corresponding to the pixel signal from the node Nshc2 to the multiplexer MUX. The capacitors Cp1 and Cp2 sample and hold the pixel signal at different times.

[0271] As described above, even if the first holding circuit SHC1 and the second holding circuit SHC2 are configured by passive elements, the first holding circuit SHC1 and the second holding circuit SHC2 can perform the operation of the present disclosure. Therefore, the circuit scale and layout area of ​​the SH portion 125 can be reduced.

[0272] (Fifth Implementation Method)

[0273] Fig.13 1 is a circuit diagram showing a configuration example of the SH portion 125 according to the fifth embodiment. The fifth embodiment is different from the other embodiments in the configuration of the SH portion 125. The configuration of the fifth embodiment other than the SH portion 125 may be similar to that of the other embodiments. Fig.13 In FIG. 1 , only the structure of the SH portion 125 is shown, and illustration of other structures is omitted.

[0274] (Configuration and Function of First Holding Circuit SHC1)

[0275] The first holding circuit SHC1 includes a capacitor Cp1 and a switch Sw1. One end of the capacitor Cp1 is connected to the pixel PX via the switch Sw1, and the capacitor Cpl can accumulate a pixel signal. In addition, one end of the capacitor Cp1 as a node Nshc1 is connected to the multiplexer MUX. The other end of the capacitor Cp1 is connected to the ground GND.

[0276] The switch Sw1 is connected between the node Nshc1 and the pixel PX. When the first holding circuit SHC1 samples the pixel signal from the pixel PX to the capacitor Cp1, the switch Sw1 is turned on. Therefore, the pixel signal is accumulated in the capacitor Cpl, and therefore, the node Nshc1 is set to the potential of the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switch Sw1 is turned off. Therefore, the pixel signal is accumulated and held in the capacitor Cpl. At this time, the node Nshc1 is held at a potential corresponding to the pixel signal. Therefore, the first holding circuit SHC1 outputs the output signal OUTshc1 corresponding to the pixel signal from the node Nshc1 to the multiplexer MUX.

[0277] (Configuration and Function of Second Holding Circuit SHC2)

[0278] The second holding circuit SHC2 may be constructed in the same manner as the first holding circuit SHC1, except that capacitor Cp1 is replaced with capacitor Cp2, switch Sw1 is replaced with switch Sw2, and node Nshc1 is replaced with node Nshc2.

[0279] When the second holding circuit SHC2 samples the pixel signal from the pixel PX to the capacitor Cp2, the switch Sw2 is turned on. Therefore, the pixel signal is accumulated in the capacitor Cp2, and therefore, the node Nshc2 is set to the potential of the pixel signal. On the other hand, when the capacitor Cp2 holds the pixel signal, the switch Sw2 is turned off. Therefore, the pixel signal is accumulated and held in the capacitor Cp2. At this time, the node Nshc2 holds the potential corresponding to the pixel signal. Therefore, the second holding circuit SHC2 outputs the output signal OUTshc2 corresponding to the pixel signal from the node Nshc2 to the multiplexer MUX.

[0280] As described above, the first holding circuit SHC1 and the second holding circuit SHC2 can be configured by passive elements, and the source follower circuit can be omitted. Therefore, the circuit scale and layout area of ​​the SH portion 125 can be further reduced.

[0281] (Sixth Implementation Method)

[0282] Fig.14 is a circuit diagram showing a configuration example of a pixel PX according to the sixth embodiment. The sixth embodiment is different from the other embodiments in the configuration of the pixel PX. The configuration of the sixth embodiment other than the pixel PX may be similar to the other embodiments. Fig.14 , only the configuration of the pixel PX is shown, and illustration of other configurations is omitted.

[0283] In the sixth embodiment, each pixel PX includes only one photoelectric conversion unit PD, and the sensitivity is constant. However, the pixel PX includes a capacitor Cpx, and the capacitance of the floating diffusion FD can be changed. Therefore, the pixel PX can change the conversion efficiency of the pixel signal. In addition, the exposure time of the pixel PX can be changed.

[0284] Therefore, in the pixel PX of the sixth embodiment, it is not possible to obtain Figure 8 However, high-sensitivity reset signals NH1 and NH2, high-sensitivity data signals SH1 and SH2, short-time high-sensitivity reset signal NH2DOL, and short-time high-sensitivity data signal SH2DOL can be obtained as other signals. Therefore, even in the pixel PX of the sixth embodiment, the dynamic range can be expanded.

[0285] (Application example of mobile object)

[0286] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, a robot, etc.

[0287] Fig.15 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0288] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.15 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0289] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle, etc.

[0290] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, radio waves transmitted from a portable device as a substitute for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, and lights of the vehicle.

[0291] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing on objects such as people, vehicles, obstacles, signs, or symbols on the road surface, or detection processing of the distance to these objects.

[0292] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0293] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0294] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle (the information is obtained by the outside information detection unit 12030 or the inside information detection unit 12040), and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform the coordinated control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes: collision avoidance or collision mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or vehicle lane departure warning, etc.

[0295] In addition, the microcomputer 12051 can perform collaborative control intended for autonomous driving, which enables the vehicle to drive autonomously by controlling a driving force generating device, a steering mechanism, or a braking device, etc. based on information about the interior or exterior of the vehicle (the information is obtained by the exterior information detection unit 12030 or the interior information detection unit 12040), without relying on the driver's operation.

[0296] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 based on information about the exterior of the vehicle, which information is obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the exterior information detection unit 12030.

[0297] The audio and video output unit 12052 transmits an output signal of at least one of audio and video to an output device that can visually or auditorily notify the vehicle's passengers or the outside of the vehicle of the information. Fig.15 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0298] Fig.16 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0299] exist Fig.16 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0300] The camera units 12101, 12102, 12103, 12104 and 12105 are, for example, arranged at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper part of the windshield inside the vehicle. The camera unit 12101 arranged on the front nose and the camera unit 12105 arranged on the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged on the side mirrors mainly obtain images on the sides of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or rear door mainly obtains images at the rear of the vehicle 12100. The camera unit 12105 arranged on the upper part of the windshield inside the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signals, traffic signs or lanes, etc.

[0301] Notice, Fig.16An example of the photographing range of the camera units 12101 to 12104 is shown. The photographing range 12111 indicates the photographing range of the camera unit 12101 provided to the front nose. The photographing ranges 12112 and 12113 respectively indicate the photographing ranges of the camera units 12102 and 12103 provided to the side mirrors. The photographing range 12114 indicates the photographing range of the camera unit 12104 provided to the rear bumper or the rear door. For example, by superimposing the image data photographed by the camera units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0302] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0303] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object as the leading vehicle, in particular, the three-dimensional object exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control intended for automatic driving can be performed, which allows the vehicle to travel autonomously without relying on the driver's operation, etc.

[0304] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the camera units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk representing the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0305] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by a program that extracts feature points in the captured images of the camera units 12101 to 12104 that are infrared cameras and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points that represent the outline of an object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound image output unit 12052 may also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

[0306] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the camera unit 12031 and the like among the components described in this specification.

[0307] Typically, an in-vehicle CIS requires a dynamic range of, for example, 120 dB or more, which corresponds to a range from sunlight to starlight. In this case, multiple photodiodes are provided in each pixel PX, the conversion efficiency of the pixel signal is changed, or the exposure time is changed, thereby expanding the dynamic range of the pixel PX. However, in order to obtain a pixel signal in HDR, it is necessary to perform AD conversion on multiple pixel signals from one pixel PX. Applying the solid-state imaging device 100 according to the above-described embodiment to the imaging section 12031, etc. enables the pixel signal to be read out from such a pixel PX with HDR at a short frame rate.

[0308] (Seventh Implementation Plan)

[0309] Fig.17 1 is a block diagram showing a configuration example of a solid-state imaging device 100 according to a seventh embodiment. The solid-state imaging device 100 of the seventh embodiment further includes a clamp voltage generating circuit 400. The clamp voltage generating circuit 400 is provided in common for the SH sections 125 of a plurality of columns, and applies a predetermined first voltage VgCL (see FIG. 1 ) to the plurality of SH sections 125. Fig.18 ).

[0310] Fig.18 is a circuit diagram showing a configuration example of an SH section 125 according to the seventh embodiment. Fig.18 , the internal configuration of the first holding circuit SHC1 of the SH portion 125 is shown, and the configurations of the second holding circuit SHC2 and the multiplexer MUX are not shown. The internal configuration of the second holding circuit SHC2 may be similar to that of the first holding circuit SHC1.

[0311] The first holding circuit SHC1 according to the seventh embodiment further includes a clamp transistor TnCL and a clamp switch SwCL. The configuration of the first holding circuit SHC1 according to the seventh embodiment other than these parts may be similar to that of the first holding circuit SHC1 according to the first embodiment.

[0312] The clamp transistor TnCL and the clamp switch SwCL are connected in series between the power supply VDD and the node Nshc1, and are connected in parallel with the constant current source Cs1. The clamp transistor TnCL is, for example, an n-type transistor. The drain of the clamp transistor TnCL is connected to the power supply VDD via the clamp switch SwCL. The source of the clamp transistor TnCL is connected to the node Nshc1. The gate of the clamp transistor TnCL is connected to the Fig.17 The clamping voltage generating circuit 400 is provided and a predetermined first voltage VgCL is received from the clamping voltage generating circuit 400.

[0313] The clamp switch SwCL is controlled to be turned on and off by the clamp enable signal CL_en from the timing control circuit 102. When the clamp switch SwCL enters the on state, the clamp transistor TnCL is connected between the power supply VDD and the node Nshc1. Therefore, the clamp transistor TnCL constitutes a source follower circuit, and the voltage of the node Nshc1 is set (clamped) to a clamp voltage Vclamp corresponding to the first voltage VgCL. For example, when the threshold voltage of the clamp transistor TnCL is VtCL, the clamp voltage Vclamp of the node Nshc1 is set (clamped) to VgCL-VtCL.

[0314] The reason why the clamp transistor TnCL is provided is as follows.

[0315] In the case where high brightness light such as the sun is incident on the pixel PX, even when Figure 3 When the first transfer gate portion T12a is in a non-conductive state, a large amount of charge is also generated in the first photoelectric conversion portion PD11a, and the first FD portion FD15a overflows the charge. In this case, the pixel signal VSL of the vertical signal line 110 is in an over-range state exceeding one of the minimum value and the maximum value, and the reset signal and the data signal become equal, so the image becomes black.

[0316] In order to suppress this blackening of the image, when high-brightness light is incident, the pixel signal VSL is clamped at a predetermined clamping voltage Vclamp in the automatic zeroing period of the comparator 121. The clamping voltage Vclamp is a voltage between the reset signal and the pixel signal VSL in the over-range state caused by the high-brightness light. In addition, the clamping voltage Vclamp is pre-set so that the reference signal RAMP when detecting the reset signal does not intersect with the pixel signal VSL in the over-range state caused by the high-brightness light. Therefore, in the automatic zeroing period when high-brightness light is incident, the reference signal RAMP is clamped to be substantially equal to the clamping voltage Vclamp. Then, the reset signal and the data signal are detected as usual. At this time, when the pixel signal VSL is in an over-range state exceeding the minimum value (or maximum value), the reference signal RAMP does not intersect with the pixel signal VSL and cannot be detected. In this way, in the case where the reset signal cannot be detected, the signal processing circuit 108 determines that high brightness light such as the sun is incident on the pixel PX, and sets the image to white or the like (full encoding). Therefore, it is possible to suppress the blackening of the image by high brightness light such as the sun. Note that in the present embodiment, it will be described assuming that the pixel signal VSL enters an over-range state exceeding the minimum value when high brightness light is incident.

[0317] In the seventh embodiment, after the first holding circuit SHC1 samples and holds the pixel signal VSL, the comparator 121 performs an auto-zero operation. In order to clamp the reference signal RAMP to a predetermined voltage in the auto-zero operation, a clamp transistor TnCL and a clamp switch SwCL are provided at a node Nshc1 between the output of the first holding circuit SHC1 and the input of the comparator 121. Therefore, the clamp transistor TnCL and the clamp switch SwCL can clamp the output signal OUTshc1 of the first holding circuit SHC1 to a clamp voltage Vclamp (Vclamp=VgCL-VtCL). Therefore, even if the pixel signal sampled by the first holding circuit SHC1 is in an out-of-range state due to high-brightness light, the clamp transistor TnCL and the clamp switch SwCL clamp the output signal OUTshc1 to the clamp voltage Vclamp so that the reference signal RAMP does not cross the pixel signal VSL. Therefore, the signal processing circuit 108 can determine that high-brightness light such as the sun is incident on the pixel PX, and can suppress blackening of the high-brightness light in the image.

[0318] Fig.19 1 is a timing chart showing an operation example of the first holding circuit SHC1 and the comparator 121 detecting a reset signal according to the seventh embodiment.

[0319] First, at t1, the signal Sample and the signal AZ_sh reach a high level, and the switches Sw1 and Sw3 are turned on. The signal CL remains at a low level, and the switch Sw2 remains in an off state. Therefore, the first holding circuit SHC1 samples the pixel signal VSL. The sampling period is t1 to t2.

[0320] When the charge of the FD portion overflows due to high-brightness light, the pixel signal VSL is in an over-range state exceeding the voltage Vlim_L, which is the minimum value, for example. At this time, the output signal OUTshc1 and the voltage of the node Ng also become the voltage Vlim_L.

[0321] At t2 , when the signal Sample and the signal AZ_sh are brought to a low level, the switches Sw1 and Sw3 are turned off, and the sampling period ends.

[0322] At t3, the signal CL reaches a high level and turns on the switch Sw2. Therefore, the output voltage OUTshc1 of the nodes Nshc1 and Ng is maintained at the voltage Vlim_L.

[0323] At t4, the auto-zero operation of the comparator 121 is performed. The signal AZ_cm reaches a high level, and the switch SwAZ of the comparator 121 is turned on. At approximately the same time, the clamp enable signal CL_en reaches a high level, and the clamp switch SwCL is turned on. Therefore, the output voltage OUTshc1 is set to the clamp voltage Vclamp (Vclamp=VgCL-VtCL). In the auto-zero operation of the comparator 121, the output voltage OUTshc1 is set to a predetermined clamp voltage Vclamp, so that the reset voltage Vrst increases the clamp voltage Vsclamp. Therefore, the voltage of the entire reference signal RAMP is also increased. Therefore, it is possible to prevent the reference signal RAMP from crossing the output voltage OUTshc1 that is reduced to the voltage Vlim_L as the minimum value by the high brightness light.

[0324] For example, Fig. 20 : is a timing chart showing the relationship between the voltage of the output voltage OUTshc1 and the reference signals RAMP1 and RAMP2. The reference signal RAMP1 represents the reference signal when there is no clamp voltage Vclamp (Vclamp=0). The reference signal RAMP2 represents the reference signal when there is a clamp voltage Vclamp (Vclamp is not 0).

[0325] In the auto-zero operation from t4 to t5, the reference signal RAMP1 is not clamped by the clamp voltage Vclamp (Vclamp=0), and is therefore set to the level of the voltage Vlim_L. Therefore, the time between t6 and t6_1 from the detection start t6 of the reset signal Sp to the time point t6_1 at which the reference signal RAMP1 crosses the output signal OUTshc1 is substantially equal to the time between t6_2 and t6_3 from the detection start t6_2 of the data signal Sd1 to the time point t6_3 at which the reference signal RAMP1 crosses the output signal OUTshc1. That is, the reset signal Sp and the data signal Sd are substantially equal. In this case, the image is made black by the CDS process.

[0326] On the other hand, the reference signal RAMP2 indicates a reference signal when the clamp voltage Vclamp exists (Vclamp is not 0).

[0327] In this case, in the auto-zero operation from t4 to t5, the reference signal RAMP2 is clamped at a predetermined clamping voltage Vclamp (Vclamp is not 0) and is set to the level of the voltage Vlim_L+Vclamp. Therefore, in the detection period of the reset signal Sp from t6 to t6_2, the reference signal RAMP2 does not cross the output signal OUTshc1. That is, the reset signal Sp is not detected. The signal processing circuit 108 fully encodes the pixel signal under the condition that the reset signal Sp is not detected. Therefore, it is possible to suppress the image from becoming black due to high brightness light. Note that although the data signal Sd2 is detected as the time from t6_3 to t6_4 (i.e., from the detection start t6_2 to the time point t6_4 when the reference signal RAMP2 crosses the output signal OUTshc1), the data signal Sd2 may be used or not used under the condition of full encoding of the pixel signal.

[0328] Therefore, the signal processing circuit 108 can determine that high brightness light is incident on the pixel PX, and can suppress the darkening of the image due to the high brightness light. That is, according to the seventh embodiment, even when the SH portion 125 is provided, the darkening of the image due to the high brightness light can be suppressed.

[0329] Note that although the reference signal RAMP is tilted downward in the seventh embodiment, the reference signal RAMP may be tilted upward. In addition, the detection order of the reset signal Sp and the data signal Sd may be reversed.

[0330] (Eighth Implementation Plan)

[0331] Fig.21 1 is a circuit diagram showing a configuration example of a pixel PX, an SH section 125, and a comparator 121 according to an eighth embodiment. The eighth embodiment is an embodiment in which the SH section 125 according to the seventh embodiment is applied to each of the first holding circuit SHC1 and the second holding circuit SHC2 of the first embodiment. Each of the first holding circuit SHC1 and the second holding circuit SHC2 has a configuration similar to that of the first holding circuit SHC1 of the seventh embodiment. The comparator 121 has the same configuration as that of the comparator 121 of the first embodiment. For convenience, the clamp switch SwCL and the clamp transistor TnCL of the first holding circuit SHC1 are referred to as the clamp switch SwCL1 and the clamp transistor TnCL1, respectively. The clamp switch SwCL and the clamp transistor TnCL of the second holding circuit SHC2 are referred to as the clamp switch SwCL2 and the clamp transistor TnCL2, respectively.

[0332] The first holding circuit SHC1 further includes a clamp transistor TnCL1 and a clamp switch SwCL1 connected in series between the power supply VDD and the drain of the transistor Tr1. The clamp transistor TnCL1 and the clamp switch SwCL1 are connected in parallel with the constant current source Cs1. The second holding circuit SHC2 further includes a clamp transistor TnCL2 and a clamp switch SwCL2 connected in series between the power supply VDD and the drain of the transistor Tr2. The clamp transistor TnCL2 and the clamp switch SwCL2 are connected in parallel with the constant current source Cs2.

[0333] Furthermore, as described above, although the first holding circuit SHC1 and the second holding circuit SHC2 according to the eighth embodiment are different from each other in operation timing, each of the first holding circuit SHC1 and the second holding circuit SHC2 basically operates similarly to the first holding circuit SHC1 of the seventh embodiment. The operation of the comparator 121 according to the eighth embodiment can be similar to the operation of the comparator 121 of the first embodiment. Therefore, according to the eighth embodiment, the effects of the first embodiment and the seventh embodiment can be obtained.

[0334] Fig. 22 1 is a timing diagram showing an operation example of the first holding circuit SHC1 and the second holding circuit SHC2 and the comparator 121 detecting the reset signal Sp and the data signal Sd according to the eighth embodiment. Note that in this embodiment, the reference signal RAMP has an upward slope. In addition, Fig. 22 In the upper part of FIG. 1 , signals Sw1 to Sw3 and SwCL1 of the first holding circuit SHC1 are shown, and in the lower part, signals Sw4 to Sw6 and SwCL2 of the second holding circuit SHC2 are shown.

[0335] First, at t11, the switches Sw1 and Sw3 are turned on. The switch Sw2 is kept in an off state. Therefore, the first holding circuit SHC1 starts sampling the pixel signal VSL.

[0336] When the charge in the FD portion overflows due to high-brightness light, the pixel signal VSL is in an over-range state exceeding the voltage Vlim_L as the minimum value, for example. At this time, the output signal OUTshc1 and the voltage of the node Ng1 also become the voltage Vlim_L.

[0337] At t12 , the switches Sw1 and Sw3 are turned off, and the sampling period of the pixel signal VSL ends.

[0338] At t13, the switches Sw4 and Sw6 of the second holding circuit SHC2 are turned on. The switch Sw5 is kept in an off state. Therefore, the second holding circuit SHC2 starts sampling the pixel signal VSL.

[0339] At t14, the switch Sw2 of the first holding circuit SHC1 is turned on, and the first holding circuit SHC1 holds the output signal OUTshc1. At this time, the output signal OUTshc1 is held at the voltage Vlim_L. In addition, the selection signal SEL_SHC1 is selectively activated, and the multiplexer MUX outputs the output signal OUTshc1 of the first holding circuit SHC1 to the comparator 121.

[0340] At t15, the clamp switch SwCL1 and the auto-zero switch SwAZ are turned on. Therefore, the auto-zero operation of the comparator 121 is performed, and the transistor TnCL1 sets the drain of the transistor Tr1 to the clamp voltage Vclamp corresponding to the first voltage VgCL. Therefore, the output signal OUTshc1 of the first holding circuit SHC1 is clamped by the clamp voltage Vclamp. In the state where the output signal OUTshc1 is clamped to the voltage (Vlim_L+Vclamp), the auto-zero operation of the comparator 121 is performed. The auto-zero operation of the present embodiment will be described later.

[0341] At t16, the clamp switch SwCL1 and the auto-zero switch SwAZ are turned off. Therefore, the auto-zero operation and the clamp operation of the comparator 121 are ended. Therefore, the output signal OUTshc1 returns to the voltage Vlim_L.

[0342] From t16 to t17, the first holding circuit SHC1 holds the output signal OUTshc1 at the voltage Vlim_L, and the comparator 121 attempts to detect the voltage Vlim_L as the reset signal Sp. However, in the auto-zero operation from t15 to t16, the output signal OUTshc1 is set to the clamping voltage Vclamp. Therefore, as will be referred to later Fig.23 As described above, the voltage Vlim_L in the over-range state due to the high-brightness light does not cross the clamped reference signal RAMP, and the reset signal Sp is not detected. The signal processing circuit 108 determines that the high-brightness light is incident based on the fact that the reset signal Sp needs to be detected.

[0343] At t17 , the switch Sw2 is turned off to release the holding state of the output signal OUTshc1 by the first holding circuit SHC1 , and the switch Sw4 is turned off to end the sampling period of the second holding circuit SHC2 .

[0344] At t18, the switch Sw5 of the second holding circuit SHC2 is turned on, and the second holding circuit SHC2 holds the output signal OUTshc2. At this time, the output signal OUTshc2 is held at the voltage Vlim_L. In addition, the selection signal SEL_SHC2 is selectively activated, and the multiplexer MUX outputs the output signal OUTshc2 of the second holding circuit SHC1 to the comparator 121.

[0345] From t18 to t19 , the second hold circuit SHC2 holds the output signal OUTshc2 at the voltage Vlim_L, and the comparator 121 detects the voltage Vlim_L as the data signal Sd.

[0346] Fig.23 OUTshc1 is a timing diagram showing the relationship between the output voltage OUTshc1 and the gate signals GATE1 and GATE2. The gate signal GATE1 represents the gate signal (comparator input: comparison reference signal) of the transistor Tp1 when the clamping voltage Vclamp (Vclamp=0) is not applied. The gate signal GATE2 represents the gate signal (comparator input: comparison reference signal) of the transistor Tp1 when the clamping voltage Vclamp (Vclamp is not 0) is applied. Therefore, each of the gate signals GATE1 and GATE2 is a capacitance addition signal of the reference signal RAMP and the signal input to the capacitor Cvsl. Note that in the present embodiment, the reference signal RAMP has an upward inclination, and the gate signals GATE1 and GATE2 similarly have an upward inclination.

[0347] In the auto-zero operation from t14 to t15, the gate signal GATE1 is not clamped by the clamp voltage Vclamp (Vclamp=0), and is therefore set to the level of the voltage Vlim_L. Therefore, the time t16_1 to t16_2 from the detection start t16_1 of the reset signal Sp to the inversion reference point t16_2 at which the gate signal GATE1 crosses the output signal OUTshc1 is substantially equal to the time t18 to t18_1 from the detection start t18 of the data signal Sd1 to the moment t18_1 at which the gate signal GATE1 crosses the output signal OUTshc1. That is, the reset signal Sp and the data signal Sd are substantially equal. In this case, the image is made black by the CDS process.

[0348] On the other hand, the gate signal GATE2 indicates the gate signal of the transistor Tp1 when the clamp voltage Vclamp exists (Vclamp is not 0).

[0349] In this case, in the auto-zero operation from t14 to t15, the gate signal GATE2 is clamped at a predetermined clamping voltage Vclamp (Vclamp is not 0) and is set to the level of the voltage Vlim_L-Vclamp. Therefore, in the detection period of the reset signal Sp from t16_1 to t17, the gate signal GATE2 does not cross the output signal OUTshc1. That is, the reset signal Sp is not detected. The signal processing circuit 108 fully encodes the pixel signal under the condition that the reset signal Sp is not detected. Therefore, it is possible to suppress the image from being blackened due to high brightness light. Note that although the data signal Sd2 is detected as the time from t18 to t18_2, that is, from the detection start t18 to the time point t18_2 when the gate signal GATE2 crosses the output signal OUTshc1, the data signal Sd2 may be used or not used under the condition of full encoding of the pixel signal.

[0350] Therefore, the signal processing circuit 108 can determine that high-brightness light is incident on the pixel PX, and can suppress the blackening of the image due to the high-brightness light. That is, according to the eighth embodiment, even in the case where the first holding circuit SHC1 holds the reset signal Sp and the second holding circuit SHC2 holds the data signal Sd, it is possible to suppress the blackening of the image due to the high-brightness light.

[0351] Note that in the eighth embodiment, the detection order of the reset signal Sp and the data signal Sd may be reversed. In this case, in the auto-zero operation, when the clamp switch SwCL2 of the second holding circuit SHC2 is turned on, the clamp transistor TnCL2 may set the drain of the transistor Tr2 to the clamp voltage Vclamp. In this case, when the output signal OUTshc2 from the clamp transistor TnCL2 is detected, the reference signal RAMP is clamped.

[0352] The eighth embodiment can be applied to the readout of each of the high-sensitivity reset signal NH2, the high-sensitivity reset signal NH1, the high-sensitivity data signal SH1, the high-sensitivity data signal SH2, the low-sensitivity data signal SL and the low-sensitivity reset signal NL. Therefore, in the eighth embodiment, the images of these signals can be suppressed from becoming black due to high-brightness light.

[0353] (Ninth Implementation Plan)

[0354] Fig.241 is a circuit diagram showing a configuration example of a pixel PX, an SH unit 125, and a comparator 121 according to a ninth embodiment. The ninth embodiment is an embodiment in which the SH unit 125 according to the seventh embodiment is applied to the second embodiment. Each of the first holding circuit SHC1 and the second holding circuit SHC2 has the same configuration as the first holding circuit SHC1 of the seventh embodiment. The comparator 121 has the same configuration as the comparator 121 of the second embodiment.

[0355] Although the operations of the first holding circuit SHC1 and the second holding circuit SHC2 according to the ninth embodiment are different from each other in operation timing, each of the first holding circuit SHC1 and the second holding circuit SHC2 basically operates similarly to the first holding circuit SHC1 of the seventh embodiment. The operation of the comparator 121 according to the ninth embodiment is similar to the operation of the comparator 121 of the second embodiment. Therefore, according to the ninth embodiment, the effects of the second embodiment and the seventh embodiment can be obtained.

[0356] (Tenth Implementation Plan)

[0357] Fig.25 1 is a circuit diagram showing a configuration example of a pixel PX, an SH unit 125, and a comparator 121 according to a tenth embodiment. The tenth embodiment is an embodiment in which the SH unit 125 according to the seventh embodiment is applied to the third embodiment. Each of the first holding circuit SHC1 and the second holding circuit SHC2 has the same configuration as the first holding circuit SHC1 of the seventh embodiment. The comparator 121 has the same configuration as the comparator 121 of the third embodiment.

[0358] Although the operations of the first holding circuit SHC1 and the second holding circuit SHC2 according to the tenth embodiment are different from each other in operation timing, the respective operations are basically similar to those of the first holding circuit SHC1 of the seventh embodiment. The operation of the comparator 121 according to the tenth embodiment may be similar to the operation of the comparator 122 of the third embodiment. Therefore, according to the tenth embodiment, the effects of the third embodiment and the seventh embodiment can be obtained.

[0359] (Eleventh Implementation Plan)

[0360] Fig.26 1 is a circuit diagram showing a configuration example of the SH unit 125 according to the eleventh embodiment. The eleventh embodiment is an embodiment in which the SH unit 125 according to the seventh embodiment is applied to the fourth embodiment.

[0361] The respective operations of the SH portion 125 according to the eleventh embodiment are basically similar to those of the SH portion 125 of the seventh embodiment. Therefore, according to the eleventh embodiment, the effects of the fourth embodiment and the seventh embodiment can be obtained.

[0362] Note that the present technology can have the following configurations.

[0363] (1) A solid-state imaging device comprising:

[0364] a pixel portion including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal;

[0365] an AD conversion unit that converts the pixel signal from the pixel unit into a digital signal;

[0366] a first holding circuit provided between the pixel portion and the AD conversion portion and holding the pixel signal;

[0367] a second holding circuit provided between the pixel portion and the AD conversion portion and holding the pixel signal; and

[0368] A selection circuit capable of connecting any one of the first holding circuit and the second holding circuit to the AD conversion section and selectively transmitting the pixel signal held in the first holding circuit or the second holding circuit to the AD conversion section.

[0369] (2) The solid-state imaging device according to (1), further comprising:

[0370] a bypass signal line, the bypass signal line being provided between the pixel portion and the AD conversion portion and transmitting the pixel signal as it is, wherein:

[0371] The selection circuit is capable of connecting any one of the first holding circuit, the second holding circuit and the bypass signal line to the AD conversion unit, and selectively transmitting the pixel signal held in the first holding circuit, the pixel signal held in the second holding circuit, or the pixel signal transmitted through the bypass signal line to the AD conversion unit.

[0372] (3) The solid-state imaging device according to (1) or (2), wherein:

[0373] The first holding circuit comprises:

[0374] a first capacitor having one end connected to the pixel portion, the first capacitor being capable of accumulating the pixel signal; and

[0375] a first transistor having a gate connected to the other end of the first capacitor and a drain connected to a current source and the selection circuit; and

[0376] The second holding circuit comprises:

[0377] a second capacitor having one end connected to the pixel portion, the second capacitor being capable of accumulating the pixel signal; and

[0378] The second transistor has a gate connected to the other end of the second capacitor and a drain connected to a current source and the selection circuit.

[0379] (4) The solid-state imaging device according to (3), wherein:

[0380] The first holding circuit comprises:

[0381] a first switch provided between the first capacitor and the pixel portion;

[0382] a second switch connected between a drain of the first transistor and the one end of the first capacitor; and

[0383] a third switch connected between a drain of the first transistor and the other end of the first capacitor; and

[0384] The second holding circuit comprises:

[0385] a fourth switch provided between the second capacitor and the pixel portion;

[0386] a fifth switch connected between a drain of the second transistor and the one end of the second capacitor; and

[0387] A sixth switch is connected between a drain of the second transistor and the other end of the second capacitor.

[0388] (5) The solid-state imaging device according to (4), wherein:

[0389] When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch and the third switch enter a conducting state and the second switch is in a non-conducting state,

[0390] When the first capacitor holds the pixel signal, the first switch and the third switch enter a non-conductive state and the second switch enters a conductive state,

[0391] When the pixel signal is sampled from the pixel portion to the second capacitor, the fourth switch and the sixth switch enter a conducting state, and the fifth switch is in a non-conducting state, and

[0392] When the second capacitor holds the pixel signal, the fourth switch and the sixth switch enter a non-conductive state, and the fifth switch enters a conductive state.

[0393] (6) The solid-state imaging device according to (5), wherein the first holding circuit and the second holding circuit sample the pixel signal at different timings.

[0394] (7) The solid-state imaging device according to (5) or (6), wherein:

[0395] The second holding circuit samples a second pixel signal among the pixel signals during a period in which the first holding circuit holds a first pixel signal among the pixel signals and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion section, and

[0396] The first holding circuit samples the other of the pixel signals during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion section.

[0397] (8) The solid-state imaging device according to (1) or (2), wherein:

[0398] The first holding circuit comprises:

[0399] a first capacitor having one end connected to the pixel portion and the other end connected to a reference voltage source, the first capacitor being capable of accumulating the pixel signal;

[0400] a first transistor having a gate connected to the one end of the first capacitor and a source connected to a current source and the selection circuit; and

[0401] The second holding circuit comprises:

[0402] a second capacitor having one end connected to the pixel portion and the other end connected to a reference voltage source, the second capacitor being capable of accumulating the pixel signal; and

[0403] A second transistor has a gate connected to the one end of the second capacitor and a source connected to a current source and the selection circuit.

[0404] (9) The solid-state imaging device according to (8), wherein:

[0405] The first holding circuit includes a first switch provided between the one end of the first capacitor and the pixel portion; and

[0406] The second holding circuit includes a second switch provided between the one end of the second capacitor and the pixel portion.

[0407] (10) The solid-state imaging device according to (9), wherein:

[0408] When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch enters an on state,

[0409] When the first capacitor holds the pixel signal, the first switch enters a non-conducting state,

[0410] When the pixel signal is sampled from the pixel portion to the second capacitor, the second switch enters an on state, and

[0411] When the second capacitor holds the pixel signal, the second switch enters a non-conductive state.

[0412] (11) The solid-state imaging device according to (10), wherein the first capacitor and the second capacitor sample the pixel signal at different timings.

[0413] (12) The solid-state imaging device according to (10) or (11), wherein:

[0414] The second holding circuit samples a second pixel signal among the pixel signals during a period in which the first holding circuit holds a first pixel signal among the pixel signals and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion section, and

[0415] The first holding circuit samples the other of the pixel signals during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion section.

[0416] (13) The solid-state imaging device according to any one of (1) to (12), further comprising:

[0417] a negative capacitance circuit connected to a first signal line connected between the pixel portion and the first holding circuit and the second holding circuit and transmitting the pixel signal, wherein:

[0418] The negative capacitance circuit comprises:

[0419] an amplifier having an input terminal connected to the first signal line; and

[0420] A capacitor is connected between the input terminal and an output terminal of the amplifier.

[0421] (14) The solid-state imaging device according to any one of (1) to (13), wherein each pixel of the pixel portion includes a first photoelectric conversion element and a second photoelectric conversion element having different light receiving areas.

[0422] (15) The solid-state imaging device according to any one of (1) to (14), wherein:

[0423] Each pixel of the pixel unit includes:

[0424] a first floating diffusion layer and a second floating diffusion layer, each of which accumulates charges from the photoelectric conversion element;

[0425] an amplifying transistor that outputs the pixel signal based on a potential of the first floating diffusion layer; and

[0426] a seventh switch, the seventh switch being disposed between the first floating diffusion layer and the second floating diffusion layer;

[0427] When the seventh switch enters a non-conductive state, the amplifying transistor outputs the pixel signal based on the potential of the first floating diffusion layer, and

[0428] When the seventh switch enters an on state, the amplification transistor outputs the pixel signal based on a potential of a region coupling the first floating diffusion layer and the second floating diffusion layer.

[0429] (16) The solid-state imaging device according to any one of (3) to (7), wherein:

[0430] The first holding circuit further includes:

[0431] a third transistor and an eighth switch connected in series between a power supply and a drain of the first transistor, and

[0432] The second holding circuit further includes:

[0433] A fourth transistor and a ninth switch are connected in series between the power supply and the drain of the second transistor.

[0434] (17) The solid-state imaging device according to (16), wherein:

[0435] The third transistor and the eighth switch are connected in parallel with the current source, and

[0436] The fourth transistor and the ninth switch are connected in parallel with the current source.

[0437] (18) The solid-state imaging device according to (16) or (17), further comprising:

[0438] A voltage generating circuit that applies a predetermined first voltage to the gates of the third transistor and the fourth transistor, wherein:

[0439] When the eighth switch is in an on state, the third transistor sets the drain of the first transistor to a clamping voltage corresponding to the first voltage, and

[0440] When the ninth switch is in an on state, the fourth transistor sets the drain of the second transistor to the clamping voltage.

[0441] (19) The solid-state imaging device according to any one of (16) to (18), wherein:

[0442] In an auto-zero operation of making the pixel signal held by the first holding circuit and compared in the AD conversion section equal to a reference signal, the eighth switch enters a conducting state, and

[0443] The ninth switch enters a conducting state in an auto-zero operation of making the pixel signal held by the second holding circuit and compared in the AD conversion section equal to the reference signal.

[0444] Note that the present disclosure is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present disclosure. In addition, the effects described in this specification are merely examples and are not restrictive, and other effects may be provided.

[0445] Reference numerals list

[0446] PX Pixel

[0447] 125 SH Department

[0448] 121 Comparator

[0449] SHC1 first holding circuit

[0450] SHC2 second holding circuit

[0451] BP bypass signal line

[0452] MUX Multiplexer

[0453] Cp1, Cp2 capacitors

[0454] Tr1, Tr2 transistors

[0455] Sw1 to Sw6 Switches

[0456] Cs1, Cs2 constant current source

Claims

1. A solid-state imaging device, comprising: a pixel portion including a photoelectric conversion element for photoelectrically converting incident light into a pixel signal; an AD conversion unit that converts the pixel signal from the pixel unit into a digital signal; a holding circuit provided between the pixel portion and the AD conversion portion and holding the pixel signal; and a selection circuit capable of selectively connecting any one of the pixel portion and the holding circuit to the AD conversion portion to selectively transfer the pixel signal from the pixel portion or the holding circuit to the AD conversion portion, wherein The holding circuit includes a first amplifying transistor, The pixel unit further includes: a first transmission gate portion, a floating diffusion portion connected to the pixel portion via the first transfer gate portion, a second transmission gate portion, a third transfer gate portion disposed between the floating diffusion portion and a first end of the second transfer gate portion, a capacitor connected to a second end of the second transmission gate portion, and A second amplifying transistor, a first terminal of the second amplifying transistor is connected to the floating diffusion and a second terminal of the second amplifying transistor outputs the pixel signal, and the second terminal of the second amplifying transistor is connected to the first amplifying transistor. 2 . The solid-state imaging device according to claim 1 , wherein the first transfer gate portion, the second transfer gate portion, and the third transfer gate portion each include a transistor.

3. The solid-state imaging device according to claim 1, wherein The holding circuit includes a first holding circuit that holds the pixel signal and a second holding circuit that holds the pixel signal, and The selection circuit is capable of selectively connecting any one of the first holding circuit, the second holding circuit, and the pixel portion to the AD conversion portion to selectively transfer the pixel signal from the first holding circuit, the second holding circuit, or the pixel portion to the AD conversion portion.

4. The solid-state imaging device according to claim 3, wherein: The first holding circuit comprises: a first capacitor having one end connected to the pixel portion, the first capacitor being capable of accumulating the pixel signal; and The first amplifying transistor has a gate connected to the other end of the first capacitor and a drain connected to a first current source and the selection circuit; and The second holding circuit comprises: a second capacitor having one end connected to the pixel portion, the second capacitor being capable of accumulating the pixel signal; and The second transistor has a gate connected to the other end of the second capacitor and a drain connected to a second current source and the selection circuit.

5. The solid-state imaging device according to claim 4, wherein: The first holding circuit comprises: a first switch provided between the first capacitor and the pixel portion; a second switch connected between a drain of the first amplifying transistor and the one end of the first capacitor; and a third switch connected between the drain of the first amplifying transistor and the other end of the first capacitor; and The second holding circuit comprises: a fourth switch provided between the second capacitor and the pixel portion; a fifth switch connected between a drain of the second transistor and the one end of the second capacitor; and A sixth switch is connected between a drain of the second transistor and the other end of the second capacitor.

6. The solid-state imaging device according to claim 5, wherein: When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch and the third switch enter a conducting state and the second switch is in a non-conducting state, When the first capacitor holds the pixel signal, the first switch and the third switch enter a non-conductive state and the second switch enters a conductive state, When the pixel signal is sampled from the pixel portion to the second capacitor, the fourth switch and the sixth switch enter a conducting state, and the fifth switch is in a non-conducting state, and When the second capacitor holds the pixel signal, the fourth switch and the sixth switch enter a non-conductive state, and the fifth switch enters a conductive state.

7. The solid-state imaging device according to claim 6, wherein: The first holding circuit and the second holding circuit sample the pixel signal at different times.

8. The solid-state imaging device according to claim 6, wherein: The second holding circuit samples a second pixel signal among the pixel signals during a period in which the first holding circuit holds a first pixel signal among the pixel signals and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion section, and The first holding circuit samples the other of the pixel signals during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion section.

9. The solid-state imaging device according to claim 3, wherein: The first holding circuit comprises: a first capacitor having one end connected to the pixel portion and the other end connected to a reference voltage source, the first capacitor being capable of accumulating the pixel signal; and the first amplifying transistor having a gate connected to the one end of the first capacitor and a source connected to a first current source and the selection circuit; and The second holding circuit comprises: a second capacitor having one end connected to the pixel portion and the other end connected to a reference voltage source, the second capacitor being capable of accumulating the pixel signal; and A second transistor has a gate connected to the one end of the second capacitor and a source connected to a second current source and the selection circuit.

10. The solid-state imaging device according to claim 9, wherein: The first holding circuit includes a first switch provided between the one end of the first capacitor and the pixel portion; and The second holding circuit includes a second switch provided between the one end of the second capacitor and the pixel portion.

11. The solid-state imaging device according to claim 10, wherein: When the pixel signal is sampled from the pixel portion to the first capacitor, the first switch enters an on state, When the first capacitor holds the pixel signal, the first switch enters a non-conducting state, When the pixel signal is sampled from the pixel portion to the second capacitor, the second switch enters an on state, and When the second capacitor holds the pixel signal, the second switch enters a non-conductive state.

12. The solid-state imaging device according to claim 11, wherein The first capacitor and the second capacitor sample the pixel signal at different times.

13. The solid-state imaging device according to claim 11, wherein The second holding circuit samples a second pixel signal among the pixel signals during a period in which the first holding circuit holds a first pixel signal among the pixel signals and the selection circuit outputs the first pixel signal from the first holding circuit to the AD conversion section, and The first holding circuit samples the other of the pixel signals during a period in which the second holding circuit holds the second pixel signal and the selection circuit outputs the second pixel signal from the second holding circuit to the AD conversion section.

14. The solid-state imaging device according to claim 3, further comprising: a negative capacitance circuit connected to a first signal line connected between the pixel portion and the first holding circuit and the second holding circuit and transmitting the pixel signal, wherein: The negative capacitance circuit comprises: an amplifier having an input terminal connected to the first signal line; and A capacitor is connected between the input terminal and an output terminal of the amplifier.

15. The solid-state imaging device according to claim 3, wherein: Each pixel of the pixel portion includes a first photoelectric conversion element and a second photoelectric conversion element having different light receiving areas.

16. The solid-state imaging device according to claim 4, wherein The first holding circuit further includes: a third transistor and an eighth switch connected in series between a power supply and a drain of the first amplifying transistor, and The second holding circuit further includes: A fourth transistor and a ninth switch are connected in series between the power supply and the drain of the second transistor.

17. The solid-state imaging device according to claim 16, wherein: The third transistor and the eighth switch are connected in parallel with the first current source, and The fourth transistor and the ninth switch are connected in parallel with the second current source.

18. The solid-state imaging device according to claim 16, further comprising: A voltage generating circuit that applies a predetermined first voltage to the gates of the third transistor and the fourth transistor, wherein: When the eighth switch is in the on state, the third transistor sets the drain of the first amplifying transistor to a clamping voltage corresponding to the first voltage, or When the ninth switch is in an on state, the fourth transistor sets the drain of the second transistor to the clamping voltage.

19. The solid-state imaging device according to claim 16, wherein: In an auto-zero operation of making the pixel signal held by the first holding circuit and compared in the AD conversion section equal to a comparison reference signal, the eighth switch enters a conducting state, and The ninth switch enters an on state in an auto-zero operation of making the pixel signal held by the second holding circuit and compared in the AD conversion section equal to the comparison reference signal.

Images