Image sensing circuit, image sensor and electronic equipment

Abstract

The embodiment of the invention provides an image sensing circuit, an image sensor and electronic equipment. The image sensing circuit comprises a photodiode PPD pixel module and a signal sampling module, the PPD pixel module is used for converting the optical signal into an image voltage signal and transmitting the image voltage signal to a sensing node of the PPD pixel module; and the signal sampling module is used for acquiring the same voltage signal corresponding to the sensing node for multiple times, obtaining a sampling result based on the plurality of acquired voltage signals, and outputting the sampling result to the post-stage module. According to the fact that the thermal noise is reduced along with the increase of the sampling times, the same voltage signal corresponding to the sensing node is collected for multiple times, so that the thermal noise of the voltage signal is reduced, and the stability of the image sensing circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of machine vision technology, and in particular to an image sensing circuit, an image sensor and an electronic device. Background Art

[0002] CMOS image sensor (CIS, a device that converts optical images into electronic signals) is a type of solid-state imaging sensor. Due to its advantages such as low power consumption, high integration and simple process, it is widely used in digital cameras, smart phones, machine vision, security monitoring and intelligent transportation.

[0003] The working process of CMOS image sensor is as follows: First, the photodiode generates photoelectric effect when exposed to light, converts the light signal into an electrical signal, accumulates the generated charge in the pixel unit, and then converts the accumulated charge into an analog signal through the pixel readout circuit, and inputs the analog signal into the analog-to-digital converter, so that the analog-to-digital converter converts the analog voltage signal into a digital signal. Finally, the final image appears by processing the converted digital signal.

[0004] With the continuous development of CMOS image sensors, at present, CMOS image sensors based on PPD (Pinned Photodiode) pixel units are particularly widely used due to their excellent performance. However, when reading the reset voltage signal of the sensing node of the PPD pixel unit and the voltage signal after the charge (photogenerated electrons) of the sensing node are transferred, the reset voltage signal and the voltage signal after the charge transfer (image voltage signal) have thermal noise, resulting in poor circuit stability. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an image sensing circuit, an image sensor and an electronic device to improve the stability of the image sensing circuit. The specific technical solution is as follows:

[0006] In a first aspect, an embodiment of the present application provides an image sensor circuit, the circuit comprising:

[0007] Photodiode PPD pixel module and signal sampling module;

[0008] The PPD pixel module is used to convert the light signal into an image voltage signal and transmit the image voltage signal to its own sensing node;

[0009] The signal sampling module is used to collect multiple times the same voltage signal corresponding to the sensing node, obtain sampling results based on the collected multiple voltage signals, and output the sampling results to the subsequent module.

[0010] In one possible implementation,

[0011] The signal sampling module includes at least two capacitor components, each of which includes at least one capacitor; among the at least two capacitor components, at least one first sub-switch is included between the first capacitor component close to the input end of the signal sampling module and the input end; and at least one second sub-switch is included between any two adjacent capacitor components.

[0012] In a possible implementation manner, the capacitance values ​​of the capacitors are equal.

[0013] In one possible implementation,

[0014] For each first capacitor component group, the first capacitor component group is composed of the first capacitor component and a second capacitor component adjacent to the first capacitor component, the first sub-switch and the second sub-switch in the first capacitor component group are turned on to perform a collection so that the second capacitor component has a first voltage sub-signal; the second switch in the first capacitor component group is turned off and the collection is performed so that the first capacitor component has a second voltage sub-signal; the first sub-switch is turned off and the second sub-switch in the first capacitor component group is turned on so that the first capacitor component and the second capacitor component have an average value of the first voltage sub-signal and the second voltage sub-signal;

[0015] Wherein, the second capacitor component adjacent to the first capacitor component includes a capacitor component close to the output end of the signal sampling module;

[0016] When the signal sampling module includes at least two second capacitor components, the first sub-switch and the second sub-switches in the first capacitor component group are turned off, and the other second sub-switches in the signal sampling module are turned on to obtain an average value of multiple voltage signals.

[0017] In one possible implementation,

[0018] The signal sampling module is specifically used to collect the first reset voltage signal corresponding to the sensing node for multiple times, and output the average value of the collected multiple first reset voltage signals to the subsequent module; and

[0019] The first image voltage signal corresponding to the sensing node is collected multiple times, and an average value of the collected multiple first image voltage signals is output to the subsequent module.

[0020] In a possible implementation, the signal sampling module includes a first capacitor, a second capacitor, a first switch, and a second switch;

[0021] The first end of the first switch is connected to the input end of the signal sampling module, and the second end of the first switch is connected to the first end of the first capacitor and the first end of the second switch respectively;

[0022] The second end of the first capacitor is grounded;

[0023] The second end of the second switch is connected to the output end of the signal sampling module and the first end of the second capacitor respectively;

[0024] The second terminal of the second capacitor is grounded;

[0025] The plurality of first reset voltage signals include a first voltage signal and a second voltage signal;

[0026] The signal sampling module is specifically used to receive the first voltage signal when the first switch and the second switch of the module are both turned on, so that the voltage signal at the first end of the second capacitor is the first voltage signal; when the second switch of the module is turned off and the first switch is turned on, keep the voltage signal at the first end of the second capacitor as the first voltage signal, and receive the second voltage signal, so that the voltage signal at the first end of the first capacitor is the second voltage signal; when the first switch and the second switch of the module are both turned off, keep the voltage signal at the first end of the first capacitor as the second voltage signal, and keep the voltage signal at the first end of the second capacitor as the first voltage signal; when the second switch of the module is turned on and the first switch is turned off, output the average value of the first voltage signal and the second voltage signal to the post-stage module.

[0027] In a possible implementation manner, the plurality of first image voltage signals include a third voltage signal and a fourth voltage signal;

[0028] The signal sampling module is specifically used to receive the third voltage signal when the first switch and the second switch of the module are both turned on, so that the voltage signal at the first end of the second capacitor is the third voltage signal; when the second switch of the module is turned off and the first switch is turned on, keep the voltage signal at the first end of the second capacitor as the third voltage signal, and receive the fourth voltage signal, so that the voltage signal at the first end of the first capacitor is the fourth voltage signal; when the first switch and the second switch of the module are both turned off, keep the voltage signal at the first end of the first capacitor as the fourth voltage signal, and keep the voltage signal at the first end of the second capacitor as the third voltage signal; when the second switch of the module is turned on and the first switch is turned off, output the average value of the third voltage signal and the fourth voltage signal to the post-stage module.

[0029] In a possible implementation, the signal sampling module includes a first capacitor, a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch;

[0030] The first end of the first switch is connected to the input end of the signal sampling module, and the second end of the first switch is respectively connected to the first end of the first capacitor, the first end of the second switch, and the first end of the third switch;

[0031] The second end of the first capacitor is grounded;

[0032] The second end of the second switch is respectively connected to the output end of the signal sampling module, the first end of the third capacitor, and the second end of the fourth switch;

[0033] The second end of the third capacitor is grounded;

[0034] The first end of the second capacitor is connected to the second end of the third switch and the first end of the fourth switch respectively;

[0035] The second terminal of the second capacitor is grounded;

[0036] The plurality of first reset voltage signals include a first voltage signal, a second voltage signal, a third voltage signal, and a fourth voltage signal;

[0037] The signal sampling module is specifically used for receiving the first voltage signal when the first switch and the second switch of the module are both turned on and the third switch and the fourth switch are both turned off, so that the voltage signal at the first end of the third capacitor is the first voltage signal; when the second switch of the module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the third capacitor as the first voltage signal, and receiving the second voltage signal, so that the voltage signal at the first end of the first capacitor is the second voltage signal; when the first switch and the second switch of the module are both turned off, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the first capacitor as the second voltage signal, and keeping the voltage signal at the first end of the third capacitor as the first voltage signal; when the second switch of the module is turned on, the first switch is turned off, and the third switch and the fourth switch are both turned off, obtaining the first reset sub-voltage signal; wherein the first reset sub-voltage signal is the average value of the first voltage signal and the second voltage signal;

[0038] The signal sampling module is specifically used to maintain the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal and receive the third voltage signal when the second switch of the signal sampling module is turned off, the first switch is turned on, the third switch is turned on, and the fourth switch is turned off, so that the voltage signal at the first end of the second capacitor is the third voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, maintain the voltage signal at the first end of the second capacitor as the third voltage signal, maintain the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal, and receive the fourth voltage signal so that the voltage signal at the first end of the first capacitor is the fourth voltage signal; when the first switch and the second switch of the first capacitor are both turned off, and the third switch and the fourth switch are both turned off, the voltage signal at the first end of the first capacitor is maintained as the fourth voltage signal, the voltage signal at the first end of the second capacitor is maintained as the third voltage signal, and the voltage signal at the first end of the third capacitor is maintained as the first reset sub-voltage signal; when the first switch and the second switch of the first capacitor are both turned off, the third switch is turned on, and the fourth switch is turned off, the voltage signal at the first end of the third capacitor is maintained as the first reset sub-voltage signal, and a second reset sub-voltage signal is obtained; wherein the second reset sub-voltage signal is an average value of the third voltage signal and the fourth voltage signal;

[0039] The signal sampling module is specifically used to keep the voltage signal at the first end of the second capacitor as the second reset sub-voltage signal, and keep the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off; and output the average value of the first reset sub-voltage signal and the second reset sub-voltage signal to the post-stage module when the first switch and the second switch of the signal sampling module are both turned off, the third switch is turned off, and the fourth switch is turned on.

[0040] In a possible implementation manner, the plurality of first image voltage signals include a fifth voltage signal, a sixth voltage signal, a seventh voltage signal, and an eighth voltage signal;

[0041] The signal sampling module is specifically used for receiving the fifth voltage signal when the first switch and the second switch of the signal sampling module are both turned on and the third switch and the fourth switch are both turned off, so that the voltage signal at the first end of the third capacitor is the fifth voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the third capacitor as the fifth voltage signal, and receiving the sixth voltage signal, so that the voltage signal at the first end of the first capacitor is the sixth voltage signal; when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the first capacitor as the sixth voltage signal, and keeping the voltage signal at the first end of the third capacitor as the fifth voltage signal; when the second switch of the signal sampling module is turned on, the first switch is turned off, and the third switch and the fourth switch are both turned off, obtaining the first image sub-voltage signal; wherein the first image sub-voltage signal is the average value of the fifth voltage signal and the sixth voltage signal;

[0042] The signal sampling module is specifically used to maintain the voltage signal at the first end of the third capacitor as the first image sub-voltage signal and receive the seventh voltage signal when the second switch of the signal sampling module is turned off, the first switch is turned on, the third switch is turned on, and the fourth switch is turned off, so that the voltage signal at the first end of the second capacitor is the seventh voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, maintain the voltage signal at the first end of the second capacitor as the seventh voltage signal, maintain the voltage signal at the first end of the third capacitor as the first image sub-voltage signal, and receive the eighth voltage signal so that the voltage signal at the first end of the first capacitor is the eighth voltage signal. the eighth voltage signal; when the first switch and the second switch are both turned off, and the third switch and the fourth switch are both turned off, the voltage signal at the first end of the first capacitor is maintained as the eighth voltage signal, the voltage signal at the first end of the second capacitor is maintained as the seventh voltage signal, and the voltage signal at the first end of the third capacitor is maintained as the first image sub-voltage signal; when the first switch and the second switch are both turned off, the third switch is turned on, and the fourth switch is turned off, the voltage signal at the first end of the third capacitor is maintained as the first image sub-voltage signal, and a second image sub-voltage signal is obtained; wherein the second image sub-voltage signal is an average value of the seventh voltage signal and the eighth voltage signal;

[0043] The signal sampling module is specifically used to keep the voltage signal at the first end of the second capacitor as the second image sub-voltage signal, and keep the voltage signal at the first end of the third capacitor as the first image sub-voltage signal when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off; and output the average value of the first image sub-voltage signal and the second image sub-voltage signal to the post-stage module when the first switch and the second switch of the signal sampling module are both turned off, the third switch is turned off and the fourth switch is turned on.

[0044] In a possible implementation, the circuit further includes a column-level amplification module;

[0045] The output end of the PPD pixel module is connected to the input end of the column-level amplification module, and the output end of the column-level amplification module is connected to the input end of the signal sampling module;

[0046] The column-level amplification module is used to collect the second reset voltage signal corresponding to the sensing node for multiple times, amplify each collected second reset voltage signal to obtain multiple first reset voltage signals, and output the multiple first reset voltage signals to the signal sampling module;

[0047] The column-level amplification module is also used to collect the second image voltage signals corresponding to the sensing nodes multiple times, and amplify each collected second image voltage signal to obtain multiple first image voltage signals, and output the multiple first image voltage signals to the signal sampling module.

[0048] In a possible implementation manner, the column-level amplification module includes an amplifier, an input capacitor, a feedback capacitor, a load capacitor, and a transistor switch;

[0049] The first end of the input capacitor is connected to the input end of the column-level amplification module, and the second end of the input capacitor is respectively connected to the first end of the transistor switch, the first end of the feedback capacitor, and the input end of the amplifier;

[0050] The output end of the amplifier is respectively connected to the second end of the transistor switch, the second end of the feedback capacitor, the first end of the load capacitor, and the output end of the column-level amplification module;

[0051] The second terminal of the load capacitor is grounded.

[0052] In a possible implementation, the circuit further includes an analog-to-digital conversion module;

[0053] The input end of the analog-to-digital conversion module is connected to the output end of the signal sampling module, and the output end of the analog-to-digital conversion module is used to connect to a subsequent circuit;

[0054] The analog-to-digital conversion module is used to receive an average value of the plurality of first reset voltage signals, convert the average value of the plurality of first reset voltage signals into a first digital signal, and transmit the first digital signal to the subsequent circuit;

[0055] The analog-to-digital conversion module is further used to receive an average value of the multiple first image voltage signals, convert the average value of the multiple first image voltage signals into a second digital signal, and transmit the second digital signal to the subsequent circuit.

[0056] In a second aspect, an embodiment of the present application provides an image sensor, wherein the image sensor comprises the image sensing circuit described in any one of the above-mentioned first aspect.

[0057] In a third aspect, an embodiment of the present application provides an electronic device, which includes the image sensor described in the second aspect.

[0058] Beneficial effects of the embodiments of the present application:

[0059] The embodiment of the present application provides an image sensing circuit, an image sensor and an electronic device, wherein the image sensing circuit includes: a photodiode PPD pixel module and a signal sampling module; the PPD pixel module is used to convert an optical signal into an image voltage signal and transmit the image voltage signal to its own sensing node; the signal sampling module is used to collect multiple times the same voltage signal corresponding to the sensing node, obtain sampling results based on the collected multiple voltage signals, and output the sampling results to the subsequent module. According to the fact that thermal noise decreases with the increase of the number of sampling times, the thermal noise of the voltage signal is reduced by collecting multiple times the same voltage signal corresponding to the sensing node, thereby improving the stability of the image sensing circuit.

[0060] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0062] Figure 1 A schematic diagram of a CMOS image sensor circuit in the related art;

[0063] Figure 2 A schematic diagram of a first structure of an image sensor circuit provided in an embodiment of the present application;

[0064] Figure 3a It is a schematic diagram of the first stage when the signal sampling module samples the first reset voltage signal twice;

[0065] Figure 3b It is a schematic diagram of the second stage when the signal sampling module samples the first reset voltage signal twice;

[0066] Figure 3c It is a schematic diagram of the third stage when the signal sampling module samples the first reset voltage signal twice;

[0067] Figure 3d It is a schematic diagram of the fourth stage when the signal sampling module samples the first reset voltage signal twice;

[0068] Figure 4a It is a schematic diagram of the first stage when the signal sampling module samples the first image voltage signal twice;

[0069] Figure 4b It is a schematic diagram of the second stage when the signal sampling module samples the first image voltage signal twice;

[0070] Figure 4c It is a schematic diagram of the third stage when the signal sampling module samples the first image voltage signal twice;

[0071] Figure 4d It is a schematic diagram of the fourth stage when the signal sampling module samples the first image voltage signal twice;

[0072] Figure 5a It is a schematic diagram of the first stage when the signal sampling module samples the first reset voltage signal four times;

[0073] Figure 5b It is a schematic diagram of the second stage when the signal sampling module samples the first reset voltage signal four times;

[0074] Figure 5c It is a schematic diagram of the third stage when the signal sampling module samples the first reset voltage signal four times;

[0075] Figure 5d It is a schematic diagram of the fourth stage when the signal sampling module samples the first reset voltage signal four times;

[0076] Figure 5e It is a schematic diagram of the fifth stage when the signal sampling module samples the first reset voltage signal four times;

[0077] Figure 5f It is a schematic diagram of the sixth stage when the signal sampling module samples the first reset voltage signal four times;

[0078] Figure 5g It is a schematic diagram of the seventh stage when the signal sampling module samples the first reset voltage signal four times;

[0079] Figure 5h It is a schematic diagram of the eighth stage when the signal sampling module samples the first reset voltage signal four times;

[0080] Figure 5i It is a schematic diagram of the ninth stage when the signal sampling module samples the first reset voltage signal four times;

[0081] Figure 5j It is a schematic diagram of the tenth stage when the signal sampling module samples the first reset voltage signal four times;

[0082] Figure 6a It is a schematic diagram of the first stage when the signal sampling module samples the first image voltage signal four times;

[0083] Figure 6b It is a schematic diagram of the second stage when the signal sampling module samples the first image voltage signal four times;

[0084] Figure 6c It is a schematic diagram of the third stage when the signal sampling module samples the first image voltage signal four times;

[0085] Figure 6d It is a schematic diagram of the fourth stage when the signal sampling module samples the first image voltage signal four times;

[0086] Figure 6e It is a schematic diagram of the fifth stage when the signal sampling module samples the first image voltage signal four times;

[0087] Figure 6f It is a schematic diagram of the sixth stage when the signal sampling module samples the first image voltage signal four times;

[0088] Figure 6g It is a schematic diagram of the seventh stage when the signal sampling module samples the first image voltage signal four times;

[0089] Figure 6h It is a schematic diagram of the eighth stage when the signal sampling module samples the first image voltage signal four times;

[0090] Figure 6i It is a schematic diagram of the ninth stage when the signal sampling module samples the first image voltage signal four times;

[0091] Figure 6j It is a schematic diagram of the tenth stage when the signal sampling module samples the first image voltage signal four times;

[0092] Figure 7 A second structural schematic diagram of the image sensor circuit provided in an embodiment of the present application;

[0093] Figure 8 A third structural schematic diagram of the image sensor circuit provided in an embodiment of the present application;

[0094] Fig. 9 A fourth structural schematic diagram of the image sensor circuit provided in an embodiment of the present application;

[0095] Fig.10 A schematic diagram of the structure of an image sensor provided in an embodiment of the present application;

[0096] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0097] Fig.12a A schematic diagram of the structure of a signal sampling module provided in an embodiment of the present application;

[0098] Figure 12b Another structural schematic diagram of the signal sampling module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0099] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0100] First, let’s briefly introduce CMOS image sensors and how they work. CMOS image sensors are a type of solid-state imaging sensor. Due to their low power consumption, high integration, and simple process, they are widely used in digital cameras, smart phones, machine vision, security monitoring, and intelligent transportation.

[0101] The working process of CMOS image sensor is as follows: First, the photodiode generates photoelectric effect when exposed to light, converts the light signal into an electrical signal, accumulates the generated charge in the pixel unit, and then converts the accumulated charge into an analog signal through the pixel readout circuit, and inputs the analog signal into the analog-to-digital converter, so that the analog-to-digital converter converts the analog voltage signal into a digital signal. Finally, the final image appears by processing the converted digital signal.

[0102] With the continuous development of CMOS image sensors, at present, CMOS image sensors based on PPD pixel units are widely used due to their excellent performance. The structure of CMOS image sensor circuit based on PPD pixel unit can be seen in Figure 1 The PPD pixel unit includes a photodiode PPD, a transmission gate control transistor TX, a reset transistor RST, a signal amplifier SF, and a pixel row selector RS. The working mode of the CMOS image sensing circuit based on the PPD pixel unit is as follows:

[0103] When light irradiates the photodiode PPD, the photodiode PPD generates a photoelectric effect and generates electron-hole pairs. The internal electric field causes the electrons to move to the n region and the holes to move to the p region. When the light irradiation ends, the reset transistor RST is controlled to be in the on state, and the sensing node SN of the PPD pixel unit is reset (the accumulated charge in the sensing node SN is cleared). After the reset operation is completed, the signal amplifier SF receives the reset voltage signal of the sensing node SN through its own gate and outputs the signal through its own source. The voltage value of the voltage signal output by the source is equal to the voltage value of the reset voltage signal input by the gate. At this time, the pixel row selector RS is in the on state, and the column-level amplification module (column-level amplifier) ​​receives the voltage signal output by the source of the signal amplifier SF and performs amplification processing, that is, the reset voltage signal is read. The read reset voltage signal contains thermal noise introduced by the reset, etc.

[0104] After the reset voltage signal is read, the control transmission gate control transistor TX is switched from the off state to the on state, so that the charge (photogenerated electrons) are transferred from the photodiode PPD to the sensing node SN. After the transfer is completed, the signal amplifier SF receives the voltage signal of the sensing node SN after the charge transfer through its own gate, and outputs the signal through its own source. The voltage value of the voltage signal output by the source is equal to the voltage value of the voltage signal after the charge transfer input by the gate. At this time, the pixel row selector RS is in the on state, and the column-level amplification module (column-level amplifier) ​​receives the voltage signal output by the source of the signal amplifier SF and amplifies it, that is, the voltage signal (image voltage signal) of the sensing node after the charge transfer is read. The read voltage signal includes the signal generated by the photoelectric conversion, the thermal noise introduced by the reset, etc.

[0105] Since the reset voltage signal of the sensing node SN and the voltage signal after the charge (photogenerated electron) transfer read out have thermal noise, the stability of the circuit is poor.

[0106] In order to improve the above problems, embodiments of the present application provide an image sensing circuit, an image sensor, and an electronic device.

[0107] Next, the image sensor circuit provided in the embodiment of the present application is described in detail. The image sensor circuit 1 includes:

[0108] Photodiode PPD pixel module 11 and signal sampling module 12;

[0109] The PPD pixel module 11 is used to convert the light signal into an image voltage signal, and transmit the image voltage signal to its own sensing node SN;

[0110] The signal sampling module 12 is used to collect multiple samples of the same voltage signal corresponding to the sensing node SN, obtain sampling results based on the collected multiple voltage signals, and output the sampling results to the subsequent module.

[0111] In the embodiment of the present application, since thermal noise decreases with increasing sampling times, the thermal noise of the voltage signal is reduced by performing multiple sampling operations on the same voltage signal corresponding to the sensing node, thereby improving the stability of the image sensing circuit.

[0112] In a possible implementation, see Fig.12a The signal sampling module 12 includes at least two capacitor components, and the capacitor component includes at least one capacitor; among the at least two capacitor components, a first capacitor component close to the input end of the signal sampling module 12 and the input end include at least one first sub-switch; and at least one second sub-switch is included between any two adjacent capacitor components.

[0113] pass Fig.12a In the structure of the signal sampling module 12 shown, the signal sampling module 12 may output an average value of a plurality of voltage signals, a value after weighted summation, or other calculation results.

[0114] In one possible implementation, Fig.12a and Figure 12b In the structure of the signal sampling module 12 shown, the capacitance values ​​of the capacitors are equal.

[0115] Based on the fact that the capacitance values ​​of the capacitors are equal, the signal sampling module 12 can output an average value of a plurality of voltage signals.

[0116] Next, combine Fig.12a and Figure 12b The working process of the signal sampling module 12 is described as follows:

[0117] For each first capacitor component group, the first capacitor component group is composed of the first capacitor component (the capacitor component close to the input end) and the second capacitor component adjacent to the first capacitor component, and the first sub-switch and the second sub-switch in the first capacitor component group are turned on to perform a collection so that the second capacitor component has a first voltage sub-signal; the second switch in the first capacitor component group is turned off and the collection is performed so that the first capacitor component has a second voltage sub-signal; the first sub-switch is turned off and the second sub-switch in the first capacitor component group is turned on so that the first capacitor component and the second capacitor component have an average value of the first voltage sub-signal and the second voltage sub-signal;

[0118] Wherein, the second capacitor component adjacent to the first capacitor component includes a capacitor component close to the output end of the signal sampling module;

[0119] When the signal sampling module includes at least two second capacitor components, the first sub-switch and the second sub-switches in the first capacitor component group are turned off, and the other second sub-switches in the signal sampling module are turned on to obtain an average value of multiple voltage signals.

[0120] See also Figure 12b , when the value of n is 2, C(2n+1) is C5, S(2n+1) is S5, S(2n+2) is S6, the non-grounded end of C3 has (V1+V2) / 2, the non-grounded end of C2 has (V3+V4) / 2, and the non-grounded end of C5 has (V5+V6) / 2. Then S1, S2, S3, and S5 are disconnected, the non-grounded end of C3 remains (V1+V2) / 2, the non-grounded end of C2 remains (V3+V4) / 2, and the non-grounded end of C5 remains (V5+V6) / 2. S4 and S6 are turned on, and the signal sampling module outputs (V1+V2+V3+V4+V5+V6) / 6.

[0121] The specific switching process of the switch can be found in the detailed description below.

[0122] The same is true for sampling 8 times, 10 times, etc., which will not be elaborated here.

[0123] In a possible implementation manner, the signal sampling module 12 is specifically configured to collect the first reset voltage signal corresponding to the sensing node SN for multiple times through its own input end after the sensing node SN of the PPD pixel module 11 is reset, and output the average value of the collected multiple first reset voltage signals to the subsequent module through its own output end;

[0124] After the photogenerated electrons of the photodiode PPD of the PPD pixel module 11 are transferred to the sensing node SN, the first image voltage signal corresponding to the sensing node SN is collected multiple times through its own input end, and the average value of the collected multiple first image voltage signals is output to the subsequent module through its own output end; wherein, the sensing node SN is used to store and transmit the photogenerated electrons.

[0125] As mentioned above, the reset voltage signal of the sensing node SN and the voltage signal after the charge (photogenerated electron) transfer both have thermal noise, and the expression of the thermal noise is:

[0126]

[0127] Among them, Q tn represents the charge of thermal noise, k represents the Boltzmann constant, T represents the absolute temperature, C represents the capacitance of the sensing node SN, M represents the number of sampling times of the signal, and A col Represents the gain of the column-level amplifier module (column-level amplifier), γ SF represents the noise factor of the signal amplifier, G m，A Indicates the transconductance of the column-level amplifier module (column-level amplifier), C p Represents the parasitic capacitance of the signal amplifier, C e represents the bypass capacitance of the signal amplifier, W represents the channel width of the signal amplifier, C ox represents the oxide layer capacitance, L represents the channel length of the signal amplifier, μ represents the carrier mobility, I D represents the drain current of the signal amplifier, n represents the number of electrons, γ A A represents the noise factor of the column-level amplifier module (column-level amplifier). CG Indicates the automatic gain of the column-stage amplifier module (column-stage amplifier).

[0128] It can be seen from the above formula that thermal noise is related to the relevant parameters of the signal amplifier in the PPD pixel module 11, the relevant parameters of the column-level amplification module (column-level amplifier), and the relevant design of signal sampling. Based on the above formula, the thermal noise of the signal can be reduced by increasing the number of signal sampling times.

[0129] In the embodiment of the present application, based on the fact that thermal noise decreases with increasing sampling times, the first reset voltage signal corresponding to the sensing node SN is collected multiple times to reduce the thermal noise of the first reset voltage signal, that is, reduce the thermal noise of the read reset voltage signal; and the first image voltage signal corresponding to the sensing node SN is collected multiple times to reduce the thermal noise of the first image voltage signal, that is, reduce the thermal noise of the read image voltage signal, thereby improving the stability of the image sensing circuit and improving the performance of the image sensor.

[0130] In one possible implementation, see Figure 2 , the image sensing circuit 1 also includes a column-level amplification module 13;

[0131] The output end of the PPD pixel module 11 is connected to the input end of the column-level amplification module 13, and the output end of the column-level amplification module 13 is connected to the input end of the signal sampling module 12;

[0132] The column-level amplification module 13 is used to collect the second reset voltage signal corresponding to the sensing node SN for multiple times after the sensing node SN of the PPD pixel module 11 is reset, amplify each collected second reset voltage signal to obtain multiple first reset voltage signals, and output the multiple first reset voltage signals to the signal sampling module 12;

[0133] The column-level amplification module 13 is also used to collect the second image voltage signal corresponding to the sensing node SN for multiple times after the photogenerated electrons of the photodiode PPD of the PPD pixel module 11 are transferred to the sensing node SN, and to amplify each collected second image voltage signal to obtain multiple first image voltage signals, and output the multiple first image voltage signals to the signal sampling module 12.

[0134] The output terminal of the PPD pixel module 11 is used to output a second reset voltage signal and a second image voltage signal to the column-stage amplification module 13 . The second reset voltage signal and the second image voltage signal are signals output by the signal amplifier SF.

[0135] In the embodiment of the present application, the column-level amplification module 13 is provided to amplify the second reset voltage signal and the second image voltage signal, so as to ensure that the subsequent circuit can accurately process the signal.

[0136] In a possible implementation, see Figure 3a-3d and Figure 4a-4d , the signal sampling module 12 includes a first capacitor C1, a second capacitor C2, a first switch S1, and a second switch S2;

[0137] The first end of the first switch S1 is connected to the input end of the signal sampling module 12, and the second end of the first switch S1 is connected to the first end of the first capacitor C1 and the first end of the second switch S2 respectively;

[0138] The second end of the first capacitor C1 is grounded to GND;

[0139] The second end of the second switch S2 is connected to the output end of the signal sampling module 12 and the first end of the second capacitor C2 respectively;

[0140] A second end of the second capacitor C2 is grounded to GND;

[0141] Wherein, the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2;

[0142] The plurality of first reset voltage signals include a first voltage signal V1 and a second voltage signal V2;

[0143] The signal sampling module 12 is specifically used to receive the first voltage signal V1 when the first switch S1 and the second switch S2 are both turned on, so that the voltage signal at the first end of the second capacitor C2 is the first voltage signal V1. Figure 3a When the second switch S2 is turned off and the first switch S1 is turned on, the voltage signal at the first end of the second capacitor C2 is kept as the first voltage signal V1, and the second voltage signal V2 is received, so that the voltage signal at the first end of the first capacitor C1 is the second voltage signal V2. Figure 3b When the first switch S1 and the second switch S2 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept as the second voltage signal V2, and the voltage signal at the first end of the second capacitor C2 is kept as the first voltage signal V1. Figure 3c When the second switch S2 is turned on and the first switch S1 is turned off, the average value (V1+V2) / 2 of the first voltage signal V1 and the second voltage signal V2 is output to the subsequent module. Figure 3d .

[0144] When the second switch S2 is turned on and the first switch S1 is turned off, the first capacitor C1 and the second capacitor C2 share charges. According to the law of conservation of charge, a common voltage V is obtained between the first capacitor C1 and the second capacitor C2. The relevant expression is as follows: based on the capacitance value of the first capacitor C1 being equal to the capacitance value of the second capacitor C2, the common voltage V is the average value (V1+V2) / 2 of the first voltage signal V1 and the second voltage signal V2. The signal sampling module 12 outputs the average value (V1+V2) / 2 of the first voltage signal V1 and the second voltage signal V2 to the subsequent module.

[0145]

[0146] In the embodiment of the present application, the first reset voltage signal is sampled twice through the combination of the first capacitor C1, the second capacitor C2, the first switch S1, and the second switch S2 to reduce the thermal noise of the first reset voltage signal.

[0147] In a possible implementation manner, the plurality of first image voltage signals include a third voltage signal V3 and a fourth voltage signal V4;

[0148] The signal sampling module 12 is specifically used to receive the third voltage signal V3 when the first switch S1 and the second switch S2 are both turned on, so that the voltage signal at the first end of the second capacitor C2 is the third voltage signal V3. Figure 4a When the second switch S2 is turned off and the first switch S1 is turned on, the voltage signal at the first end of the second capacitor C2 is kept as the third voltage signal V3, and the fourth voltage signal V4 is received, so that the voltage signal at the first end of the first capacitor C1 is the fourth voltage signal V4. Figure 4b When the first switch S1 and the second switch S2 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept as the fourth voltage signal V4, and the voltage signal at the first end of the second capacitor C2 is kept as the third voltage signal V3. Figure 4c When the second switch S2 is turned on and the first switch S1 is turned off, the average value (V3+V4) / 2 of the third voltage signal V3 and the fourth voltage signal V4 is output to the subsequent module. Figure 4d .

[0149] When the second switch S2 is turned on and the first switch S1 is turned off, the first capacitor C1 and the second capacitor C2 share charge. According to the law of conservation of charge, a common voltage is obtained between the first capacitor C1 and the second capacitor C2. Based on the capacitance value of the first capacitor C1 being equal to the capacitance value of the second capacitor C2, the signal sampling module 12 outputs the average value (V3+V4) / 2 of the third voltage signal V3 and the fourth voltage signal V4 to the subsequent module.

[0150] In the embodiment of the present application, the first image voltage signal is sampled twice through the combination of the first capacitor C1, the second capacitor C2, the first switch S1, and the second switch S2 to reduce the thermal noise of the first image voltage signal.

[0151] Understandably, Figure 3a-3d and Figure 4a-4d The first switch S1 and the second switch S2 shown in the figure may be MOS switch tubes (a type of field effect transistor), may be analog switches, or may be other types of switches, which are not specifically limited in the present application.

[0152] In a possible implementation, see Figure 5a-5j and Figure 6a-6j, the signal sampling module 12 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

[0153] The first end of the first switch S1 is connected to the input end of the signal sampling module 12, and the second end of the first switch S1 is respectively connected to the first end of the first capacitor C1, the first end of the second switch S2, and the first end of the third switch S3;

[0154] The second end of the first capacitor C1 is grounded to GND;

[0155] The second end of the second switch S2 is respectively connected to the output end of the signal sampling module 12, the first end of the third capacitor C3, and the second end of the fourth switch S4;

[0156] A second end of the third capacitor C3 is grounded to GND;

[0157] The first end of the second capacitor C2 is connected to the second end of the third switch S3 and the first end of the fourth switch S4 respectively;

[0158] A second end of the second capacitor C2 is grounded to GND;

[0159] Wherein, the capacitance value of the first capacitor C1, the capacitance value of the second capacitor C2, and the capacitance value of the third capacitor C3 are equal;

[0160] The plurality of first reset voltage signals include a first voltage signal V1, a second voltage signal V2, a third voltage signal V3, and a fourth voltage signal V4;

[0161] The signal sampling module 12 is specifically used to receive the first voltage signal V1 when the first switch S1 and the second switch S2 are both turned on and the third switch S3 and the fourth switch S4 are both turned off, so that the voltage signal at the first end of the third capacitor C3 is the first voltage signal V1. Figure 5a When the second switch S2 is turned off, the first switch S1 is turned on, and the third switch S3 and the fourth switch S4 are turned off, the voltage signal at the first end of the third capacitor C3 is kept as the first voltage signal V1, and the second voltage signal V2 is received, so that the voltage signal at the first end of the first capacitor C1 is the second voltage signal V2. Figure 5b When the first switch S1 and the second switch S2 are both turned off, and the third switch S3 and the fourth switch S4 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept as the second voltage signal V2, and the voltage signal at the first end of the third capacitor C3 is kept as the first voltage signal V1. Figure 5cWhen the second switch S2 is turned on, the first switch S1 is turned off, and the third switch S3 and the fourth switch S4 are both turned off, the first reset sub-voltage signal is obtained, which can be seen from Figure 5d ; Wherein, the first reset sub-voltage signal is an average value of the first voltage signal V1 and the second voltage signal V2 (V1+V2) / 2;

[0162] When the second switch S2 is turned on, the first switch S1 is turned off, and the third switch S3 and the fourth switch S4 are both turned off, according to the law of conservation of charge, a common voltage is obtained between the first capacitor C1 and the third capacitor C3. Based on the fact that the capacitance value of the first capacitor C1 is equal to the capacitance value of the third capacitor C3, this common voltage is the average value of the first voltage signal V1 and the second voltage signal V2 (V1+V2) / 2, that is, the first reset sub-voltage signal is obtained.

[0163] The signal sampling module 12 is specifically used to keep the voltage signal at the first end of the third capacitor C3 as the first reset sub-voltage signal (V1+V2) / 2, and receive the third voltage signal V3 when the second switch S2 of the signal sampling module 12 is turned off, the first switch S1 is turned on, the third switch S3 is turned on, and the fourth switch S4 is turned off, so that the voltage signal at the first end of the second capacitor C2 is the third voltage signal V3. Figure 5e ; When the second switch S2 is turned off, the first switch S1 is turned on, and the third switch S3 and the fourth switch S4 are both turned off, the voltage signal at the first end of the second capacitor C2 is kept as the third voltage signal V3, the voltage signal at the first end of the third capacitor C3 is kept as the first reset sub-voltage signal (V1+V2) / 2, and the fourth voltage signal V4 is received, so that the voltage signal at the first end of the first capacitor C1 is the fourth voltage signal V4, which can be seen from Figure 5f ; When the first switch S1 and the second switch S2 are both turned off, and the third switch S3 and the fourth switch S4 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept as the fourth voltage signal V4, the voltage signal at the first end of the second capacitor C2 is kept as the third voltage signal V3, and the voltage signal at the first end of the third capacitor C3 is kept as the first reset sub-voltage signal (V1+V2) / 2. Figure 5g When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned on, and the fourth switch S4 is turned off, the voltage signal at the first end of the third capacitor C3 is kept at the first reset sub-voltage signal (V1+V2) / 2, and the second reset sub-voltage signal is obtained. Figure 5h ; Wherein, the second reset sub-voltage signal is the average value of the third voltage signal V3 and the fourth voltage signal V4 (V3+V4) / 2;

[0164] When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned on, and the fourth switch S4 is turned off, according to the law of conservation of charge, a common voltage is obtained between the first capacitor C1 and the second capacitor C2. Based on the fact that the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2, this common voltage is the average value of the third voltage signal V3 and the fourth voltage signal V4 (V3+V4) / 2, that is, the second reset sub-voltage signal is obtained.

[0165] The signal sampling module 12 is specifically used to keep the voltage signal at the first end of the second capacitor C2 as the second reset sub-voltage signal (V3+V4) / 2, and keep the voltage signal at the first end of the third capacitor C3 as the first reset sub-voltage signal (V1+V2) / 2 when the first switch S1 and the second switch S2 of the signal sampling module 12 are both turned off and the third switch S3 and the fourth switch S4 are both turned off. Figure 5i ; When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned off, and the fourth switch S4 is turned on, the average value (V1+V2+V3+V4) / 4 of the first reset sub-voltage signal (V1+V2) / 2 and the second reset sub-voltage signal (V3+V4) / 2 is output to the subsequent module, which can be seen in Figure 5j .

[0166] When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned off, and the fourth switch S4 is turned on, the second capacitor C2 and the third capacitor C3 share charge. According to the law of conservation of charge, a common voltage is obtained between the second capacitor C2 and the third capacitor C3. Based on the fact that the capacitance value of the second capacitor C2 is equal to the capacitance value of the third capacitor C3, this common voltage is the average value (V1+V2+V3+V4) / 4 of the first reset sub-voltage signal (V1+V2) / 2 and the second reset sub-voltage signal (V3+V4) / 2. The signal sampling module 12 outputs (V1+V2+V3+V4) / 4 to the subsequent module.

[0167] In the embodiment of the present application, the first reset voltage signal is sampled four times through the combination of the first capacitor C1, the second capacitor C2, the third capacitor C3, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 to reduce the thermal noise of the first reset voltage signal.

[0168] In a possible implementation manner, the plurality of first image voltage signals include a fifth voltage signal V5, a sixth voltage signal V6, a seventh voltage signal V7, and an eighth voltage signal V8;

[0169] The signal sampling module 12 is specifically used to receive the fifth voltage signal V5 when the first switch S1 and the second switch S2 are both turned on and the third switch S3 and the fourth switch S4 are both turned off, so that the voltage signal at the first end of the third capacitor C3 is the fifth voltage signal V5. Figure 6a When the second switch S2 is turned off, the first switch S1 is turned on, and the third switch S3 and the fourth switch S4 are turned off, the voltage signal at the first end of the third capacitor C3 is kept as the fifth voltage signal V5, and the sixth voltage signal V6 is received, so that the voltage signal at the first end of the first capacitor C1 is the sixth voltage signal V6, which can be seen from Figure 6b When the first switch S1 and the second switch S2 are both turned off, and the third switch S3 and the fourth switch S4 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept as the sixth voltage signal V6, and the voltage signal at the first end of the third capacitor C3 is kept as the fifth voltage signal V5. Figure 6c When the second switch S2 is turned on, the first switch S1 is turned off, and the third switch S3 and the fourth switch S4 are both turned off, the first image sub-voltage signal is obtained, which can be seen from Figure 6d ; Wherein, the first image sub-voltage signal is an average value of the fifth voltage signal V5 and the sixth voltage signal V6 (V5+V6) / 2;

[0170] The signal sampling module 12 is specifically used to keep the voltage signal at the first end of the third capacitor C3 as the first image sub-voltage signal (V5+V6) / 2, and receive the seventh voltage signal V7, so that the voltage signal at the first end of the second capacitor C2 is the seventh voltage signal V7, when the second switch S2 of the signal sampling module 12 is turned off, the first switch S1 is turned on, the third switch S3 is turned on, and the fourth switch S4 is turned off. Figure 6e When the second switch S2 is turned off, the first switch S1 is turned on, and the third switch S3 and the fourth switch S4 are turned off, the voltage signal at the first end of the second capacitor C2 is kept as the seventh voltage signal V7, the voltage signal at the first end of the third capacitor C3 is kept as the first image sub-voltage signal (V5+V6) / 2, and the eighth voltage signal V8 is received, so that the voltage signal at the first end of the first capacitor C1 is the eighth voltage signal V8. Figure 6fWhen the first switch S1 and the second switch S2 are both turned off, and the third switch S3 and the fourth switch S4 are both turned off, the voltage signal at the first end of the first capacitor C1 is kept at the eighth voltage signal V8, the voltage signal at the first end of the second capacitor C2 is kept at the seventh voltage signal V7, and the voltage signal at the first end of the third capacitor C3 is kept at the first image sub-voltage signal (V5+V6) / 2. Figure 6g When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned on, and the fourth switch S4 is turned off, the voltage signal at the first end of the third capacitor C3 is kept at the first image sub-voltage signal (V5+V6) / 2, and the second image sub-voltage signal is obtained. Figure 6h ; Wherein, the second image sub-voltage signal is an average value of the seventh voltage signal V7 and the eighth voltage signal V8 (V7+V8) / 2;

[0171] The signal sampling module 12 is specifically used to keep the voltage signal at the first end of the second capacitor C2 as the second image sub-voltage signal (V7+V8) / 2, and keep the voltage signal at the first end of the third capacitor C3 as the first image sub-voltage signal (V5+V6) / 2 when the first switch S1 and the second switch S2 of the signal sampling module 12 are both turned off, and the third switch S3 and the fourth switch S4 are both turned off. Figure 6i When the first switch S1 and the second switch S2 are both turned off, the third switch S3 is turned off, and the fourth switch S4 is turned on, the average value (V5+V6+V7+V8) / 4 of the first image sub-voltage signal (V5+V6) / 2 and the second image sub-voltage signal (V7+V8) / 2 is output to the subsequent module. Figure 6j .

[0172] In the embodiment of the present application, the first image voltage signal is sampled four times through the combination of the first capacitor C1, the second capacitor C2, the third capacitor C3, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 to reduce the thermal noise of the first image voltage signal.

[0173] Understandably, Figure 5a-5j and Figure 6a-6j The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 shown in the figure may be MOS switch tubes, analog switches, or other types of switches, which are not specifically limited in the present application.

[0174] The signal sampling module 12 provided in the present application only needs to use capacitors and switches, does not require other active circuits, and does not consume additional power.

[0175] In one possible implementation, see Figure 7 , the PPD pixel module 11 includes a photodiode PPD, a transmission gate control transistor TX, a reset transistor RST, a signal amplifier SF, and a pixel row selector RS;

[0176] The control end of the transmission gate control transistor TX is connected to the transmission control signal end TX', the first end of the transmission gate control transistor TX is connected to the first end of the photodiode PPD, and the second end of the transmission gate control transistor TX is connected to the sensing node SN;

[0177] The second end of the photodiode PPD is grounded to GND;

[0178] The control end of the reset transistor RST is connected to the reset control signal end RST′, the first end of the reset transistor RST is connected to the sensing node SN, and the second end of the reset transistor RST is connected to the reset signal input end VRST;

[0179] A first terminal of the signal amplifier SF is connected to the sensing node SN, a second terminal of the signal amplifier SF is connected to the power supply voltage terminal VDD, and a third terminal of the signal amplifier SF is connected to a first terminal of the pixel row selector RS;

[0180] The control end of the pixel row selector RS is connected to the selection signal end RS', and the second end of the pixel row selector RS is connected to the input end of the column-level amplification module 13;

[0181] The reset transistor RST is used to be in a conducting state after the exposure of the photodiode PPD is completed, so that the reset signal of the reset signal input terminal VRST resets the sensing node SN;

[0182] The signal amplifier SF is used to receive the third reset voltage signal of the sensing node SN through its first terminal, and output the second reset voltage signal through its third terminal following the third reset voltage signal, so that the column-level amplification module 13 receives the second reset voltage signal through the pixel row selector RS in the on state; wherein the voltage value of the second reset voltage signal is equal to the voltage value of the third reset voltage signal;

[0183] The transmission gate control transistor TX is used to switch itself from an off state to an on state after the third reset voltage signal of the sensing node SN is acquired, so that the photogenerated electrons of the photodiode PPD are transferred to the sensing node SN;

[0184] The signal amplifier SF is also used to receive the third image voltage signal of the sensing node SN through its first end, and follow the third image voltage signal to output the second image voltage signal through its third end, so that the column-level amplification module 13 receives the second image voltage signal through the pixel row selector RS in the on state; wherein the voltage value of the second image voltage signal is equal to the voltage value of the third image voltage signal.

[0185] The transmission gate control transistor TX can be a triode, a field effect transistor, or other types of transistors. When the transmission gate control transistor TX is a triode, the control end of the transmission gate control transistor TX is the base, the first end of the transmission gate control transistor TX is the emitter / collector, and the second end of the transmission gate control transistor TX is the collector / emitter corresponding to the first section; when the transmission gate control transistor TX is a field effect transistor, the control end of the transmission gate control transistor TX is the gate, the first end of the transmission gate control transistor TX is the source / drain, and the second end of the transmission gate control transistor TX is the drain / source corresponding to the first end.

[0186] The reset transistor RST can be a triode, a field effect transistor, or other types of transistors. When the reset transistor RST is a triode, the control end of the reset transistor RST is the base, the first end of the reset transistor RST is the emitter / collector, and the second end of the reset transistor RST is the collector / emitter corresponding to the first end; when the reset transistor RST is a field effect transistor, the control end of the reset transistor RST is the gate, the first end of the reset transistor RST is the source / drain, and the second end of the reset transistor RST is the drain / source corresponding to the first end.

[0187] The signal amplifier SF can be a triode, a field effect transistor, or other types of transistors. When the signal amplifier SF is a triode, the first end of the signal amplifier SF is the base, the third end of the signal amplifier SF is the emitter, and the second end of the signal amplifier SF is the collector; when the signal amplifier SF is a field effect transistor (source follower), the first end of the signal amplifier SF is the gate, the third end of the signal amplifier SF is the source, and the second end of the signal amplifier SF is the drain.

[0188] The pixel row selector RS can be a triode, a field effect transistor, or other types of transistors. When the pixel row selector RS is a triode, the control end of the pixel row selector RS is the base, the second end of the pixel row selector RS is the emitter / collector, and the first end of the pixel row selector RS is the collector / emitter corresponding to the second end; when the pixel row selector RS is a field effect transistor, the control end of the pixel row selector RS is the gate, the second end of the pixel row selector RS is the source / drain, and the first end of the pixel row selector RS is the drain / source corresponding to the second end.

[0189] In one possible implementation, see Figure 8 , the column-level amplification module 13 includes an amplifier amp, an input capacitor Cin, a feedback capacitor Cf, a load capacitor CL, and a transistor switch AZamp;

[0190] The first end of the input capacitor Cin is connected to the input end of the column-level amplification module 13, and the second end of the input capacitor Cin is respectively connected to the first end of the transistor switch AZamp, the first end of the feedback capacitor Cf, and the input end of the amplifier amp;

[0191] The output end of the amplifier amp is respectively connected to the second end of the transistor switch AZamp, the second end of the feedback capacitor Cf, the first end of the load capacitor CL, and the output end of the column-level amplification module 13;

[0192] A second end of the load capacitor CL is connected to the ground GND.

[0193] The ratio of the input capacitance Cin to the feedback capacitance Cf determines the gain of the amplifier amp.

[0194] The transistor switch Azamp is used to control the initialization of the amplifier amp.

[0195] In one possible implementation, see Fig. 9 , the image sensing circuit 1 also includes an analog-to-digital conversion module 14;

[0196] The input end of the analog-to-digital conversion module 14 is connected to the output end of the signal sampling module 12, and the output end of the analog-to-digital conversion module 14 is used to connect to the subsequent circuit;

[0197] The analog-to-digital conversion module 14 is used to receive the average value of the multiple first reset voltage signals, convert the average value of the multiple first reset voltage signals into a first digital signal, and transmit the first digital signal to the subsequent circuit;

[0198] The analog-to-digital conversion module 14 is further configured to receive an average value of the plurality of first image voltage signals, convert the average value of the plurality of first image voltage signals into a second digital signal, and transmit the second digital signal to the subsequent circuit.

[0199] The present application also provides an image sensor 2, see Fig.10 , the image sensor 2 includes the image sensing circuit 1 described in any one of the above embodiments.

[0200] The present application embodiment also provides an electronic device 3, see Fig.11 , the electronic device 3 includes the image sensor 2 described in the above embodiment.

[0201] The electronic device 3 may be a digital camera, a smart phone, or other types of electronic devices, which are not specifically limited in the present application.

[0202] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0203] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0204] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. An image sensing circuit, characterized in that: The circuit includes a photodiode PPD pixel module and a signal sampling module; The PPD pixel module is used to convert the light signal into an image voltage signal and transmit the image voltage signal to its own sensing node; The signal sampling module is used to collect multiple times the same voltage signal corresponding to the sensing node, obtain sampling results based on the collected multiple voltage signals, and output the sampling results to the subsequent module.

2. The circuit according to claim 1, characterized in that The signal sampling module includes at least two capacitor components, each of which includes at least one capacitor; among the at least two capacitor components, at least one first sub-switch is included between the first capacitor component close to the input end of the signal sampling module and the input end; and at least one second sub-switch is included between any two adjacent capacitor components.

3. The circuit according to claim 2, characterized in that The capacitance values ​​of the capacitors are equal.

4. The circuit according to claim 3, characterized in that For each first capacitor component group, the first capacitor component group is composed of the first capacitor component and a second capacitor component adjacent to the first capacitor component, the first sub-switch and the second sub-switch in the first capacitor component group are turned on to perform a collection so that the second capacitor component has a first voltage sub-signal; the second switch in the first capacitor component group is turned off and the collection is performed so that the first capacitor component has a second voltage sub-signal; the first sub-switch is turned off and the second sub-switch in the first capacitor component group is turned on so that the first capacitor component and the second capacitor component have an average value of the first voltage sub-signal and the second voltage sub-signal; Wherein, the second capacitor component adjacent to the first capacitor component includes a capacitor component close to the output end of the signal sampling module; When the signal sampling module includes at least two second capacitor components, the first sub-switch and the second sub-switches in the first capacitor component group are turned off, and the other second sub-switches in the signal sampling module are turned on to obtain an average value of multiple voltage signals.

5. The circuit according to claim 4, characterized in that The signal sampling module is specifically used to collect the first reset voltage signal corresponding to the sensing node for multiple times, and output the average value of the collected multiple first reset voltage signals to the subsequent module; as well as, The first image voltage signal corresponding to the sensing node is collected multiple times, and an average value of the collected multiple first image voltage signals is output to the subsequent module.

6. The circuit according to claim 5, characterized in that The signal sampling module includes a first capacitor, a second capacitor, a first switch, and a second switch; The first end of the first switch is connected to the input end of the signal sampling module, and the second end of the first switch is connected to the first end of the first capacitor and the first end of the second switch respectively; The second end of the first capacitor is grounded; The second end of the second switch is connected to the output end of the signal sampling module and the first end of the second capacitor respectively; The second terminal of the second capacitor is grounded; The plurality of first reset voltage signals include a first voltage signal and a second voltage signal; The signal sampling module is specifically used to receive the first voltage signal when the first switch and the second switch of the module are both turned on, so that the voltage signal at the first end of the second capacitor is the first voltage signal; when the second switch of the module is turned off and the first switch is turned on, keep the voltage signal at the first end of the second capacitor as the first voltage signal, and receive the second voltage signal, so that the voltage signal at the first end of the first capacitor is the second voltage signal; when the first switch and the second switch of the module are both turned off, keep the voltage signal at the first end of the first capacitor as the second voltage signal, and keep the voltage signal at the first end of the second capacitor as the first voltage signal; when the second switch of the module is turned on and the first switch is turned off, output the average value of the first voltage signal and the second voltage signal to the post-stage module.

7. The circuit according to claim 6, characterized in that The plurality of first image voltage signals include a third voltage signal and a fourth voltage signal; The signal sampling module is specifically used to receive the third voltage signal when the first switch and the second switch of the module are both turned on, so that the voltage signal at the first end of the second capacitor is the third voltage signal; when the second switch of the module is turned off and the first switch is turned on, keep the voltage signal at the first end of the second capacitor as the third voltage signal, and receive the fourth voltage signal, so that the voltage signal at the first end of the first capacitor is the fourth voltage signal; when the first switch and the second switch of the module are both turned off, keep the voltage signal at the first end of the first capacitor as the fourth voltage signal, and keep the voltage signal at the first end of the second capacitor as the third voltage signal; when the second switch of the module is turned on and the first switch is turned off, output the average value of the third voltage signal and the fourth voltage signal to the post-stage module.

8. The circuit according to claim 5, characterized in that The signal sampling module includes a first capacitor, a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch; The first end of the first switch is connected to the input end of the signal sampling module, and the second end of the first switch is respectively connected to the first end of the first capacitor, the first end of the second switch, and the first end of the third switch; The second end of the first capacitor is grounded; The second end of the second switch is respectively connected to the output end of the signal sampling module, the first end of the third capacitor, and the second end of the fourth switch; The second end of the third capacitor is grounded; The first end of the second capacitor is connected to the second end of the third switch and the first end of the fourth switch respectively; The second terminal of the second capacitor is grounded; The plurality of first reset voltage signals include a first voltage signal, a second voltage signal, a third voltage signal, and a fourth voltage signal; The signal sampling module is specifically used for receiving the first voltage signal when the first switch and the second switch of the module are both turned on and the third switch and the fourth switch are both turned off, so that the voltage signal at the first end of the third capacitor is the first voltage signal; when the second switch of the module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the third capacitor as the first voltage signal, and receiving the second voltage signal, so that the voltage signal at the first end of the first capacitor is the second voltage signal; when the first switch and the second switch of the module are both turned off, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the first capacitor as the second voltage signal, and keeping the voltage signal at the first end of the third capacitor as the first voltage signal; when the second switch of the module is turned on, the first switch is turned off, and the third switch and the fourth switch are both turned off, obtaining the first reset sub-voltage signal; wherein the first reset sub-voltage signal is the average value of the first voltage signal and the second voltage signal; The signal sampling module is specifically used to maintain the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal and receive the third voltage signal when the second switch of the signal sampling module is turned off, the first switch is turned on, the third switch is turned on, and the fourth switch is turned off, so that the voltage signal at the first end of the second capacitor is the third voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, maintain the voltage signal at the first end of the second capacitor as the third voltage signal, maintain the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal, and receive the fourth voltage signal so that the voltage signal at the first end of the first capacitor is the fourth voltage signal; when the first switch and the second switch of the first capacitor are both turned off, and the third switch and the fourth switch are both turned off, the voltage signal at the first end of the first capacitor is maintained as the fourth voltage signal, the voltage signal at the first end of the second capacitor is maintained as the third voltage signal, and the voltage signal at the first end of the third capacitor is maintained as the first reset sub-voltage signal; when the first switch and the second switch of the first capacitor are both turned off, the third switch is turned on, and the fourth switch is turned off, the voltage signal at the first end of the third capacitor is maintained as the first reset sub-voltage signal, and a second reset sub-voltage signal is obtained; wherein the second reset sub-voltage signal is an average value of the third voltage signal and the fourth voltage signal; The signal sampling module is specifically used to keep the voltage signal at the first end of the second capacitor as the second reset sub-voltage signal, and keep the voltage signal at the first end of the third capacitor as the first reset sub-voltage signal when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off; and output the average value of the first reset sub-voltage signal and the second reset sub-voltage signal to the post-stage module when the first switch and the second switch of the signal sampling module are both turned off, the third switch is turned off, and the fourth switch is turned on.

9. The circuit according to claim 8, characterized in that The plurality of first image voltage signals include a fifth voltage signal, a sixth voltage signal, a seventh voltage signal, and an eighth voltage signal; The signal sampling module is specifically used for receiving the fifth voltage signal when the first switch and the second switch of the signal sampling module are both turned on and the third switch and the fourth switch are both turned off, so that the voltage signal at the first end of the third capacitor is the fifth voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the third capacitor as the fifth voltage signal, and receiving the sixth voltage signal, so that the voltage signal at the first end of the first capacitor is the sixth voltage signal; when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off, keeping the voltage signal at the first end of the first capacitor as the sixth voltage signal, and keeping the voltage signal at the first end of the third capacitor as the fifth voltage signal; when the second switch of the signal sampling module is turned on, the first switch is turned off, and the third switch and the fourth switch are both turned off, obtaining the first image sub-voltage signal; wherein the first image sub-voltage signal is the average value of the fifth voltage signal and the sixth voltage signal; The signal sampling module is specifically used to maintain the voltage signal at the first end of the third capacitor as the first image sub-voltage signal and receive the seventh voltage signal when the second switch of the signal sampling module is turned off, the first switch is turned on, the third switch is turned on, and the fourth switch is turned off, so that the voltage signal at the first end of the second capacitor is the seventh voltage signal; when the second switch of the signal sampling module is turned off, the first switch is turned on, and the third switch and the fourth switch are both turned off, maintain the voltage signal at the first end of the second capacitor as the seventh voltage signal, maintain the voltage signal at the first end of the third capacitor as the first image sub-voltage signal, and receive the eighth voltage signal so that the voltage signal at the first end of the first capacitor is the eighth voltage signal. the eighth voltage signal; when the first switch and the second switch are both turned off, and the third switch and the fourth switch are both turned off, the voltage signal at the first end of the first capacitor is maintained as the eighth voltage signal, the voltage signal at the first end of the second capacitor is maintained as the seventh voltage signal, and the voltage signal at the first end of the third capacitor is maintained as the first image sub-voltage signal; when the first switch and the second switch are both turned off, the third switch is turned on, and the fourth switch is turned off, the voltage signal at the first end of the third capacitor is maintained as the first image sub-voltage signal, and a second image sub-voltage signal is obtained; wherein the second image sub-voltage signal is an average value of the seventh voltage signal and the eighth voltage signal; The signal sampling module is specifically used to keep the voltage signal at the first end of the second capacitor as the second image sub-voltage signal, and keep the voltage signal at the first end of the third capacitor as the first image sub-voltage signal when the first switch and the second switch of the signal sampling module are both turned off and the third switch and the fourth switch are both turned off; and output the average value of the first image sub-voltage signal and the second image sub-voltage signal to the post-stage module when the first switch and the second switch of the signal sampling module are both turned off, the third switch is turned off and the fourth switch is turned on.

10. The circuit according to claim 5, characterized in that The circuit also includes a column-level amplification module; The output end of the PPD pixel module is connected to the input end of the column-level amplification module, and the output end of the column-level amplification module is connected to the input end of the signal sampling module; The column-level amplification module is used to collect the second reset voltage signal corresponding to the sensing node for multiple times, amplify each collected second reset voltage signal to obtain multiple first reset voltage signals, and output the multiple first reset voltage signals to the signal sampling module; The column-level amplification module is also used to collect the second image voltage signals corresponding to the sensing nodes multiple times, and amplify each collected second image voltage signal to obtain multiple first image voltage signals, and output the multiple first image voltage signals to the signal sampling module.

11. The circuit according to claim 10, characterized in that The column-level amplification module includes an amplifier, an input capacitor, a feedback capacitor, a load capacitor, and a transistor switch; The first end of the input capacitor is connected to the input end of the column-level amplification module, and the second end of the input capacitor is respectively connected to the first end of the transistor switch, the first end of the feedback capacitor, and the input end of the amplifier; The output end of the amplifier is respectively connected to the second end of the transistor switch, the second end of the feedback capacitor, the first end of the load capacitor, and the output end of the column-level amplification module; The second terminal of the load capacitor is grounded.

12. The circuit according to claim 5, characterized in that The circuit also includes an analog-to-digital conversion module; The input end of the analog-to-digital conversion module is connected to the output end of the signal sampling module, and the output end of the analog-to-digital conversion module is used to connect to a subsequent circuit; The analog-to-digital conversion module is used to receive an average value of the plurality of first reset voltage signals, convert the average value of the plurality of first reset voltage signals into a first digital signal, and transmit the first digital signal to the subsequent circuit; The analog-to-digital conversion module is further used to receive an average value of the multiple first image voltage signals, convert the average value of the multiple first image voltage signals into a second digital signal, and transmit the second digital signal to the subsequent circuit.

13. An image sensor, characterized in that: The image sensor comprises the image sensing circuit described in any one of claims 1-12.

14. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in claim 13 above.

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