Master synchronization method and device, base station communication equipment and readable storage medium

Abstract

The invention relates to a master synchronization method and device, base station communication equipment and a computer readable storage medium. The method comprises the following steps: receiving a primary synchronization signal PSS sequence serially issued by a central processing unit (CPU), and determining a correlation sequence of a downlink synchronization signal and the current PSS sequence; when the correlation sequence meets a preset condition, performing primary synchronization according to the current PSS sequence; the preset condition comprises that the correlation peak value of the correlation sequence exceeds a first preset threshold. By adopting the method, resource occupation can be reduced.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a master synchronization method, apparatus, base station communication equipment, and computer-readable storage medium. Background Art

[0002] The terminal needs to go through the cell search process to access the 5G New Radio (NR) network. The cell search process includes establishing / maintaining clock and frequency synchronization between the terminal and the base station. Currently, the primary synchronization signal (PSS) and the secondary synchronization signal (SSS) are defined for cell search. Among them, PSS is the first signal that the terminal uses to search for a cell to access the 5G NR network. It is used to transmit (Parameters used to determine the cell identity). Whether the PSS synchronization sequence can be effectively and quickly detected to achieve primary synchronization is the key to user access to the network.

[0003] In current distributed base stations, three groups of PSS sequences are usually pre-stored in a field programmable gate array (FPGA), and the downlink synchronization signal is correlated with the three groups of PSS sequences in parallel. The maximum correlation peak is found in the obtained correlation sequence, and the PSS sequence corresponding to the maximum correlation peak and the peak position of the maximum correlation peak are obtained. Based on this, the However, since three groups of PSS sequences need to be stored in the FPGA, this master synchronization method occupies multiple DSP resources at the same time, resulting in a problem of high resource usage. Summary of the invention

[0004] Based on this, it is necessary to provide a master synchronization method, apparatus, base station communication equipment, computer-readable storage medium and computer program product that can reduce resource occupation in order to address the above technical problems.

[0005] In a first aspect, the present application provides a master synchronization method, which is applied to a field programmable gate array FPGA of a base station, comprising:

[0006] Receive the main synchronization signal PSS sequence serially sent by the central processing unit CPU, and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence;

[0007] When the correlation sequence meets a preset condition, primary synchronization is performed according to the current PSS sequence; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

[0008] In a second aspect, the present application further provides a master synchronization method, which is applied to a central processing unit (CPU) of a base station, and includes:

[0009] Obtain a primary synchronization signal PSS sequence;

[0010] The PSS sequence is serially sent to a field programmable gate array FPGA so that the FPGA determines a correlation sequence between a downlink synchronization signal and a current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets a preset condition.

[0011] In a third aspect, the present application further provides a master synchronization device, which is applied to a field programmable gate array FPGA of a base station, comprising:

[0012] A receiving module is used to receive a primary synchronization signal PSS sequence serially sent by a central processing unit CPU, and determine a correlation sequence between a downlink synchronization signal and a current PSS sequence;

[0013] The detection module is used to perform primary synchronization according to the current PSS sequence when the correlation sequence meets a preset condition; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

[0014] In a fourth aspect, the present application further provides a master synchronization device, which is applied to a central processing unit (CPU) of a base station, and includes:

[0015] An acquisition module, used for acquiring a primary synchronization signal PSS sequence;

[0016] The sending module is used to serially send the PSS sequence to the field programmable gate array FPGA, so that the FPGA determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0017] In a fifth aspect, the present application also provides a base station communication device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the first aspect or the second aspect are implemented.

[0018] In a sixth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method described in any one of the first aspect or the second aspect are implemented.

[0019] In a seventh aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method described in any one of the first aspect or the second aspect.

[0020] The above-mentioned main synchronization method, device, base station communication equipment, computer-readable storage medium and computer program product determine the correlation sequence between the downlink synchronization signal and the current PSS sequence by receiving the main synchronization signal PSS sequence serially sent by the central processing unit CPU. When the correlation sequence meets the preset conditions, the main synchronization is performed according to the current PSS sequence. The preset conditions include that the correlation peak of the correlation sequence exceeds the first preset threshold; each group of PSS sequences can be pre-stored in the central processing unit (CPU) outside the FPGA. During the main synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one group of PSS sequences at any time, reducing resource occupation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a flowchart of parallel PSS synchronization in FPGA;

[0023] Figure 2 is a flowchart of a master synchronization method in one embodiment;

[0024] Figure 3 is a flowchart of a master synchronization method in another embodiment;

[0025] Figure 4 A schematic diagram of a flow chart of a PSS synchronization method based on FPGA and CPU in one embodiment;

[0026] Figure 5 An interactive flow chart of a PSS synchronization method based on FPGA and CPU in one embodiment;

[0027] Figure 6 The figure is an interactive flow chart of a main synchronization method in one embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0030] In traditional technology, reference Figure 1 The main synchronization of the distributed base station is to store three groups of PSS sequences in FPGA in advance. After the FPGA performs frequency shifting, downsampling, filtering and other processing on the received signal, the processed received signal is correlated with the three groups of PSS sequences in parallel to obtain three groups of correlation sequences. The correlation peak of each group of correlation sequences is determined, and the maximum correlation peak is selected. If the maximum correlation peak is higher than the preset correlation peak threshold, the PSS sequence corresponding to the maximum correlation peak is determined. , completing the main synchronization. It can be seen that in the traditional technology, three groups of PSS sequences need to be stored in the FPGA, and multiple groups of DSP are occupied at the same time, which has the problem of occupying more resources.

[0031] Based on the above-mentioned traditional technology, the main synchronization method provided in the embodiment of the present application pre-stores three groups of PSS sequences in the CPU outside the FPGA. When main synchronization is required, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one group of PSS sequences at any time, thereby reducing resource usage.

[0032] It should be noted that the beneficial effects brought about by the embodiments of the present application or the technical problems solved are not limited to this one, but may also include other implicit or related problems. For details, please refer to the description of the following embodiments.

[0033] In an exemplary embodiment, Figure 2 As shown, a master synchronization method is provided, which is described by taking the method applied to an FPGA of a base station (including but not limited to a pico base station) as an example, and includes the following steps:

[0034] Step S102, receiving a primary synchronization signal PSS sequence serially sent by a central processing unit CPU, and determining a correlation sequence between a downlink synchronization signal and a current PSS sequence.

[0035] The current PSS sequence may be a PSS sequence currently sent by the CPU. The downlink synchronization signal may be a synchronization signal used for cell search, including but not limited to a synchronization signal block (Synchronization Signal and PBCHblock, SSB). The correlation sequence may be a result obtained by performing correlation calculation on the downlink synchronization signal and the current PSS sequence.

[0036] In a specific implementation, an FPGA and a CPU may be provided in the base station. The FPGA is connected to the CPU. Three PSS sequences are pre-stored in the CPU. When main synchronization is required, the CPU may serially send the three PSS sequences to the FPGA. The FPGA may calculate the correlation sequence of a currently received PSS sequence, i.e., the current PSS sequence, with the downlink synchronization signal.

[0037] For example, three sets of local PSS sequences can be pre-stored in the CPU , , When a downlink synchronization signal is detected in the FPGA, the CPU can first send the first group of local PSS sequences Send to FPGA, FPGA storage And calculate the downlink synchronization signal and The correlation sequence between .

[0038] Step S104: when the correlation sequence meets a preset condition, primary synchronization is performed according to the current PSS sequence; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

[0039] The preset condition may be a preset selection condition of a PSS sequence for primary synchronization. The correlation peak may be a maximum correlation peak of the correlation sequence. The first preset threshold may be a preset correlation peak threshold.

[0040] In the specific implementation, the FPGA can determine whether the current PSS sequence and the related sequence of the downlink synchronization signal meet the preset conditions. If they meet the preset conditions, the main synchronization is performed according to the current PSS sequence. Otherwise, if it does not meet the preset conditions, it continues to receive the next PSS sequence sent by the CPU, updates the current PSS sequence to the next PSS sequence to save storage resources, and continues to detect whether the next PSS sequence and the related sequence of the downlink synchronization signal meet the preset conditions.

[0041] For example, the FPGA can determine the relevant sequence Whether the maximum correlation peak exceeds the preset correlation peak threshold, if it exceeds the correlation peak threshold, then according to the first group of local PSS sequence Sure , otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA continues to receive the second group of local PSS sequences sent by the CPU. ,Will Updated to , calculate the downlink synchronization signal and The correlation sequence between ,judge Whether the maximum correlation peak exceeds the correlation peak threshold.

[0042] The above-mentioned main synchronization method determines the correlation sequence between the downlink synchronization signal and the current PSS sequence by receiving the main synchronization signal PSS sequence serially sent by the central processing unit CPU. When the correlation sequence meets the preset conditions, the main synchronization is performed according to the current PSS sequence. The preset conditions include that the correlation peak of the correlation sequence exceeds the first preset threshold. Each group of PSS sequences can be pre-stored in the CPU outside the FPGA. During the main synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one group of PSS sequences at any time, reducing resource occupation.

[0043] In an exemplary embodiment, the above-mentioned main synchronization method may further specifically include: when the relevant sequence does not meet the preset conditions, receiving the next PSS sequence of the current PSS sequence, and updating the current PSS sequence to the next PSS sequence; detecting whether the relevant sequence of the downlink synchronization signal and the next PSS sequence meets the preset conditions.

[0044] In the specific implementation, if the FPGA determines that the current PSS sequence and the related sequence of the downlink synchronization signal do not meet the preset conditions, it can continue to receive the next PSS sequence sent by the CPU, update the current PSS sequence to the next PSS sequence, and detect whether the next PSS sequence and the related sequence of the downlink synchronization signal meet the preset conditions. If they meet the preset conditions, the main synchronization is performed according to the next PSS sequence. Otherwise, if they do not meet the preset conditions, the above process is repeated, and the next PSS sequence sent by the CPU is continued to be received, and the next PSS sequence and the related sequence of the downlink synchronization signal are detected. Whether it meets the preset conditions.

[0045] For example, if the FPGA determines the relevant sequence If the maximum correlation peak does not exceed the correlation peak threshold, the second group of local PSS sequences sent by the CPU will continue to be received. , the previously stored Updated to , calculate the downlink synchronization signal and The correlation sequence between ,judge Whether the maximum correlation peak exceeds the correlation peak threshold, if it exceeds the correlation peak threshold, then according to the second group of local PSS sequence Sure , otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA continues to receive the third group of local PSS sequences sent by the CPU. ,Will Updated to , calculate the downlink synchronization signal and The correlation sequence between ,judge Whether the maximum correlation peak exceeds the correlation peak threshold, if it exceeds the correlation peak threshold, then according to the third group of local PSS sequence Sure , otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA determines that the main synchronization cannot be achieved.

[0046] In this embodiment, when the related sequence does not meet the preset conditions, the next PSS sequence of the current PSS sequence is received, the current PSS sequence is updated to the next PSS sequence, and the related sequence of the downlink synchronization signal and the next PSS sequence is detected whether it meets the preset conditions. Each PSS sequence serially sent down by the CPU can be detected in turn to reduce resource usage.

[0047] In an exemplary embodiment, the above-mentioned main synchronization method may further specifically include: determining the power value of the synchronization signal block SSB; reporting the power value to the CPU so that the CPU serially sends down the PSS sequence according to the power value.

[0048] In a specific implementation, the FPGA can extract the signal at the location of the SSB from the received signal, calculate the power value of the signal, and report the power value to the CPU. The CPU determines whether the received power value exceeds the second preset threshold. If it exceeds the second preset threshold, the synchronization process is started, and the CPU sends the PSS sequence to the FPGA serially. Otherwise, if the power value received by the CPU does not exceed the second preset threshold, the synchronization process is not started, and the CPU stays in a waiting state. The second preset threshold can be a pre-set SSB detection power.

[0049] In this embodiment, by determining the power value of the synchronization signal block SSB, the power value is reported to the CPU so that the CPU can serially send the PSS sequence according to the power value. When the arrival of SSB is detected, the synchronization process can be started, so that the CPU can serially send three groups of local PSS sequences to the FPGA to avoid waste of resources.

[0050] In an exemplary embodiment, the above step S102 may specifically include: receiving the SSB frequency sent by the CPU, and the PSS sequence sent by the CPU in turn for the SSB frequency.

[0051] Among them, the SSB frequency point can be a frequency band for main synchronization.

[0052] In a specific implementation, when the synchronization process starts, the CPU can send the SSB frequency points to the FPGA in sequence, and for each SSB frequency point, send three PSS sequences in turn, and the FPGA receives each SSB frequency point and its corresponding three PSS sequences.

[0053] For example, in addition to pre-storing three sets of local PSS sequences, the CPU can also pre-store SSB frequency information. When an SSB is detected, the CPU can first send the first SSB frequency to the FPGA, and then send three sets of local PSS sequences in serial order. , , Then, the CPU can send the second SSB frequency to the FPGA, and then send three sets of local PSS sequences in serial order. , , , and so on, until the last SSB frequency.

[0054] It is understandable that the FPGA can update the original SSB frequency to the new SSB frequency, or update the original PSS sequence to the new PSS sequence every time a new SSB frequency or a new PSS sequence is received, so as to further reduce resource usage.

[0055] In this embodiment, by receiving the SSB frequency sent by the CPU and the PSS sequence sent by the CPU in turn for the SSB frequency, the main synchronization of different SSB frequencies can be achieved, thereby improving the accuracy of cell synchronization.

[0056] In an exemplary embodiment, the above step S102 may specifically include: performing correlation processing on the downlink synchronization signal and the current PSS sequence to obtain a correlation sequence.

[0057] In a specific implementation, the FPGA can perform correlation calculation on the downlink synchronization signal and the current PSS sequence sent by the CPU to obtain a correlation sequence corresponding to the current PSS sequence.

[0058] In practical applications, FPGA can perform frequency shifting, downsampling, filtering and other processing on the received signal to obtain the downlink synchronization signal, and slide-correlate the downlink synchronization signal with a set of local PSS sequences currently sent by the CPU to obtain the correlation sequence , the specific formula can be

[0059] ,

[0060] in, A set of local PSS sequences currently sent by the CPU. is the downlink synchronization signal, is the time domain data index, is the length of the PSS sequence.

[0061] It can be understood that the current PSS sequence can be the three groups of local PSS sequences in the above embodiment. , , In other words, FPGA can synchronize the downlink synchronization signal with the current downlink signal from CPU. , or Perform correlation calculations to obtain the corresponding correlation sequence , or .

[0062] In this embodiment, by correlating the downlink synchronization signal with the current PSS sequence to obtain a correlation sequence, the received downlink synchronization signal can be correlated with the PSS sequence currently sent by the CPU, and the cell identifier can be determined based on the result of the correlation calculation to improve the accuracy of cell synchronization.

[0063] In an exemplary embodiment, Figure 3 As shown, a main synchronization method is provided, which is described by taking the method applied to the CPU of a base station as an example, and includes the following steps:

[0064] Step S202, obtaining a primary synchronization signal PSS sequence;

[0065] Step S204, the PSS sequence is serially sent to the field programmable gate array FPGA, so that the FPGA determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0066] In the specific implementation, three PSS sequences can be determined in advance and stored in the CPU. When main synchronization is required, the CPU sends three PSS sequences serially to the FPGA. The FPGA calculates the correlation sequence between the currently received PSS sequence, that is, the current PSS sequence, and the downlink synchronization signal. If the maximum correlation peak of the calculated correlation sequence exceeds the preset correlation peak threshold, main synchronization is performed according to the current PSS sequence.

[0067] Since the specific processing process of the CPU has been described in detail in the above embodiments, it will not be repeated here.

[0068] In this embodiment, by obtaining the main synchronization signal PSS sequence, the PSS sequence is serially sent to the field programmable gate array FPGA; each group of PSS sequences can be pre-stored in the CPU outside the FPGA. During the main synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one group of PSS sequences at any time, reducing resource usage.

[0069] In an exemplary embodiment, the above-mentioned master synchronization method may further specifically include: when the relevant sequence read from the FPGA does not meet the preset conditions, sending the next PSS sequence of the current PSS sequence to the FPGA; when the relevant sequence read from the FPGA meets the preset conditions, stopping sending the PSS sequence.

[0070] In the specific implementation, the CPU can read from the FPGA whether the maximum correlation peak of the current correlation sequence exceeds the correlation peak threshold. If it does not exceed the correlation peak threshold, it means that the current correlation sequence does not meet the preset conditions. The CPU can continue to send the next PSS sequence to the FPGA for FPGA detection. Otherwise, if the maximum correlation peak of the current correlation sequence exceeds the correlation peak threshold, it means that the current correlation sequence meets the preset conditions. The FPGA can perform main synchronization according to the current PSS sequence, and stop sending the PSS sequence at this time.

[0071] In this embodiment, when the relevant sequence read from the FPGA does not meet the preset conditions, the next PSS sequence of the current PSS sequence is sent to the FPGA, and when the relevant sequence read from the FPGA meets the preset conditions, the sending of the PSS sequence is stopped. Information on whether to continue to send the PSS sequence can be obtained from the FPGA, thereby realizing sequential detection of PSS sequences and reducing resource usage.

[0072] In an exemplary embodiment, the above step S204 may specifically include: receiving the power value of the synchronization signal block SSB reported by the FPGA; when the power value exceeds a second preset threshold, serially sending a PSS sequence to the FPGA.

[0073] In the specific implementation, the FPGA can extract the signal at the SSB location from the received signal, calculate the power value of the signal, and report the power value to the CPU. The CPU determines whether the received power value exceeds the second preset threshold. If it exceeds the second preset threshold, the synchronization process is started and the PSS sequence is sent serially to the FPGA. Otherwise, if the power value received by the CPU does not exceed the second preset threshold, the synchronization process is not started and the CPU remains in a waiting state.

[0074] In this embodiment, by receiving the power value of the synchronization signal block SSB reported by the FPGA, when the power value exceeds the second preset threshold, the PSS sequence is serially sent to the FPGA. When the arrival of SSB is detected, the synchronization process can be started, so that the CPU can serially send three groups of local PSS sequences to the FPGA to avoid waste of resources.

[0075] In an exemplary embodiment, the above step S202 may specifically include: determining a pseudo-random sequence; performing subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence; and performing orthogonal frequency division multiplexing on the subcarrier sequence to obtain a PSS sequence.

[0076] The pseudo-random sequence includes but is not limited to an m-sequence. The orthogonal frequency division multiplexing (OFDM) process may be an inverse Fourier transform process in the orthogonal frequency division multiplexing.

[0077] In the specific implementation, the CPU can determine three pseudo-random sequences. For each pseudo-random sequence, it is first mapped to a subcarrier to obtain a corresponding subcarrier sequence, and then the subcarrier sequence is orthogonal frequency division multiplexing modulated together with other subcarriers to obtain a corresponding PSS time domain signal. The PSS timing signal can be stored on the CPU as a PSS sequence.

[0078] In practical applications, the PSS sequence in 5G NR is used to transmit , SSS sequence is used to transmit , the physical cell identifier (PCI) can be determined based on the PSS sequence and SSS sequence. The specific formula is: ,in, , , thus 1008 PCIs can be defined. The PSS sequence can be an m-sequence with a length of 127, and the specific formula is

[0079] ,

[0080] in, ,

[0081] ,

[0082] correspond There are three types of m-sequences, and only one type can be used in a physical cell. For each m-sequence, the m-sequence can be mapped to a subcarrier to obtain a subcarrier sequence consisting of 127 consecutive subcarriers. The subcarrier sequence is a frequency domain sequence. The subcarrier sequence can be modulated together with other subcarriers in the transmission bandwidth through orthogonal frequency division multiplexing to obtain a corresponding time domain signal. The time domain signal corresponding to the subcarrier sequence is used as a PSS sequence and stored on the CPU. Therefore, three sets of local PSS sequences can be pre-stored on the CPU.

[0083] It should be noted that this embodiment can be executed by, but is not limited to, a CPU. For example, it can also be executed by a base station, a terminal, or a core network, as long as the obtained three PSS sequences can be stored in the CPU.

[0084] In this embodiment, by determining a pseudo-random sequence, performing subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence, and performing orthogonal frequency division multiplexing on the subcarrier sequence to obtain a PSS sequence, three groups of PSS sequences can be stored in advance on the CPU, reducing the storage resources and processing resources of the FPGA and reducing resource usage.

[0085] In order to facilitate those skilled in the art to have a deeper understanding of the embodiments of the present application, a specific example will be described below.

[0086] This application proposes a low-cost PSS synchronization method based on FPGA and CPU, which can reduce the demand for analog to digital converters (ADC) and FPGA, thereby reducing the overall implementation cost. First, this application uses FPGA and CPU to jointly decode synchronization information, FPGA performs PSS synchronization, CPU sends PSS sequence, and performs subsequent SSS synchronization, etc., which can reduce the overall implementation cost while reducing the resources occupied by the FPGA synchronization module; secondly, the CPU uses the method of polling and sending three groups of PSS sequences to FPGA, and the FPGA internal serially performs related calculations on the three groups of PSS sequences, which can save FPGA resources while reducing the overall implementation cost. The low-cost PSS synchronization system based on this method is composed of FPGA module and CPU module, which cooperate to achieve PSS synchronization and reduce the overall implementation cost.

[0087] Figure 4 A flowchart of a low-cost PSS synchronization method based on FPGA and CPU is provided. Figure 4 , the PSS synchronization method may include the following steps:

[0088] Step S301, generating three groups of PSS sequences by cyclically shifting the basic m-sequence, modulating the three groups of PSS sequences into time domain signals, and storing the signals in the CPU.

[0089] In 5G NR, each physical cell identifier is determined by a combination of a PSS sequence and an SSS sequence. Compared to LTE's 504 PCIs, 5G NR provides greater cell deployment flexibility. Different from LTE's 504 physical cell identifiers, NR defines 1008 PCIs, of which: , .

[0090] The ZC sequence (Zadoff-Chu sequence) is a subcarrier phase sequence, which is a phase modulation at any angle. 5G application scenarios include high-frequency bands 5G-60GHz. The use of phase modulation at any angle causes the ZC sequence to have a larger frequency deviation at high frequencies, which affects its correlation, manifested as a decrease in the peak-to-peak value of the correlation and an increase in false detection. Therefore, the m sequence is used instead. The PSS sequence is a pseudo-random sequence with a length of 127. The specific formula is:

[0091] ,

[0092] in, ,

[0093] .

[0094] For a physical cell, the m-sequence can only be one of the three m-sequences. After the NR PSS m-sequence is mapped to the subcarrier, a subcarrier sequence consisting of 127 consecutive subcarriers is formed. The 127 subcarriers in the frequency domain are transformed with other subcarriers and modulated into OFDM time domain signals. The three groups of PSS time domain signals are stored in the CPU as PSS sequences.

[0095] Step S302, the CPU reads the SSB power inside the FPGA and determines whether the SSB power is greater than the threshold value. When the SSB power is greater than the threshold value, the synchronization process starts.

[0096] After the FPGA performs frequency shifting, downsampling, filtering and other processing on the received signal, it calculates the SSB power value and uploads the SSB power value to the CPU. After the CPU reads the SSB power value, it determines whether it is greater than the preset threshold (the second preset threshold). If it is less than or equal to the preset threshold, it stays in the waiting state. If it is greater than the preset threshold, the synchronization process is started.

[0097] In step S303, the CPU sends each group of PSS sequence and SSB frequency information in serial to the FPGA.

[0098] The three groups of PSS sequences in the time domain and information including SSB frequency points are stored in the CPU in advance. After the synchronization process is triggered, the CPU sends the SSB frequency points in turn, and then sends the three groups of PSS sequences in turn after sending the SSB frequency points. The FPGA processes the PSS sequence sent by the CPU through the overload coefficient module for related calculations. Each time the CPU sends a new group of PSS sequences, the FPGA refreshes the stored PSS sequence.

[0099] Step S304: FPGA serially correlates the received downlink synchronization signal with three groups of PSS sequences in the time domain.

[0100] FPGA filters out PSS information (downlink synchronization signal) from the received signal by frequency shifting, downsampling, filtering, etc., and performs sliding correlation between the information and the PSS sequence sent by the CPU. The relevant expression is: ,in, PSS sequence sent by the CPU. is the downsampled downlink received signal (downlink synchronization signal), is the time domain data index, Send the PSS sequence length to the CPU.

[0101] Step S305, finding three groups of correlation maximum values, the PSS sequence corresponding to the correlation peak value is the synchronization sequence, and the corresponding position is the PSS synchronization point.

[0102] If the calculation result is 0, it means that the PSS sequence in the received signal is not in the same group as the sequence sent by the CPU; if the calculation result is not 0, it means that the PSS sequence in the received signal is not in the same group as the sequence sent by the CPU, but it may be other interference signals; if the calculation result is not 0, and the calculation result is the predetermined maximum value (the maximum correlation peak exceeds the correlation peak threshold), it means that the PSS sequence in the received signal is in the same group as the sequence sent by the CPU, and the cell is obtained. .

[0103] Figure 5 Provides an interactive flow chart of the PSS synchronization method based on FPGA and CPU. Figure 5FPGA can perform frequency shifting, downsampling, filtering and other processing on the received signal, extract SSB from the received signal, calculate the SSB power value, CPU reads the SSB power value, detects whether the SSB power value is greater than the second preset threshold, if it is less than or equal to the second preset threshold, maintains the waiting state, and continues to read the SSB power value, if it is greater than the second preset threshold, then the SSB frequency point information and three groups of PSS sequences are serially sent to FPGA, FPGA reloads the currently sent PSS sequence, and performs correlation calculation on the received downlink synchronization signal and the currently sent PSS sequence to obtain a group of correlation sequences, if the maximum correlation peak of the correlation sequence exceeds the PSS threshold (the first preset threshold or the correlation peak threshold), the main synchronization process is completed, otherwise, if the maximum correlation peak of the correlation sequence does not exceed the PSS threshold, the CPU continues to send the next group of PSS sequences, and repeats the above-mentioned correlation sequence calculation and correlation peak detection process until the maximum correlation peak exceeds the PSS threshold, and the main synchronization is performed according to the corresponding PSS sequence.

[0104] The above-mentioned PSS synchronization method adopts the collaboration between FPGA and CPU to store three groups of PSS sequences in the CPU in advance. When the CPU detects that the SSB power is greater than the threshold, the three groups of PSS coefficients are polled and sent to the FPGA. The FPGA internally performs correlation calculations on the three groups of PSS sequences in series to find correlation peaks, find the corresponding PSS sequence and position, and realize the PSS synchronization function; the FPGA and CPU can be used to jointly decode the synchronization information, reduce the resources occupied by the FPGA synchronization module, and reduce the overall implementation cost; the CPU adopts the method of polling and sending the three groups of PSS coefficients to the FPGA, and the FPGA internally performs correlation calculations on the three groups of PSS sequences in series, saving FPGA resources while reducing the overall implementation cost.

[0105] In one embodiment, Figure 6 As shown, a master synchronization method is provided, comprising the following steps:

[0106] Step S401, determining three pseudo-random sequences, performing subcarrier mapping on each pseudo-random sequence to obtain three subcarrier sequences, performing orthogonal frequency division multiplexing processing on the three subcarrier sequences to obtain three PSS sequences, and storing the three PSS sequences in the CPU;

[0107] Step S402, FPGA reports the power value of the synchronization signal block SSB to the CPU;

[0108] Step S403, the CPU detects whether the power value exceeds the second preset threshold, and when it is detected that the power value exceeds the second preset threshold, sends the first PSS sequence to the FPGA;

[0109] Step S404, the FPGA determines a correlation sequence between a downlink cell synchronization signal and a first PSS sequence;

[0110] Step S405, if the relevant sequence meets the preset conditions, the FPGA performs main synchronization according to the first PSS sequence;

[0111] Step S406, if the relevant sequence does not meet the preset condition, the CPU sends a second PSS sequence to the FPGA;

[0112] Step S407, the FPGA determines a correlation sequence between the downlink cell synchronization signal and the second PSS sequence;

[0113] Step S408, if the relevant sequence meets the preset condition, the FPGA performs main synchronization according to the second PSS sequence;

[0114] Step S409, if the relevant sequence does not meet the preset condition, the CPU sends the third PSS sequence to the FPGA;

[0115] Step S410, the FPGA determines a correlation sequence between a downlink cell synchronization signal and a third PSS sequence;

[0116] Step S411: If the relevant sequence meets the preset condition, the FPGA performs main synchronization according to the third PSS sequence.

[0117] In a specific implementation, three pseudo-random sequences can be subcarrier mapped and OFDM modulated to obtain three PSS sequences, and the three PSS sequences are stored in the CPU. The FPGA reports the SSB power value to the CPU. The CPU detects whether the received SSB power value exceeds the second preset threshold. If it exceeds, the first PSS sequence is sent to the FPGA. The FPGA performs correlation calculation on the downlink synchronization signal and the first PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, the main synchronization is performed according to the first PSS sequence. Otherwise, if the maximum correlation peak of the correlation sequence does not exceed the correlation peak threshold, the CPU continues to send the SSB power value to the FPGA. GA sends the second PSS sequence, FPGA refreshes the PSS sequence, and correlates the downlink synchronization signal with the current second PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, the main synchronization is performed according to the second PSS sequence. Otherwise, if the maximum correlation peak of the correlation sequence does not exceed the correlation peak threshold, the CPU continues to send the third PSS sequence to FPGA, FPGA refreshes the PSS sequence, and correlates the downlink synchronization signal with the current third PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, the main synchronization is performed according to the third PSS sequence.

[0118] Among them, refreshing the PSS sequence of FPGA can be understood as deleting the previously stored PSS sequence and storing the PSS sequence issued by the current CPU, or it can be understood as updating the previously stored PSS sequence to the PSS sequence issued by the current CPU. In addition, when the CPU issues a new PSS sequence, in addition to refreshing the PSS sequence, the FPGA can also refresh the previously stored related sequences, maximum related peaks, etc., to further reduce resource usage.

[0119] The above-mentioned main synchronization method determines the correlation sequence between the downlink synchronization signal and the current PSS sequence by receiving the main synchronization signal PSS sequence serially sent by the central processing unit CPU. When the correlation sequence meets the preset conditions, the main synchronization is performed according to the current PSS sequence. The preset conditions include that the correlation peak of the correlation sequence exceeds the first preset threshold. Each group of PSS sequences can be pre-stored in the CPU outside the FPGA. During the main synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one group of PSS sequences at any time, reducing resource occupation.

[0120] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0121] Based on the same inventive concept, the embodiment of the present application also provides a main synchronization device for implementing the main synchronization method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more main synchronization device embodiments provided below can refer to the limitations on the main synchronization method above, and will not be repeated here.

[0122] In an exemplary embodiment, a master synchronization device is provided, the device being applied to a field programmable gate array FPGA of a base station, comprising:

[0123] A receiving module is used to receive a primary synchronization signal PSS sequence serially sent by a central processing unit CPU, and determine a correlation sequence between a downlink synchronization signal and a current PSS sequence;

[0124] The detection module is used to perform primary synchronization according to the current PSS sequence when the correlation sequence meets a preset condition; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

[0125] In an exemplary embodiment, the above-mentioned detection module is also used to receive the next PSS sequence of the current PSS sequence and update the current PSS sequence to the next PSS sequence when the related sequence does not meet the preset condition; and detect whether the related sequence of the downlink synchronization signal and the next PSS sequence meets the preset condition.

[0126] In an exemplary embodiment, the above-mentioned main synchronization device also includes a reporting module for determining a power value of a synchronization signal block SSB; reporting the power value to the CPU so that the CPU serially sends down the PSS sequence according to the power value.

[0127] In an exemplary embodiment, the above-mentioned receiving module is also used to receive the SSB frequency sent by the CPU, and the PSS sequence sent by the CPU in turn for the SSB frequency.

[0128] In an exemplary embodiment, the above-mentioned receiving module is further used to perform correlation processing on the downlink synchronization signal and the current PSS sequence to obtain the correlation sequence.

[0129] In an exemplary embodiment, another master synchronization device is provided, the device is applied to a central processing unit (CPU) of a base station, and includes:

[0130] An acquisition module, used for acquiring a primary synchronization signal PSS sequence;

[0131] The sending module is used to serially send the PSS sequence to the field programmable gate array FPGA, so that the FPGA determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0132] In an exemplary embodiment, the above-mentioned sending module is also used to send the next PSS sequence of the current PSS sequence to the FPGA when the related sequence read from the FPGA does not meet the preset condition; when the related sequence read from the FPGA meets the preset condition, stop sending the PSS sequence.

[0133] In an exemplary embodiment, the above-mentioned sending module is also used to receive the power value of the synchronization signal block SSB reported by the FPGA; when the power value exceeds a second preset threshold, the PSS sequence is serially sent to the FPGA.

[0134] In an exemplary embodiment, the acquisition module is further used to determine a pseudo-random sequence; perform subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence; and perform orthogonal frequency division multiplexing on the subcarrier sequence to obtain the PSS sequence.

[0135] Each module in the above master synchronization device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a communication device in the form of hardware, or can be stored in a memory in a communication device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0136] In an exemplary embodiment, a communication device is provided, which may be a base station. The communication device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the communication device is used to provide computing and control capabilities. The memory of the communication device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the communication device is used to store master synchronization data. The input / output interface of the communication device is used to exchange information between the processor and an external device. The communication interface of the communication device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a master synchronization method is implemented.

[0137] Those skilled in the art will understand that the above structure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the communication device to which the scheme of the present application is applied. The specific communication device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0138] In one embodiment, a base station communication device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0139] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0140] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0141] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0142] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0143] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0144] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A master synchronization method, characterized in that: The method is applied to a field programmable gate array FPGA of a base station, and comprises: Receive the main synchronization signal PSS sequence serially sent by the central processing unit CPU, and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence; When the correlation sequence meets a preset condition, primary synchronization is performed according to the current PSS sequence; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

2. The master synchronization method according to claim 1, characterized in that: The method further comprises: When the related sequence does not meet the preset condition, receiving a next PSS sequence of the current PSS sequence, and updating the current PSS sequence to the next PSS sequence; Detect whether a correlation sequence between the downlink synchronization signal and the next PSS sequence meets the preset condition.

3. The master synchronization method according to claim 1, characterized in that: The method further comprises: Determining a power value of a synchronization signal block SSB; The power value is reported to the CPU, so that the CPU sends the PSS sequence serially according to the power value.

4. The master synchronization method according to claim 1, characterized in that: The receiving CPU serially sends a PSS sequence, including: Receive the SSB frequency sent by the CPU, and the PSS sequence sent by the CPU in turn for the SSB frequency.

5. The master synchronization method according to claim 1, characterized in that: The determining of a correlation sequence between a downlink synchronization signal and a current PSS sequence includes: The downlink synchronization signal is correlated with the current PSS sequence to obtain the correlation sequence.

6. A master synchronization method, characterized in that: The method is applied to a central processing unit (CPU) of a base station, and includes: Obtain a primary synchronization signal PSS sequence; The PSS sequence is serially sent to a field programmable gate array FPGA so that the FPGA determines a correlation sequence between a downlink synchronization signal and a current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets a preset condition.

7. The master synchronization method according to claim 6, characterized in that: The method further comprises: When the related sequence read from the FPGA does not meet the preset condition, sending a next PSS sequence of the current PSS sequence to the FPGA; When the related sequence read from the FPGA meets the preset condition, the PSS sequence is stopped from being sent.

8. The master synchronization method according to claim 6, characterized in that: The step of sending the PSS sequence serially to the FPGA includes: Receiving the power value of the synchronization signal block SSB reported by the FPGA; When the power value exceeds a second preset threshold, the PSS sequence is serially sent to the FPGA.

9. The master synchronization method according to claim 6, characterized in that: The obtaining of the PSS sequence comprises: determining a pseudo-random sequence; Performing subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence; Orthogonal frequency division multiplexing is performed on the subcarrier sequence to obtain the PSS sequence.

10. A master synchronization device, characterized in that: The device is applied to a field programmable gate array FPGA of a base station, and comprises: A receiving module is used to receive a primary synchronization signal PSS sequence serially sent by a central processing unit CPU, and determine a correlation sequence between a downlink synchronization signal and a current PSS sequence; The detection module is used to perform primary synchronization according to the current PSS sequence when the correlation sequence meets a preset condition; the preset condition includes that a correlation peak value of the correlation sequence exceeds a first preset threshold.

11. A master synchronization device, characterized in that: The device is applied to a central processing unit (CPU) of a base station, and includes: An acquisition module, used for acquiring a primary synchronization signal PSS sequence; The sending module is used to serially send the PSS sequence to the field programmable gate array FPGA, so that the FPGA determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs main synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

12. A base station communication device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 or 6 to 9 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 or 6 to 9 are implemented.

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