Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure comprises a first dielectric layer and a conductive layer which are sequentially laminated from bottom to top; correspondingly forming an insulating layer on the side surface of each first dielectric layer; sequentially depositing a channel material layer, an isolating layer and a gate conducting layer on the side surface of each conducting layer and the surface of the insulating layer; removing each insulating layer to expose each channel material layer corresponding to each first dielectric layer; and removing each exposed channel material layer to obtain a channel layer on the side surface of each conductive layer. By adopting the preparation method of the semiconductor structure, the performance of the device can be improved, the normal work of the device is ensured, and the leakage current is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the 3D memory currently proposed is a memory with a new channel material. It uses metal oxide as the channel material and stacks multiple layers of transistor devices, which can improve the integration while ensuring the performance of the memory. In the related art, the surface of each dielectric layer that plays an insulating isolation role in the multi-layer stacked memory will also be deposited with channel materials, which will cause the upper and lower layers of devices to be connected through the channel material in the dielectric layer, thereby generating parasitic transistors. Therefore, the related art has the problem that parasitic transistors affect the normal operation of the device and increase the leakage current. Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure to address the problem of parasitic transistors in the related art.

[0004] In a first aspect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] providing a substrate;

[0006] forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked sequentially from bottom to top;

[0007] forming an insulating layer corresponding to the side surface of each layer of the first dielectric layer;

[0008] Depositing a channel material layer, an isolation layer and a gate conductive layer in sequence on the side surfaces of each conductive layer and the surface of the insulating layer;

[0009] Removing each insulating layer to expose each channel material layer corresponding to each first dielectric layer;

[0010] The exposed channel material layers are removed to obtain channel layers located on the sides of the conductive layers.

[0011] The method for preparing the semiconductor structure is as follows: a stacked structure is formed on the substrate, wherein the stacked structure includes a first dielectric layer and a conductive layer stacked sequentially from bottom to top; an insulating layer is formed corresponding to the side of each first dielectric layer; a channel material layer, an isolation layer and a gate conductive layer are sequentially deposited on the side of each conductive layer and the surface of the insulating layer; each insulating layer is removed to expose each channel material layer corresponding to each first dielectric layer; each exposed channel material layer is removed to obtain a channel layer located on the side of each conductive layer. Since each channel material layer corresponding to each conductive layer will not be exposed, and each channel material layer covering the side of each first dielectric layer will be completely exposed, the etching contact area of ​​the channel material layer can be increased by removing the channel material layer by etching process at this time, so that the channel material layer corresponding to each first dielectric layer can be quickly removed to quickly remove the parasitic transistor, and the channel layer on the side of each conductive layer can be retained without being damaged, thereby improving the device performance, ensuring the normal operation of the device and reducing the leakage current.

[0012] In one embodiment, each layer of the conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and the ends of the extensions connected to the main body are used as channel regions, and the insulating layer is formed correspondingly on the side of each layer of the dielectric layer, including:

[0013] Etching to form a first trench penetrating the channel region of each layer, wherein the sidewall of the first trench exposes the side surface of the first dielectric layer and the side surface of the conductive layer which are alternately stacked in sequence;

[0014] Based on the first grooves, each layer of the first dielectric layer is laterally etched to form a second groove between each layer of the conductive layer, wherein the bottom size of the second groove is smaller than the opening size of the second groove;

[0015] An insulating layer is formed at the bottom of each layer of the second trench, so that each layer of the insulating layer covers the side surface of each layer of the first dielectric layer.

[0016] In one embodiment, forming an insulating layer at the bottom of each layer of the second trench so that each layer of the insulating layer covers the side surface of each layer of the first dielectric layer includes:

[0017] forming a continuously distributed insulating material layer on the inner wall of the first trench and the inner wall of the second trench, wherein the thickness of the insulating material layer at the bottom of the second trench is greater than the thickness of the insulating material layer at the sidewall of the second trench;

[0018] The insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench are removed to obtain an insulating layer retained at the bottom of the second trench.

[0019] In one embodiment, removing the insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench includes:

[0020] The insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench are removed by a wet etching process.

[0021] In one embodiment, after forming the stacked structure on the substrate and before forming an insulating layer on the side of each layer of the first dielectric layer, the method further includes:

[0022] A third dielectric layer is deposited, wherein the third dielectric layer fills the gaps in the stacked structure.

[0023] In one embodiment, the portion of the extension portion away from the main body portion is used as a first electrode, and after depositing the third dielectric layer, the method further includes:

[0024] removing the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode;

[0025] A capacitor dielectric layer and a second electrode are sequentially formed on the exposed surface of the first electrode.

[0026] In one embodiment, removing each layer of the insulating layer to expose each layer of the channel material layer corresponding to each layer of the first dielectric layer includes:

[0027] forming a third trench penetrating the third dielectric layer between adjacent channel regions, so that the sidewalls of the third trench expose the surfaces of each insulating layer;

[0028] The insulating layers are removed based on the third trenches to expose the channel material layers corresponding to the first dielectric layers.

[0029] In one embodiment, the insulating layer is an aluminum oxide layer.

[0030] In one embodiment, forming a third trench penetrating the third dielectric layer between adjacent channel regions so that the sidewalls of the third trench expose the surfaces of each insulating layer includes:

[0031] Using a dry etching process to form a third trench penetrating the third dielectric layer between adjacent channel regions;

[0032] Acidic solution is used to etch and remove a portion of the third dielectric layer on the inner wall of the third trench to expose the surface of each aluminum oxide layer.

[0033] In one embodiment, the removing of each layer of the insulating layer based on the third trench comprises:

[0034] The aluminum oxide layers are removed based on the third groove by etching with an alkaline solution.

[0035] In one embodiment, after removing the exposed channel material layers to obtain the channel layers located on the sides of the conductive layers, the method further comprises:

[0036] The third trench is filled with a fourth filling layer.

[0037] In a second aspect, the present invention further provides a semiconductor structure, comprising:

[0038] substrate;

[0039] A stacked structure is located on the substrate, the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and the ends of the extensions connected to the main body serve as channel regions;

[0040] A gate conductive layer, penetrating through the channel regions of each layer and extending in a direction perpendicular to the substrate;

[0041] an isolation layer surrounding a side wall of the gate conductive layer;

[0042] The multi-layer channel layers surround the sidewalls of the isolation layer and are arranged at intervals in a direction perpendicular to the substrate, and each layer of the channel layers is in one-to-one contact with each layer of the conductive layer.

[0043] The semiconductor structure includes: a substrate; a stacked structure located on the substrate, the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer includes: a main body extending in a first direction and a plurality of extensions arranged at intervals along the first direction, each extension is located on two opposite sides of the main body, the main body is integrally connected to each extension, and the end of the extension connected to the main body is used as a channel region; a gate conductive layer, which penetrates each channel region and extends in a direction perpendicular to the substrate; an isolation layer, which surrounds the side wall of the gate conductive layer; a plurality of channel layers, which surround the side wall of the isolation layer and are arranged at intervals in a direction perpendicular to the substrate, and each channel layer is in one-to-one contact with each conductive layer. Since the channel material layer corresponding to each first dielectric layer can be quickly removed, the parasitic transistor can be quickly removed. The channel layer on the side of each conductive layer can be retained without being damaged, so that the normal reading and writing of the device can be guaranteed and the leakage current can be reduced.

[0044] In one embodiment, the semiconductor structure further includes a capacitor, which includes a first electrode, a capacitor dielectric layer and a second electrode sequentially covering the surface of the first electrode, and a portion of the extension away from the main body serves as the first electrode of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 2 is a flowchart of step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0048] Figure 3 A schematic diagram of a 3D structure of a structure obtained in step S201 in a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 4 A schematic diagram of a 3D structure of a structure obtained in step S202 in a method for preparing a semiconductor structure provided in an embodiment;

[0050] Figure 5 In a method for preparing a semiconductor structure provided in an embodiment Figure 4A schematic diagram of the 3D structure of the structure obtained after the structure in is filled with the first filling layer and forms a framework structure;

[0051] Figure 6 A schematic diagram of a 3D structure of a structure obtained in step S203 in a method for preparing a semiconductor structure provided in an embodiment;

[0052] Figure 7 In a method for preparing a semiconductor structure provided in an embodiment Figure 6 Schematic diagram of the 3D structure of the structure obtained after removing the first filling layer from the structure;

[0053] Figure 8 A schematic diagram of a 3D structure of a structure obtained in step S204 in a method for preparing a semiconductor structure provided in an embodiment;

[0054] Fig. 9 A schematic diagram of a 3D structure of a structure obtained in step S205 in a method for preparing a semiconductor structure provided in an embodiment;

[0055] Fig.10 In a method for preparing a semiconductor structure provided in an embodiment Fig. 9 Schematic diagram of the 3D structure of the structure obtained after the structure in is filled with the third filling layer;

[0056] Fig.11 A schematic diagram of a 3D structure of a structure obtained in step S2052 in a method for preparing a semiconductor structure provided in an embodiment;

[0057] Fig.12 is a flowchart of step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0058] Fig.13 A schematic diagram of a 3D structure of a structure obtained in step S301 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure of the structure along the AA' direction;

[0060] Fig.15 A schematic diagram of a cross-sectional structure of a structure obtained in step S302 in a method for preparing a semiconductor structure provided in an embodiment;

[0061] Fig.16 is a flowchart of step S303 in a method for preparing a semiconductor structure provided in an embodiment;

[0062] Fig.17 A schematic diagram of a 3D structure of a structure obtained in step S3031 in a method for preparing a semiconductor structure provided in an embodiment;

[0063] Fig.18 A schematic diagram of a 3D structure of a structure obtained in step S3032 in a method for preparing a semiconductor structure provided in an embodiment;

[0064] Fig.19 A schematic diagram of a 3D structure of a structure obtained in step S40 in a method for preparing a semiconductor structure provided in an embodiment;

[0065] Fig. 20 for Fig.19 Schematic diagram of the cross-sectional structure of the structure along the AA' direction;

[0066] Fig.21 is a flowchart of step S50 in a method for preparing a semiconductor structure provided in an embodiment;

[0067] Fig. 22 A schematic diagram of a 3D structure of a structure obtained in step S501 in a method for preparing a semiconductor structure provided in an embodiment;

[0068] Fig.23 is a flowchart of step S501 in a method for preparing a semiconductor structure provided in an embodiment;

[0069] Fig.24 A schematic diagram of a cross-sectional structure of a structure obtained in step S502 in a method for preparing a semiconductor structure provided in an embodiment;

[0070] Fig.25 Schematic diagram of the cross-sectional structure of the structure obtained in step S60 in the method for preparing a semiconductor structure provided in one embodiment.

[0071] Explanation of the accompanying drawings: 1-substrate, 20-initial stacking structure, 21-stacking structure, 201-first dielectric layer, 2011-initial main body, 2012-initial extension part, 202-second dielectric layer, 203-conductive layer, 2031-main body, 2032-extension part, 31-first filling layer, 41-frame structure, 42-second filling layer, 43-insulating layer, 431-insulating material layer, 32-third filling layer, 501-capacitor dielectric layer, 502-second electrode, 601-first trench, 602-second trench, 603-third trench, 701-channel layer, 7011-channel material layer, 702-isolation layer, 703-gate conductive layer. DETAILED DESCRIPTION

[0072] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0074] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0075] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0076] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0078] See also Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0079] S10: providing a substrate;

[0080] S20: forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked sequentially from bottom to top;

[0081] S30: forming an insulating layer corresponding to the side surface of each first dielectric layer;

[0082] S40: depositing a channel material layer, an isolation layer and a gate conductive layer in sequence on the side surfaces of each conductive layer and the surface of the insulating layer;

[0083] S50: removing each insulating layer to expose each channel material layer corresponding to each first dielectric layer;

[0084] S60: removing the exposed channel material layers to obtain channel layers located on the sides of the conductive layers.

[0085] The method for preparing the semiconductor structure is as follows: a stacked structure is formed on a substrate, wherein the stacked structure includes a first dielectric layer and a conductive layer stacked sequentially from bottom to top; an insulating layer is formed corresponding to the side of each first dielectric layer; a channel material layer, an isolation layer and a gate conductive layer are sequentially deposited on the side of each conductive layer and the surface of the insulating layer; each insulating layer is removed to expose each channel material layer corresponding to each first dielectric layer; each exposed channel material layer is removed to obtain a channel layer located on the side of each conductive layer. Since each channel material layer corresponding to each conductive layer will not be exposed, and each channel material layer covering the side of each first dielectric layer will be completely exposed, the etching contact area of ​​the channel material layer can be increased by removing the channel material layer by an etching process at this time, so that the channel material layer corresponding to each first dielectric layer can be quickly removed to quickly remove the parasitic transistor, and the channel layer on the side of each conductive layer can be retained without being damaged, thereby improving the device performance, ensuring the normal operation of the device and reducing the leakage current. In addition, the preparation method can also reduce process difficulty, improve process accuracy, and simplify the process flow.

[0086] In step S20, refer to Figure 1 Step S10 in Fig. 9 , a stacked structure 21 is formed on the substrate 1, and the stacked structure 21 includes a first dielectric layer 201 and a conductive layer 203 stacked in sequence from bottom to top.

[0087] Among them, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0088] The first dielectric layer 201 may include an oxide material or a nitride material, such as silicon oxide or silicon nitride. The material of the conductive layer 203 may include a metal material, such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta) or other suitable metals.

[0089] In some embodiments, Figure 2 As shown, the above step S20 includes:

[0090] S201: forming an initial stacked structure 20 on a substrate 1, wherein the initial stacked structure 20 comprises a first dielectric layer 201 and a second dielectric layer 202 stacked sequentially from bottom to top, such as Figure 3 shown.

[0091] The first dielectric layer 201 and the second dielectric layer 202 may be deposited alternately on the substrate 1 by a deposition process to obtain an initial stacked structure 20. The material of the second dielectric layer 202 may include a nitride material. The material of the second dielectric layer 202 is different from that of the first dielectric layer 201. For example, the material of the second dielectric layer 202 may be silicon nitride (Si 3 N 4 ), and the material of the first dielectric layer 201 can be silicon oxide (SiO 2 ), or, the first dielectric layer 201 and the second dielectric layer 202 may also be other suitable material combinations, which is not limited in this embodiment.

[0092] S202: Patterning the initial stacked structure 20, so that each first dielectric layer 201 includes: an initial main body portion 2011 extending along a first direction and a plurality of initial extension portions 2012 arranged at intervals along the first direction, each initial extension portion 2012 is located on two opposite sides of the initial main body portion 2011, the initial main body portion 2011 is integrally connected with each initial extension portion 2012, and the end portion where the initial extension portion 2012 is connected to the initial main body portion 2011 is used as a preset channel region, such as Figure 4 shown.

[0093] The first direction can be as follows: Figure 4 The second direction is parallel to the column extension direction of the substrate 1, and can be as follows Figure 4 The first direction and the second direction may be perpendicular to each other as shown in the row extension direction parallel to the substrate 1. Of course, the first direction, the second direction, and the direction perpendicular to the substrate 1 are only for the convenience of explaining the structure of the present solution, and do not constitute any limitation on the present solution. Moreover, in other suitable application scenarios, the first direction, the second direction, and the direction perpendicular to the substrate 1 may also be other suitable directions, as long as the solution of the present invention is reasonable, and this embodiment does not limit it here.

[0094] The initial stacked structure 20 may be patterned by using a process combining photolithography and etching.

[0095] Optional, such as Figure 5As shown, after the initial stacked structure 20 is patterned, the first filling layer 31 may be used to fill the gap area of ​​the patterned initial stacked structure 20, and then the etching process may be used to remove the parts located on both sides of the initial stacked structure 20, and then the deposition process may be used to form the frame structure 41 on both sides of the initial stacked structure 20. The material of the frame structure 41 may include a nitride material.

[0096] S203: etching to form a first filling trench penetrating through the preset channel regions of each layer, and forming a second filling layer 42 in the first filling trench, such as Figure 6 shown.

[0097] The material of the second filling layer 42 may include polysilicon. The second filling layer 42 extends in a direction perpendicular to the substrate 1 to connect the first dielectric layers 201 and define the positions of subsequent channel regions.

[0098] Optionally, after forming the second filling layer 42, a step of removing the first filling layer 31 may be performed to form a Figure 7 The structure shown.

[0099] S204: removing each second dielectric layer 202 in the initial stacked structure 20, such as Figure 8 shown.

[0100] The etching process can be used to selectively remove each second dielectric layer 202 to retain each first dielectric layer 201 . During the selective etching process, each first dielectric layer 201 can maintain its original morphology due to the support of the second filling layer 42 .

[0101] S205: Forming each conductive layer 203 between each first dielectric layer 201 to obtain a stacked structure 21. The stacked structure 21 includes the first dielectric layer 201 and the conductive layer 203 stacked sequentially from bottom to top. Fig. 9 shown.

[0102] In some embodiments, Fig. 9 As shown, each conductive layer 203 includes: a main body 2031 extending along a first direction and a plurality of extension portions 2032 arranged at intervals along the first direction, each extension portion 2032 is located on two opposite sides of the main body 2031, the main body 2031 is integrally connected with each extension portion 2032, and the end portion where the extension portion 2032 is connected to the main body 2031 serves as a channel region.

[0103] In some embodiments, after step S20 and before step S30, the method for preparing the semiconductor structure further includes: depositing a third dielectric layer 32, wherein the third dielectric layer 32 fills the gaps in the stacked structure 21. Fig.10In addition, in some embodiments, the material of the third dielectric layer 32 may be the same as that of the first dielectric layer 201, so in some embodiments, the following may be obtained: Fig.11 The structure shown.

[0104] Based on the above embodiments, in some embodiments, the portion of the extension portion 2032 away from the main body portion 2031 is used as the first electrode, and after the third dielectric layer 32 is deposited, the method for preparing the semiconductor structure further includes:

[0105] S2051: removing the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode. During the removal process, the second dielectric layer 202 may be removed together.

[0106] S2052: forming a capacitor dielectric layer 501 and a second electrode 502 in sequence on the exposed surface of the first electrode, such as Fig.11 shown.

[0107] The capacitor dielectric layer 501 and the second electrode 502 can be deposited in sequence on the exposed surface of the first electrode by a deposition process, and then the surface of the obtained structure can be smoothed by a mechanical grinding process to obtain a structure as shown in FIG. Fig.11 The structure shown.

[0108] The material of the first electrode may include a metal material, such as copper, gold, titanium, silver, aluminum, tungsten and the like. The material of the capacitor dielectric layer 501 may include an HK dielectric material. The material of the second electrode 502 may include a conductive material, and the second electrode 502 may further include a conductive barrier layer and an electrode conductive layer 203, wherein the conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof; the material of the electrode conductive layer 203 may include polysilicon.

[0109] In step S30, refer to Figure 1 Step S30 in Fig.18 , an insulating layer 43 is formed correspondingly on the side surface of each first dielectric layer 201 .

[0110] In some embodiments, Fig.12 As shown, the above step S30 includes:

[0111] S301: etching to form a first trench 601 penetrating the channel regions of each layer, the sidewall of the first trench 601 exposing the side surfaces of the dielectric layers and the side surfaces of the conductive layer 203 alternately stacked in sequence, such as Figure 13-14 shown.

[0112] The second filling layer 42 may be directly removed by an etching process, and the trench obtained after the removal is the first trench 601 .

[0113] S302: Based on the first trench 601, each layer of the first dielectric layer 201 is laterally etched to form a second trench 602 between each layer of the conductive layer 203. The bottom size of the second trench 602 is smaller than the opening size of the second trench 602. Fig.15 shown.

[0114] A wet etching process can be used to laterally etch each first dielectric layer 201 based on the first groove 601. By controlling the etching parameters of the wet etching process and utilizing the isotropy of the wet etching, the second grooves 602 formed in each first dielectric layer 201 after etching do not present a relatively regular morphology, but present a morphology as shown in FIG. Fig.15 The morphology shown is similar to a bowl placed laterally.

[0115] S303: forming an insulating layer 43 at the bottom of each layer of the second trench 602, so that each layer of the insulating layer 43 covers the side surface of each layer of the first dielectric layer 201. Fig.18 shown.

[0116] In one embodiment, Fig.16 As shown, the above step S303 includes:

[0117] S3031: forming a continuously distributed insulating material layer 431 on the inner wall of the first trench 601 and the inner wall of the second trench 602, wherein the thickness of the insulating material layer 431 at the bottom of the second trench 602 is greater than the thickness of the insulating material layer 431 at the side wall of the second trench 602, such as Fig.17 shown.

[0118] The material of the insulating material layer 431 may include aluminum oxide. The insulating material layer 431 may be formed by a deposition process. Since the space at the bottom of the second trench 602 is narrow and the sidewall of the second trench 602 is relatively flat, the insulating material layer 431 will first be closed at the bottom of the second trench 602, so that the thickness of the insulating material layer 431 at the bottom of the second trench 602 is greater than the thickness of the insulating material layer 431 at the sidewall of the second trench 602. In addition, during the deposition process, the aluminum oxide in the second trench 602 may have a certain gap.

[0119] S3032: removing the insulating material layer 431 located on the inner wall of the first trench 601 and a portion of the insulating material layer 431 located on the side wall of the second trench 602 to obtain the insulating layer 43 retained at the bottom of the second trench 602, such as Fig.18 shown.

[0120] In one embodiment, the step S3032 includes: removing the insulating material layer 431 located on the inner wall of the first trench 601 and a portion of the insulating material layer 431 located on the side wall of the second trench 602 by using a wet etching process.

[0121] During the removal process, since the insulating material layer 431 at the bottom of the second trench 602 is relatively thick, the insulating material layer 431 at the bottom of the second trench 602 can be ensured to have a certain amount of residue by controlling the appropriate etching parameters such as etching time, thereby forming a Fig.18 The insulating layer 43 shown. Fig.18 It can be seen that after step S3032, the side surfaces of each first dielectric layer 201 will be covered by the insulating layer 43 (the insulating layer 43 here is the insulating layer 43 remaining at the bottom of the second trench 602), and the side surfaces of each conductive layer 203 will be exposed again.

[0122] In step S40, refer to Figure 1 Step S40 in Figure 19-20 , a channel material layer 7011 , an isolation layer 702 and a gate conductive layer 703 are sequentially deposited on the side surfaces of each conductive layer 203 and the surface of the insulating layer 43 .

[0123] A deposition process may be used to sequentially deposit a channel material layer 7011, an isolation layer 702, and a gate conductive layer 703 in the first trench 601 to form a Figure 19-20 The structure shown.

[0124] The material of the channel material layer 7011 may include a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment may be made according to the actual situation. The material of the isolation layer 702 may include HK dielectric material. The material of the gate conductive layer 703 may include indium tin oxide (ITO) or indium oxide-zinc oxide (IZO).

[0125] In step S50, refer to Figure 1 Step S50 in Fig.24 , each insulating layer 43 is removed to expose each channel material layer 7011 corresponding to each first dielectric layer 201 .

[0126] In one embodiment, Fig.21 As shown, the above step S50 includes:

[0127] S501: forming a third trench 603 penetrating the third dielectric layer between adjacent channel regions, so that the sidewalls of the third trench 603 expose the surface of each insulating layer 43, such as Fig. 22 shown.

[0128] In one embodiment, the insulating layer 43 includes an aluminum oxide layer, such as Fig.23 As shown, the above step S501 includes:

[0129] S5011: A third trench 603 penetrating the third dielectric layer is formed between adjacent channel regions by dry etching. At this time, the inner sidewall of the third trench 603 may be a continuously distributed third dielectric layer, and the aluminum oxide layer is not exposed yet.

[0130] S5012: using an acid solution to etch and remove a portion of the third dielectric layer on the inner wall of the third trench 603 to expose the surfaces of each aluminum oxide layer.

[0131] A small amount of acid solution is used to remove part of the third dielectric layer to ensure that the surface of each aluminum oxide layer is exposed. At this time, the position of each aluminum oxide layer exposed in the third groove 603 corresponds to the position of each first dielectric layer 201.

[0132] S502: removing each insulating layer 43 based on the third trench 603 to expose each channel material layer 7011 corresponding to each first dielectric layer 201, such as Fig.24 shown.

[0133] In one embodiment, the channel material layer 7011 includes an aluminum oxide layer, and the step S502 includes: removing each layer of the aluminum oxide layer based on the third trench 603 by etching with an alkaline solution.

[0134] In step S60, refer to Figure 1 Step S60 in Fig.25 , removing the exposed channel material layers 7011 to obtain the channel layers 701 located on the sides of the conductive layers 203 .

[0135] After removing each insulating layer 43, each channel material layer 7011 corresponding to each conductive layer 203 will not be exposed, while each channel material layer 7011 covering the side of each first dielectric layer 201 will be completely exposed. At this time, the channel material layer 7011 is removed by etching to increase the etching contact area of ​​the channel material layer 7011, so that the channel material layer 7011 corresponding to each first dielectric layer 201 can be quickly removed to quickly remove the parasitic transistor. The channel layer 701 on the side of each conductive layer 203 can be retained without being damaged, such as Fig.25 shown.

[0136] In some embodiments, after the above step S502 , the method further includes: filling the third trench 603 with a fourth filling layer.

[0137] The present invention also provides a semiconductor structure, such as Fig.25As shown, the semiconductor structure includes: a substrate 1; a stacked structure 21, located on the substrate 1, the stacked structure 21 includes a first dielectric layer 201 and a conductive layer 203 stacked in sequence from bottom to top, each conductive layer 203 includes: a main body 2031 extending along a first direction and a plurality of extensions 2032 arranged at intervals along the first direction, each extension 2032 is located on two opposite sides of the main body 2031, the main body 2031 is integrally connected with each extension 2032, and the end portion where the extension 2032 is connected to the main body 2031 serves as a channel region; a gate conductive layer 703, penetrating each channel region and extending in a direction perpendicular to the substrate 1; an isolation layer 702, surrounding the side wall of the gate conductive layer 703; a plurality of channel layers 701, surrounding the side wall of the isolation layer 702, and arranged at intervals in a direction perpendicular to the substrate 1, each channel layer 701 is in one-to-one contact with each conductive layer 203.

[0138] Among them, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0139] The first dielectric layer 201 may include an oxide material or a nitride material, such as silicon oxide or silicon nitride. The material of the conductive layer 203 may include a metal material, such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta) or other suitable metals. The material of the channel material layer 7011 may include a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation. The material of the isolation layer 702 may include HK dielectric material. The material of the gate conductive layer 703 may include ITO or IZO.

[0140] Since the channel material layers 7011 corresponding to the conductive layers 203 in the semiconductor structure will not be exposed, and the channel material layers 7011 covering the sides of the first dielectric layers 201 will be completely exposed, the etching process is used to remove the channel material layers 7011, which can increase the etching contact area of ​​the channel material layers 7011, so that the channel material layers 7011 corresponding to the first dielectric layers 201 can be quickly removed to quickly remove the parasitic transistors. The channel layers 701 on the sides of the conductive layers 203 can be retained without being damaged, so that the normal reading and writing of the device can be guaranteed and the leakage current can be reduced.

[0141] The semiconductor structure comprises: a substrate 1; a stacked structure 21 located on the substrate 1, the stacked structure 21 comprises a first dielectric layer 201 and a conductive layer 203 stacked in sequence from bottom to top, each conductive layer 203 comprises: a main body 2031 extending along a first direction and a plurality of extensions 2032 arranged at intervals along the first direction, each extension 2032 is located on two opposite sides of the main body 2031, the main body 2031 is integrally connected with each extension 2032, and the end portion where the extension 2032 is connected to the main body 2031 serves as a channel region; a gate conductive layer 703 penetrating each channel region and extending in a direction perpendicular to the substrate 1; an isolation layer 702 surrounding the side wall of the gate conductive layer 703; a plurality of channel layers 701 surrounding the side wall of the isolation layer 702 and arranged at intervals in a direction perpendicular to the substrate 1, each channel layer 701 is in one-to-one contact with each conductive layer 203. Since the channel material layers 7011 corresponding to the first dielectric layers 201 can be removed quickly to quickly remove the parasitic transistors, the channel layers 701 on the sides of the conductive layers 203 can be retained without being damaged, thus ensuring normal reading and writing of the device and reducing leakage current.

[0142] In one embodiment, Fig.25 As shown, the semiconductor structure also includes a capacitor, which includes a first electrode and a capacitor dielectric layer 501 and a second electrode 502 that sequentially cover the surface of the first electrode. The portion of the extension 2032 away from the main body 2031 serves as the first electrode of the capacitor.

[0143] The material of the first electrode may include a metal material, such as copper, gold, titanium, silver, aluminum, tungsten and the like. The material of the capacitor dielectric layer 501 may include an HK dielectric material. The material of the second electrode 502 may include a conductive material, and the second electrode 502 may further include a conductive barrier layer and an electrode conductive layer 203, wherein the conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof; the material of the electrode conductive layer 203 may include polysilicon.

[0144] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked sequentially from bottom to top; forming an insulating layer corresponding to the side surface of each layer of the first dielectric layer; Depositing a channel material layer, an isolation layer and a gate conductive layer in sequence on the side surfaces of each conductive layer and the surface of the insulating layer; Removing each insulating layer to expose each channel material layer corresponding to each first dielectric layer; The exposed channel material layers are removed to obtain channel layers located on the sides of the conductive layers.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and the ends of the extensions connected to the main body are used as channel regions, and an insulating layer is formed correspondingly on the side of each dielectric layer, including: Etching to form a first trench penetrating the channel region of each layer, wherein the sidewall of the first trench exposes the side surface of the first dielectric layer and the side surface of the conductive layer which are alternately stacked in sequence; Based on the first grooves, each layer of the first dielectric layer is laterally etched to form a second groove between each layer of the conductive layer, wherein the bottom size of the second groove is smaller than the opening size of the second groove; An insulating layer is formed at the bottom of each layer of the second trench, so that each layer of the insulating layer covers the side surface of each layer of the first dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step of forming an insulating layer at the bottom of each layer of the second trench so that each layer of the insulating layer covers the side surface of each layer of the first dielectric layer comprises: forming a continuously distributed insulating material layer on the inner wall of the first trench and the inner wall of the second trench, wherein the thickness of the insulating material layer at the bottom of the second trench is greater than the thickness of the insulating material layer at the sidewall of the second trench; The insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench are removed to obtain an insulating layer retained at the bottom of the second trench.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The removing of the insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench comprises: The insulating material layer located on the inner wall of the first trench and a portion of the insulating material layer located on the side wall of the second trench are removed by a wet etching process.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: After forming a stacked structure on the substrate and before forming an insulating layer on the side surface of each layer of the first dielectric layer, the method further includes: A third dielectric layer is deposited, wherein the third dielectric layer fills the gaps in the stacked structure.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The portion of the extension portion away from the main portion is used as a first electrode, and after depositing the third dielectric layer, the method further includes: removing the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode; A capacitor dielectric layer and a second electrode are sequentially formed on the exposed surface of the first electrode.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The removing of each insulating layer to expose each channel material layer corresponding to each first dielectric layer includes: forming a third trench penetrating the third dielectric layer between adjacent channel regions, so that the sidewalls of the third trench expose the surfaces of each insulating layer; The insulating layers are removed based on the third trenches to expose the channel material layers corresponding to the first dielectric layers.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The insulating layer is an aluminum oxide layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step of forming a third trench penetrating the third dielectric layer between adjacent channel regions so that the sidewalls of the third trench expose the surfaces of each insulating layer, comprises: Using a dry etching process to form a third trench penetrating the third dielectric layer between adjacent channel regions; Acidic solution is used to etch and remove a portion of the third dielectric layer on the inner wall of the third trench to expose the surface of each aluminum oxide layer.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The removing of each layer of the insulating layer based on the third trench comprises: The aluminum oxide layers are removed based on the third groove by etching with an alkaline solution.

11. The method for preparing a semiconductor structure according to claim 7, characterized in that: After removing the exposed channel material layers to obtain the channel layers located on the sides of the conductive layers, the method further includes: The third trench is filled with a fourth filling layer.

12. A semiconductor structure, characterized in that: include: substrate; A stacked structure is located on the substrate, the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and the ends of the extensions connected to the main body serve as channel regions; A gate conductive layer, penetrating through the channel regions of each layer and extending in a direction perpendicular to the substrate; an isolation layer surrounding a side wall of the gate conductive layer; The multi-layer channel layers surround the sidewalls of the isolation layer and are arranged at intervals in a direction perpendicular to the substrate, and each layer of the channel layers is in one-to-one contact with each layer of the conductive layer.

13. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure further includes a capacitor, which includes a first electrode, a capacitor dielectric layer and a second electrode sequentially covering the surface of the first electrode, and a portion of the extension away from the main body serves as the first electrode of the capacitor.

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