Memory and integrated circuit

Abstract

A memory and an integrated circuit. The memory includes a memory cell structure including a write transistor and a read transistor each including a gate, an active layer, a first pole, and a second pole; a grid electrode of the write transistor is configured to receive a scanning signal, a first pole of the write transistor is connected with a grid electrode of the read transistor and serves as a storage node, a second pole of the write transistor is configured to receive a write signal, and a first pole of the read transistor is configured to receive a first read signal; the first electrode of the read-out transistor is configured to receive a first read-out signal, the second electrode of the read-out transistor is configured to receive a second read-out signal, the write-in transistor is an N-type transistor, the read-out transistor is a P-type transistor, and the carrier mobility of the active layer of the read-out transistor is higher than that of the active layer of the write-in transistor. Therefore, the memory can enhance the data integrity of the storage node, and has stable and read time and faster read speed while having higher data retention time.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory and an integrated circuit. Background Art

[0002] From the von Neumann architecture to the more advanced modern architecture, memory plays an increasingly important role. Because the capacitor part of the preparation process of large-capacity memory (for example, DRAM) usually needs to use MIM (Metal-Insulator-Metal) technology, which requires a higher formation temperature and is difficult to match with the most advanced process, large-capacity memory is integrated with computing modules such as CPU, and the connection between the two requires long-distance communication, which cannot provide fast reading and writing.

[0003] On the other hand, 2T0C memory, also known as capacitorless memory, is a new type of memory. Its original design concept is to use advanced silicon technology to prepare high-speed and high-density embedded on-chip storage, which can meet the requirements of hardware systems in terms of speed, density and energy consumption. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory and an integrated circuit. The memory can improve the anti-coupling and anti-interference capabilities, reduce charge coupling, and thus enhance the data integrity of the storage node; and the memory can also have a stable and read time and a faster read speed while having a higher data retention time. At the same time, the memory can also be integrated into an integrated circuit using a back-end process, thereby improving the data transmission bandwidth and improving the performance of the integrated circuit using the memory. The memory in the integrated circuit has higher data integrity and higher read speed, and also has a higher data transmission bandwidth, thereby having higher performance.

[0005] At least one embodiment of the present disclosure provides a memory, which includes a memory cell structure, wherein the memory cell structure includes a write transistor and a read transistor, and the write transistor and the read transistor each include a gate, an active layer, a first electrode, and a second electrode; the gate of the write transistor is configured to receive a scan signal, the first electrode of the write transistor is connected to the gate of the read transistor and serves as a storage node, the second electrode of the write transistor is configured to receive a write signal, the first electrode of the read transistor is configured to receive a first read signal, and the second electrode of the read transistor is configured to receive a second read signal; the write transistor is an N-type transistor, the read transistor is a P-type transistor, and the carrier mobility of the active layer of the read transistor is higher than the carrier mobility of the active layer of the write transistor.

[0006] For example, in the memory provided in one embodiment of the present disclosure, the active layer of the write transistor includes one of an N-type two-dimensional semiconductor material and an N-type oxide semiconductor material, and the active layer of the read transistor includes one of a P-type two-dimensional semiconductor material and a P-type oxide semiconductor material.

[0007] For example, in a memory provided by an embodiment of the present disclosure, the P-type two-dimensional semiconductor material includes carbon nanotubes or tungsten selenide.

[0008] For example, in the memory provided by an embodiment of the present disclosure, the active layer of the write transistor includes an N-type oxide semiconductor material, and the active layer of the read transistor includes carbon nanotubes.

[0009] For example, in the memory provided by an embodiment of the present disclosure, the memory cell structure is composed of the write transistor and the read transistor.

[0010] For example, the memory provided by one embodiment of the present disclosure also includes: a write tube word line, connected to the gate of the write transistor; a write tube bit line, connected to the second electrode of the write transistor; a read tube word line, connected to the first electrode of the read transistor; and a read tube bit line, connected to the second electrode of the read transistor.

[0011] For example, in the memory provided by an embodiment of the present disclosure, the write transistor and the read transistor are manufactured using a back-end process.

[0012] For example, in the memory provided by an embodiment of the present disclosure, the formation temperature of the active layer of the write transistor and the active layer of the read transistor is less than 300 degrees Celsius.

[0013] For example, in a memory provided by an embodiment of the present disclosure, the active layer of the write transistor extends along a first direction, and the active layer of the read transistor extends along a second direction, and the first direction and the second direction are perpendicular to each other.

[0014] At least one embodiment of the present disclosure also provides an integrated circuit, comprising: a semiconductor substrate including a logic control circuit; a first passivation layer located on the semiconductor substrate; and a cache located on a side of the first passivation layer away from the semiconductor substrate, the cache comprising any of the memories described above.

[0015] For example, an integrated circuit provided by an embodiment of the present disclosure further includes: an internal memory located on a side of the first passivation layer away from the semiconductor substrate.

[0016] For example, in an integrated circuit provided in an embodiment of the present disclosure, the internal memory includes at least one of a phase change memory and a resistive change memory.

[0017] For example, an integrated circuit provided by an embodiment of the present disclosure further includes: a second passivation layer located on a side of the internal memory away from the semiconductor substrate, and the cache is located on a surface of the second passivation layer away from the internal memory.

[0018] For example, in an integrated circuit provided in an embodiment of the present disclosure, the semiconductor substrate includes a silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0020] Figure 1 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of improving the anti-coupling and anti-interference capabilities of a memory provided by an embodiment of the present disclosure;

[0023] Figure 4 A memory device provided by an embodiment of the present disclosure Figure 2 Schematic diagram of the cross section along the AB direction;

[0024] Figure 5 A memory device provided by an embodiment of the present disclosure Figure 2 Schematic diagram of the cross section in the CD direction;

[0025] Figures 6A-6I A schematic diagram of steps of a method for manufacturing a memory provided by an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of an integrated circuit provided for an embodiment of the present disclosure; and

[0027] Figure 8 A schematic diagram of another integrated circuit provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0030] The usual 2T0C memory is composed of two N-type transistors, excluding the capacitor part. Compared with static random access memory (SRAM), 2T0C memory has the advantages of high density, large capacity, and low leakage consumption; compared with dynamic random access memory (DRAM), 2T0C memory can achieve non-destructive reading and higher speed reading and writing.

[0031] Since the turn-off current of silicon transistors is large and leakage is serious, the retention time is very short; if 2T0C memory uses silicon transistors, its data effective retention time does not exceed 1ms, which is difficult to reach the industry standard of 64ms. In this case, three or four transistors must be used to implement internal feedback or dual switch designs to meet the above standards, and occupy additional area. In addition, due to the further miniaturization of technology nodes, the leakage effect is significantly deteriorated, resulting in the device being unable to realize storage functions.

[0032] The common 2T0C memory uses two N-type transistors. Since N-type semiconductor materials have certain requirements for the voltage setting of the system, it will cause instability. When both the write transistor and the read transistor are N-type transistors, "1" is stored as a high potential at the storage node, and the drive current passes through the read transistor; however, since the voltage of the storage node will drop over time, the drive current will inevitably change greatly, making the time required for reading unstable.

[0033] On the other hand, with the continuous advancement of integrated circuit manufacturing process nodes, the integration scale, computing performance and speed have been greatly improved. Therefore, the demand for data transmission bandwidth required by integrated circuits has increased rapidly, resulting in the factors limiting the performance of integrated circuits gradually shifting from the processing speed of the integrated circuit itself to the interconnection line density and delay outside the integrated circuit.

[0034] In this regard, the embodiment of the present disclosure provides a memory, which includes a storage unit structure, including a write transistor and a read transistor, each of which includes a gate, an active layer, a first electrode, and a second electrode; the gate of the write transistor is configured to receive a scan signal, the first electrode of the write transistor is connected to the gate of the read transistor and serves as a storage node, the second electrode of the write transistor is configured to receive a write signal, the first electrode of the read transistor is configured to receive a first read signal, the second electrode of the read transistor is configured to receive a second read signal, the write transistor is an N-type transistor, the read transistor is a P-type transistor, and the carrier mobility of the active layer of the read transistor is higher than the carrier mobility of the active layer of the write transistor. Thus, the memory can improve the anti-coupling and anti-interference capabilities, reduce charge coupling, and thus enhance the data integrity of the storage node; and the memory can also have a stable and read time and a faster read speed while having a higher data retention time. At the same time, the memory can also be integrated into an integrated circuit using a back-end process, thereby improving the data transmission bandwidth and improving the performance of the integrated circuit using the memory.

[0035] The embodiment of the present disclosure also provides an integrated circuit, which includes the above-mentioned memory. Therefore, the memory in the integrated circuit has higher data integrity and higher reading speed, and also has higher data transmission bandwidth, so as to have higher performance.

[0036] The memory and integrated circuit provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0037] Figure 1 A schematic diagram of a memory provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure. Figure 1 and Figure 2As shown, the memory 200 includes a memory cell structure 100; the memory cell structure 100 includes a write transistor 110 and a read transistor 120; the write transistor 110 and the read transistor 120 each include a gate, an active layer, a first electrode and a second electrode, for example, the write transistor 110 includes a gate 110G, an active layer 110A, a first electrode 110S and a second electrode 110D, and the read transistor 120 includes a gate 120G, an active layer 120A, a first electrode 120S and a second electrode 120D; the gate 110G of the write transistor 110 is configured to receive a scan signal, and the write transistor The first electrode 110S of 110 is connected to the gate 120G of the read-out transistor 120 and serves as a storage node SN; the second electrode 110D of the write transistor 110 is configured to receive a write signal, the first electrode 120S of the read-out transistor 120 is configured to receive a first read-out signal, the second electrode 120D of the read-out transistor 120 is configured to receive a second read-out signal, the write transistor 110 is an N-type transistor, the read-out transistor 120 is a P-type transistor, and the carrier mobility of the active layer 110A of the read-out transistor 110 is higher than the carrier mobility of the active layer 120A of the write transistor 120.

[0038] In the memory provided in the embodiment of the present disclosure, when data needs to be written in the storage cell structure 100, the data is loaded into the second electrode 110D of the write transistor 110 in the form of voltage, and at the same time, the high voltage in the scan signal turns on the N-type write transistor 110, and the voltage at the storage node SN is pulled down or pulled up. When the storage cell structure 100 does not need to write data, the scan signal is grounded or set to a low voltage or a negative voltage, so that the write transistor 100 is turned off and the data at the storage node SN is maintained. When the data of the storage node SN does not need to be read out, the P-type readout transistor 120 is in a closed state; when the data of the storage node SN needs to be read out, the first readout signal is a high voltage, and the second readout signal is a low voltage. If the value of the storage node SN is "0", the readout transistor 120 has a conduction current, otherwise there is no current, thereby realizing the storage function.

[0039] Figure 3 A schematic diagram of a memory device for improving the anti-coupling and anti-interference capabilities provided by an embodiment of the present disclosure. Figure 3 As shown, in an actual product, there is a first parasitic capacitor C1 between the storage node SN and the gate 110G of the N-type write transistor 110, and there is a second parasitic capacitor C2 between the storage node SN and the first electrode 110S of the read transistor 120. Therefore, after the scan signal in the gate 110G of the write transistor 110 turns on the write transistor 110, the falling edge of the pulse signal of the scan signal will pull down the potential on the storage node SN through the action of the first parasitic capacitor C1, thereby reducing the data integrity on the storage node SN.

[0040] Similarly, when the first pole 110S of the read transistor 120 is loaded with the first read signal, the first read signal will also affect the potential on the storage node SN through the second parasitic capacitor C2. The conventional 2T0C memory uses two N-type transistors, so the first read signal with a lower voltage will further reduce the potential on the storage node SN through the second parasitic capacitor C2, thereby further reducing the data integrity on the storage node SN. However, the write transistor of the memory provided in the embodiment of the present disclosure is an N-type transistor, and the read transistor is a P-type transistor. Therefore, the first read signal with a higher voltage will pull up the potential on the storage node SN through the parasitic capacitor C2, and compensate the potential on the storage node SN to a certain extent, thereby enhancing the data integrity on the storage node SN. It should be noted that when 2T0C uses P-type transistors, similar problems will also be encountered. The first parasitic capacitor and the second parasitic capacitor have the same effect on the potential on the storage node SN, that is, they are pulled up or reduced at the same time; in addition, although there is also a parasitic capacitor between the storage node and the second pole of the read transistor, the voltage on the second pole is usually stable, and will not adversely affect the potential on the storage node.

[0041] Therefore, the memory provided by the embodiment of the present disclosure can improve the ability of anti-coupling and anti-interference, reduce the amount of charge coupled to the storage node, and thus enhance the data integrity of the storage node. In addition, since the write transistor is an N-type transistor and the read transistor is a P-type transistor, while the write transistor uses a transistor with a lower leakage current, different types of read transistors can be used to make the carrier mobility of the active layer of the read transistor higher than the carrier mobility of the active layer of the write transistor, so the memory can also have a higher data retention time while having a stable and read time and a faster reading speed. It should be noted that the conventional 2T0C memory uses two N-type transistors, which use the same material to make the active layer, and therefore have similar performance; since the write transistor requires a lower leakage current, the carrier mobility of the N-type transistor with a lower leakage current is usually also lower, which will affect the reading speed.

[0042] At the same time, since the write transistor is an N-type transistor and the read transistor is a P-type transistor, the memory can also use an oxide transistor as a write transistor and a two-dimensional semiconductor material transistor as a read transistor, both of which do not require high-temperature processes, so they can be integrated into integrated circuits using back-end processes, thereby increasing data transmission bandwidth and improving the performance of integrated circuits using the memory.

[0043] In some examples, the first electrode is a source and the second electrode is a drain; or, the first electrode is a drain and the second electrode is a source.

[0044] In some examples, such as Figure 1 and Figure 2 As shown, the memory cell structure 100 is composed of a write transistor 110 and a read transistor 120, and does not include a capacitor; that is, the memory cell structure 100 is a 2T0C structure. Therefore, the memory can achieve high density, large capacity, low leakage power consumption, non-destructive reading, and higher speed reading and writing.

[0045] In some examples, such as Figure 1 and Figure 2 As shown, the memory 200 further includes a write pipe word line 210 connected to the gate 110G of the write transistor 110; a write pipe bit line 220 connected to the second electrode 110D of the write transistor 110; a read pipe word line 230 connected to the first electrode 120S of the read-out transistor 120; and a read pipe bit line 240 connected to the second electrode 120D of the read-out transistor 120. The write pipe word line 210 is configured to apply a scan signal to the gate 110G of the write transistor 110; the write pipe bit line 220 is configured to apply a write signal to the second electrode 110D of the write transistor 110; the read pipe word line 230 is configured to apply a first read signal to the first electrode 120S of the read-out transistor 120, and the read pipe bit line 240 is configured to apply a second read signal to the second electrode 120D of the read-out transistor 120.

[0046] When data needs to be written in the memory cell structure 100, the data is loaded to the second electrode 110D of the write transistor 110 in the form of voltage through the write pipe bit line 220, and at the same time, the high voltage in the scan signal on the write pipe word line 210 turns on the N-type write transistor 110, and the voltage at the storage node SN is pulled down or pulled up to store data. When the memory cell structure 100 does not need to write data, the scan signal on the write pipe word line 210 is grounded or set to a low voltage or a negative voltage, so that the write transistor 100 is turned off and the data at the storage node SN is maintained. When it is not necessary to read the data of the storage node SN, the P-type read transistor 120 is in a closed state; when it is necessary to read the data of the storage node SN, a first read signal is applied to the first electrode 120S of the read transistor 120 through the read tube word line 230, and a second read signal is applied to the second electrode 120D of the read transistor 120 through the read tube bit line 240. The first read signal is a high voltage, and the second read signal is a low voltage. If the value of the storage node SN is "0", the read transistor 120 has an on-current, otherwise there is no current, thereby realizing the storage function.

[0047] In some examples, the memory may include multiple memory cell structures; the multiple memory cell structures may form a memory array. For another example, the multiple memory cell structures may be distributed in multiple memory layers stacked in a stack, each memory layer including a memory array formed by the memory cell structures, thereby improving the storage density.

[0048] In some examples, the active layer of the write transistor 110 includes one of an N-type two-dimensional semiconductor material and an N-type oxide semiconductor material, and the active layer of the read transistor 120 includes one of a P-type two-dimensional semiconductor material and a P-type oxide semiconductor material.

[0049] In some examples, the active layer of the write transistor 110 is an N-type oxide semiconductor material, including indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), etc., so that it has a lower leakage current and can be manufactured using a back-end process.

[0050] In some examples, the active layer of the write transistor 110 includes indium gallium zinc oxide (IGZO). Since the IGZO transistor has a relatively high carrier mobility on the basis of having a low leakage current, a longer data retention time can be achieved and the write speed can be improved. In addition, IGZO can be manufactured using a low-temperature process, such as an evaporation process or a vapor deposition process, which is technically compatible with a standard silicon process.

[0051] In some examples, the active layer of the readout transistor 120 includes a P-type two-dimensional semiconductor material, which includes carbon nanotubes or tungsten selenide. As a result, the readout transistor has a higher carrier mobility and can be manufactured using a back-end process.

[0052] In some examples, the active layer of the readout transistor 120 includes carbon nanotubes (CNTs). Since the carrier mobility of the transistor prepared using carbon nanotubes as the active layer can reach 1850 cm 2 V -1 s -1 , which is much larger than the carrier mobility of oxide transistors (usually less than 100 cm 2 V -1 s -1 ). Therefore, when the memory uses carbon nanotube transistors as readout transistors, the readout speed can be greatly improved, and faster data reading performance can be achieved while ensuring a high data retention time. In addition, since carbon nanotubes can be grown using a solution deposition method, they are technically compatible with standard silicon processes, just like oxide semiconductor processes. On the other hand, from the perspective of circuit design, the properties and even materials of carbon nanotube transistors can be optimized and adjusted according to various applications, further matching different frequency, power consumption, voltage and other requirements, making them more suitable for integration into integrated circuits.

[0053] In some examples, both the write transistor 110 and the read transistor 120 may be manufactured using a back-end process, and thus may be integrated with an integrated circuit to improve the performance of the integrated circuit.

[0054] In some examples, the active layer of write transistor 110 and the active layer of readout transistor 120 are formed at a temperature less than 300 degrees Celsius.

[0055] In some examples, such as Figure 1 and Figure 2 As shown, the active layer of the write transistor 110 extends along the first direction (i.e., the first pole and the second pole are arranged along the first direction), and the active layer of the read transistor 120 extends along the second direction (i.e., the first pole and the second pole are arranged along the second direction), and the first direction and the second direction are perpendicular to each other. Thus, the write transistor and the read transistor partially overlap each other, thereby further reducing the occupied area and improving the storage density.

[0056] Figure 4 A memory device provided by an embodiment of the present disclosure Figure 2 Schematic diagram of the cross section along the AB direction; Figure 5 A memory device provided by an embodiment of the present disclosure Figure 2 Schematic diagram of the cross section along the CD direction.

[0057] like Figure 4 and Figure 5 As shown, the memory 200 further includes a gate insulating layer 130, which is located on a side of the gate 110G of the write transistor 110 and the gate 120G of the read transistor 120 away from the substrate 101. The active layer 110A of the write transistor 110 is located on a side of the gate insulating layer 130 away from the gate 110G, and the active layer 120A of the read transistor 120 is located on a side of the gate insulating layer 130 away from the gate 120G.

[0058] like Figure 4 As shown, the gate insulating layer 130 further includes an opening 132; the memory 200 further includes a first electrode 141 and a second electrode 142, the first electrode 141 serving as a first electrode of the write transistor 110, and the second electrode 142 serving as a second electrode of the write transistor 110. The opening 132 exposes a portion of the gate 120G, the source portion of the active layer 110A of the write transistor 110 is connected to the gate 120G of the read transistor 120 through the opening 132, the first electrode 141 is electrically connected to the source portion of the active layer 110A of the write transistor 110; the second electrode 142 is connected to the drain portion of the active layer 110A of the write transistor 110.

[0059] like Figure 5As shown, the memory 200 further includes a third electrode 143 and a fourth electrode 144, wherein the third electrode 143 serves as a first electrode of the readout transistor 120, and the fourth electrode 144 serves as a second electrode of the readout transistor 110. The third electrode 143 is disposed above the source portion of the active layer 120A of the readout transistor 120, and the fourth electrode 144 is disposed above the drain portion of the active layer 120A of the readout transistor 120.

[0060] An embodiment of the present disclosure also provides a method for manufacturing a memory. Figures 6A-6I A schematic diagram of the steps of a method for manufacturing a memory provided by an embodiment of the present disclosure. Figures 6A-6I As shown, the manufacturing method includes the following steps S101-S109.

[0061] Step S101: Fig. 6A As shown, a gate 110G of a write transistor and a gate 120G of a read transistor are formed on a substrate 101 .

[0062] For example, a gate metal layer may be formed by an evaporation process, and then a gate of the write transistor and a gate of the read transistor may be formed by an etching or lift-off process.

[0063] For another example, when the memory provided by the embodiment of the present disclosure is integrated into an integrated circuit, the above-mentioned substrate may be a passivation layer in the integrated circuit.

[0064] Step S102: Figure 6B As shown, a gate insulating layer 130 is formed on the side of the gate 110G of the write transistor and the gate 120G of the read transistor away from the substrate 101 , and an opening 132 is formed in the gate insulating layer 130 to expose the gate 120G of the read transistor.

[0065] For example, the material of the gate insulating layer may be hafnium oxide (HfO 2 ). Of course, the embodiments of the present disclosure include but are not limited to this, and the material of the gate insulating layer may also be other suitable materials.

[0066] For example, an etching process may be used to form an opening 132 in the gate insulating layer 130 to expose the gate 120G of the readout transistor.

[0067] Step S103: Figure 6C As shown, carbon nanotubes 170 are deposited on the gate insulating layer 130 .

[0068] For example, the carbon nanotubes 170 may be deposited on the gate insulating layer 130 by using a solution deposition method.

[0069] Step S104: Fig.6D As shown, a first electrode 120S and a second electrode 120D of a readout transistor 120 are formed on the carbon nanotubes.

[0070] For example, metal palladium is evaporated and then the metal palladium is stripped to form the first electrode and the second electrode of the readout transistor.

[0071] Step S105: Fig. 6E As shown, a yttrium oxide (Y2O3) layer 140 is formed on the carbon nanotubes to serve as a protective layer for the carbon nanotubes 170. It should be noted that the embodiments of the present disclosure include but are not limited to the following, and other materials may also be used to make the protective layer of the carbon nanotubes.

[0072] Step S106: Fig. 6F As shown, the yttrium oxide layer and the carbon nanotubes are etched and peeled off to remove the carbon nanotubes outside the active layer of the readout transistor.

[0073] For example, the yttrium oxide layer and the carbon nanotubes may be etched and stripped off through a mask process to remove the carbon nanotubes outside the active layer of the readout transistor.

[0074] Step S107: Figure 6G As shown, an oxide semiconductor layer, such as indium gallium zinc oxide (IGZO), is deposited. It should be noted that the yttrium oxide layer can protect the carbon nanotubes underneath during the process of depositing the oxide semiconductor layer.

[0075] Step S108: Figure 6H As shown, a first electrode and a second electrode of a write transistor are formed on the oxide semiconductor layer.

[0076] Step 109: Fig.6I As shown, the oxide semiconductor other than the active layer of the write transistor is etched and stripped off.

[0077] An embodiment of the present disclosure also provides an integrated circuit. Figure 7 A schematic diagram of an integrated circuit provided by an embodiment of the present disclosure. Figure 7As shown, the integrated circuit 500 includes a semiconductor substrate 510, a first passivation layer 520 and a cache 530; the semiconductor substrate 510 includes a logic control circuit, the first passivation layer is located on the semiconductor substrate 510, the cache 530 is located on the side of the first passivation layer 520 away from the semiconductor substrate 510, and the cache 530 includes the above-mentioned memory 200. Therefore, since the cache adopts the above-mentioned memory, it has a strong anti-coupling and anti-interference ability, which can reduce the amount of charge coupling to the storage node, thereby having a strong data integrity. In addition, the cache can also have a stable and read time and a faster read speed while having a higher data retention time. At the same time, since the cache is directly formed on the side of the first passivation layer away from the semiconductor substrate, it can be integrated in the integrated circuit, thereby improving the data transmission bandwidth, realizing the high-speed and high-bandwidth interconnection between the back-end fast cache and the lower-level storage and computing integrated chip, greatly improving the speed of the integrated circuit, and reducing the power consumption caused by data handling.

[0078] In some examples, such as Figure 7 As shown, the integrated circuit 500 further includes an internal memory 540 located on a side of the first passivation layer 520 away from the semiconductor substrate 510 .

[0079] For example, Figure 7 As shown, the internal memory 540 is directly disposed on the surface of the first passivation layer 520 away from the semiconductor substrate 510 .

[0080] For example, Figure 7 As shown, the buffer 530 is also directly disposed on the surface of the first passivation layer 520 away from the semiconductor substrate 510 .

[0081] For example, the internal memory 540 includes at least one of a phase change memory (PCM) and a resistive random access memory (RRAM).

[0082] In some examples, the semiconductor substrate 510 includes a silicon substrate, such as a single crystal silicon substrate, a polycrystalline silicon substrate, etc.

[0083] Figure 8 FIG. 1 is a schematic diagram of another integrated circuit provided by an embodiment of the present disclosure. Figure 8As shown, the integrated circuit 500 includes a semiconductor substrate 510, a first passivation layer 520, an internal memory 540, a second passivation layer 550 and a buffer 530; the semiconductor substrate 510 includes a logic control circuit, the first passivation layer 520 is located on the semiconductor substrate 510, the internal memory 540 is located on the surface of the first passivation layer 520 away from the semiconductor substrate 510, the second passivation layer 550 is located on the side of the internal memory 540 away from the semiconductor substrate 510, the buffer 530 is located on the surface of the second passivation layer 550 away from the semiconductor substrate 510, and the buffer 530 includes the above-mentioned memory 200. Therefore, since the buffer adopts the above-mentioned memory, it has strong anti-coupling and anti-interference capabilities, can reduce the amount of charge coupled to the storage node, and thus has strong data integrity. In addition, the buffer can also have a stable and read time and a faster read speed while having a higher data retention time. At the same time, since the buffer is directly formed on the side of the first passivation layer away from the semiconductor substrate, it can be integrated into an integrated circuit, thereby increasing the data transmission bandwidth and improving the performance of the integrated circuit.

[0084] In some examples, the material of the first passivation layer or the second passivation layer includes, but is not limited to, insulating materials such as silicon oxide and silicon nitride.

[0085] There are a few points to note:

[0086] (1) In the drawings of the embodiments of the present application, only the structures related to the embodiments of the present application are involved, and other structures can refer to the general design.

[0087] (2) Unless there is a conflict, the features in the same embodiment or in different embodiments of the present application may be combined with each other.

[0088] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, comprising a storage unit structure, wherein: The memory cell structure includes a write transistor and a read transistor, each of which includes a gate, an active layer, a first electrode and a second electrode; The gate of the write transistor is configured to receive a scan signal, the first electrode of the write transistor is connected to the gate of the read transistor and serves as a storage node, the second electrode of the write transistor is configured to receive a write signal, the first electrode of the read transistor is configured to receive a first read signal, and the second electrode of the read transistor is configured to receive a second read signal; The write transistor is an N-type transistor, the read transistor is a P-type transistor, and the carrier mobility of the active layer of the read transistor is higher than the carrier mobility of the active layer of the write transistor.

2. The memory according to claim 1, wherein: The active layer of the write transistor includes one of an N-type two-dimensional semiconductor material and an N-type oxide semiconductor material, and the active layer of the readout transistor includes one of a P-type two-dimensional semiconductor material and a P-type oxide semiconductor material.

3. The memory according to claim 2, wherein: The P-type two-dimensional semiconductor material includes carbon nanotubes or tungsten selenide.

4. The memory according to claim 3, wherein: The active layer of the write transistor includes an N-type oxide semiconductor material, and the active layer of the read transistor includes carbon nanotubes.

5. The memory according to any one of claims 1 to 4, wherein: The memory cell structure is composed of the write transistor and the read transistor.

6. The memory according to any one of claims 1 to 4, further comprising: A write pipe word line connected to the gate of the write transistor; A write transistor bit line connected to the second electrode of the write transistor; A read tube word line connected to the first electrode of the read transistor; as well as A read transistor bit line is connected to the second electrode of the read transistor.

7. The memory according to any one of claims 1 to 4, wherein: The write transistor and the read transistor are manufactured by a back-end process.

8. The memory according to any one of claims 1 to 4, wherein: The active layer of the write transistor and the active layer of the read transistor are formed at a temperature less than 300 degrees Celsius.

9. The memory according to any one of claims 1 to 4, wherein: The active layer of the write transistor extends along a first direction, and the active layer of the read transistor extends along a second direction, and the first direction and the second direction are perpendicular to each other.

10. An integrated circuit comprising: A semiconductor substrate including a logic control circuit; A first passivation layer, located on the semiconductor substrate; as well as a buffer, located on a side of the first passivation layer away from the semiconductor substrate, Wherein, the cache comprises a memory according to any one of claims 1-9.

11. The integrated circuit of claim 10, further comprising: The in-memory memory is located on a side of the first passivation layer away from the semiconductor substrate.

12. The integrated circuit of claim 11, wherein: The in-memory memory includes at least one of a phase change memory and a resistive change memory.

13. The integrated circuit of claim 11 , further comprising: A second passivation layer is located on a side of the memory away from the semiconductor substrate, The buffer is located on a surface of the second passivation layer away from the internal memory.

14. The memory according to any one of claims 10 to 13, wherein: The semiconductor substrate includes a silicon substrate.

Images