Three-dimensional stacked access memory structure and integration method thereof

Abstract

The application provides a three-dimensional stacked access memory structure and an integrated method thereof, and belongs to the technical field of semiconductors. The memory is composed of multiple unit structures stacked from bottom to top, the unit structure comprises a ring gate low-power bidirectional conducting device as a write-in tube of the memory and a storage capacitor, the source end of the write-in tube simultaneously serves as the bottom electrode of the storage capacitor, the write-in tube and the storage capacitor are connected in the horizontal direction, the gate ends of the write-in tubes of the unit structures in the same row are connected together through a gate conductive layer to form a word line, the drain ends of the write-in tubes of the unit structures in the same column are connected together through a contact metal to form a bit line, the top electrodes of the storage capacitors in the same row are connected together through an interconnection metal to form a plate line, the memory has long memory holding time, fast readout speed and low power consumption, the storage density is high due to the stacking of multiple storage units, and in the integrated method, the repetitive unit structures share process steps such as photolithography, etching, ion implantation and annealing, thereby reducing the process cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a three-dimensional stacked access memory structure and an integration method thereof. BACKGROUND

[0002] With the development of artificial intelligence and Internet of Things technology, the demand for high-speed, high-density, low-power storage is increasing. Existing storage needs to be compromised between operation speed, storage density and operation power consumption, and cannot have all three advantages at the same time. Therefore, a new type of high-speed, high-density, low-power storage is needed. SUMMARY

[0003] The purpose of the present application is to design a three-dimensional stacked access memory structure and an integration method thereof, which comprises a ring gate low-power bidirectional conduction device as a write tube of the memory and a storage capacitor, so as to realize high-speed reading and writing while prolonging the retention time of the memory and reducing the power consumption of the memory.

[0004] The technical scheme of the present application is as follows:

[0005] A three-dimensional stacked access memory structure is composed of a plurality of unit structures stacked from bottom to top, each unit structure comprising a write tube and a storage capacitor, the source end of the write tube simultaneously serving as the bottom electrode of the storage capacitor, so as to realize the connection of the write tube and the storage capacitor in the horizontal direction. The gate ends of the write tubes of the same row of unit structures are connected together through a gate conductive layer to form a word line WL, the drain ends of the write tubes of the same column of unit structures are connected together through a contact metal to form a bit line BL, and the top electrodes of the storage capacitors of the same row are connected together through an interconnection metal to form a plate line PL. The write tube is a low-power bidirectional conduction device with a ring gate structure, and the specific features are that the channel of the write tube is composed of a write channel layer, the gate end is composed of a gate dielectric layer and a gate conductive layer, the drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, i.e. the doping types of the semiconductor parts of the source end and the drain end are opposite. The storage capacitor is composed of a bottom electrode, a storage medium and a top electrode, the bottom electrode is composed of the contact metal of the source end of the write tube, the storage medium layer surrounds the bottom electrode, and the top electrode surrounds the storage medium layer.

[0006] The present application also provides an integration method of the above-mentioned three-dimensional stacked access memory structure, and the specific steps include:

[0007] Step 1: depositing a plurality of layers of sacrificial layer material and write channel layer material on the substrate, specifically, depositing a layer of sacrificial layer material, then depositing a layer of write channel layer material, then repeating the deposition of the sacrificial layer material and the write channel layer material, and finally depositing the material as the sacrificial layer material, the number of layers of the write channel layer is the number of repetitions of the unit structure in the above-mentioned memory structure;

[0008] Step 2: defining the active region, specifically, patterning the active region by lithography, then etching the sacrificial layer material and the write channel layer material outside the active region to form the active region;

[0009] Step 3: forming active region isolation, specifically, depositing isolation layer material, then patterning the memory array area by lithography, then etching the excess isolation layer material outside the memory array, then planarizing by chemical mechanical polishing (CMP);

[0010] Step 4: forming side wall isolation, specifically, patterning the side wall area by lithography, then etching the sacrificial layer material and the isolation layer material in the side wall area, then depositing side wall layer material, then planarizing by CMP, then patterning the memory array area by lithography, then etching the excess side wall layer material outside the memory array;

[0011] Step 5: forming write tube gate ends, specifically, patterning the area between the write tube gates and the gates by lithography, then etching the isolation layer between the write tube gates, then depositing side wall layer material, then planarizing by CMP, then patterning the area between the write tube gates by lithography, then etching the excess side wall layer material between the write tube gates, then preparing the gate stack by standard polySi-SiO2 process or HKMG process, then removing the photoresist and excess material;

[0012] Step 6: forming source-drain semiconductor layers, specifically, patterning the drain region of the write tube by lithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by lithography, then etching the sacrificial layer material in the source region of the write tube, then forming an N-type semiconductor layer by ion implantation;

[0013] Step 7: Forming source-drain contact, the specific method is to pattern the source and drain of the write-in tube by means of photolithography, then etching the isolation layer material in the region between the source and drain of the write-in tube and the isolation layer material in the region between the drain, then depositing the side wall layer material, then planarizing by means of CMP, then patterning the source and drain of the write-in tube by means of photolithography, then etching the excess side wall layer material in the region between the source and drain of the write-in tube and in the region between the drain, then depositing the contact pre-metal, then reacting the contact pre-metal with the semiconductor by means of annealing to generate metal silicide as the contact metal, then removing the unreacted contact pre-metal, then activating the impurities by means of annealing;

[0014] Step 8: Forming storage capacitor region, the specific method is to pattern the region other than the storage capacitor by means of photolithography, then depositing the storage medium layer and the top metal electrode layer;

[0015] Step 9: Cutting off the storage capacitor interconnection area, the specific method is to pattern the storage capacitor region by means of photolithography, then etching the storage medium layer and the top metal electrode layer;

[0016] Step 10: Forming plate line interconnection line, the specific method is to deposit the side wall layer material, define the region other than the plate line interconnection line by means of photolithography, then etch the side wall layer material at the plate line interconnection line, then deposit the interconnection metal layer, then remove the excess photoresist and metal;

[0017] Step 11: Forming bit line contact, the specific method is to photolithograph the region other than the bit line, then etch the sacrificial layer material at the bit line, then deposit the contact pre-metal, then react the contact pre-metal with the semiconductor by means of annealing, then remove the unreacted contact pre-metal, then anneal, and the metal silicide formed in the bit line region can be used as the bit line contact.

[0018] Specifically, the substrate in step 1 can be a bare silicon wafer or a silicon wafer on which a front-end device and circuit have been prepared. The sacrificial layer material can be fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or other dielectric materials with a dielectric constant not greater than that of silicon dioxide, or a semiconductor material such as germanium silicon. The thickness of the deposited single-layer sacrificial layer material is between 10 nm and 500 nm, and the deposition method of the sacrificial layer material can be PVD, CVD, epitaxy, etc. The write-in channel layer material can be a semiconductor material such as amorphous silicon or single-crystal silicon, and the thickness of the deposited single-layer write-in channel layer material is between 10 nm and 500 nm, and the deposition method of the write-in channel layer material can be PVD, CVD, epitaxy, etc.

[0019] The isolation material in step 3 can be a dielectric material such as silicon dioxide, and the deposition method of the isolation material can be PVD, CVD, ALD, etc. The thickness of the isolation layer material is greater than the total thickness of the multiple layers of stacked sacrificial layer material and write-in channel layer material.

[0020] The sidewall material in step 4 can be a dielectric material such as silicon nitride, and the sidewall material can be deposited by PVD, CVD, ALD or the like, and the thickness of the sidewall layer material is greater than the total thickness of the multi-layer stack of the sacrificial layer material and the write channel layer material;

[0021] The P-type impurities in step 6 can be boron or boron fluoride, and the N-type impurities can be phosphorus or arsenic, the ion implantation energy is between 1keV and 100keV, the ion implantation dose is between 1E13cm -2 and 1E17cm -2 , and the ion implantation angle is between 0° and 90°;

[0022] The contact pre-metal material in steps 7 and 11 can be a metal such as titanium, nickel or cobalt, and the contact metal material can be a metal silicide material such as titanium silicon, nickel silicon or cobalt silicon. The contact pre-metal material can be deposited by PVD or the like, and the thickness of the contact pre-metal material is between 10nm and 1000nm;

[0023] The storage medium layer material in step 8 can be a high dielectric constant layer such as hafnium oxide, zirconium oxide, aluminum oxide and the like, and a stack thereof, or a resistive switching medium layer such as tantalum oxide, or a phase change material such as GeSbTe, or a ferroelectric medium layer such as hafnium gallium oxide, hafnium lanthanum oxide, hafnium silicon oxide, and the like, and the top layer metal electrode layer material can be a metal material such as titanium nitride, tantalum nitride, tungsten or the like;

[0024] The interconnection metal material in step 10 can be a metal material such as tungsten, copper, titanium nitride, tantalum nitride or the like, or a stack of several metals.

[0025] The specific technical effects of the three-dimensional stacked access memory structure and the integrated method thereof are as follows:

[0026] 1. The write tube of the proposed memory structure is a ring gate low power bidirectional conduction device, which can simultaneously realize long hold time and low power consumption;

[0027] 2. The proposed memory structure is a three-dimensional structure, which can realize the stacking of multiple storage units in a limited area, thereby increasing the storage density;

[0028] 3. The proposed integrated method allows multiple repetitive unit structures in the storage structure to share process steps such as photolithography, etching, ion implantation, annealing and the like, thereby significantly reducing the process cost per bit of storage information in the storage structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic view of the perspective view; Figures 2 to 13

[0030] Figure 2 ​is a presentation effect diagram of the memory structure and its integrated method according to the present application, showing a cross-sectional view along the channel direction, wherein Figure 2 (b) is a schematic diagram of a single memory cell structure, Figure 2 (a) is a memory structure diagram after stacking a plurality of cell structures up and down;

[0031] Figures 3-13 is a preparation step diagram of the memory structure according to the present application, obtained by the integrated method according to the present application, wherein:

[0032] Figure 3 is a front view of depositing a plurality of sacrificial layer materials and a write channel layer;

[0033] Figure 4 is a top view after defining an active region;

[0034] Figure 5 is a top view after forming an active region isolation layer;

[0035] Figure 6 is a front view after forming a side wall isolation layer;

[0036] Figure 7 (a) is a cross-sectional view along the channel direction after forming the write tube gate end, Figure 7 (b) is a top view after forming the write tube gate end;

[0037] Figure 8 is a cross-sectional view along the channel direction after forming the source-drain semiconductor layer;

[0038] Figure 9 is a cross-sectional view along the channel direction after forming the source-drain contact;

[0039] Figure 10 is a cross-sectional view along the channel direction after forming the storage capacitor region;

[0040] Figure 11 is a cross-sectional view along the channel direction after cutting off the storage capacitor interconnection region;

[0041] Figure 12 is a cross-sectional view along the channel direction after forming the plate line interconnection line;

[0042] Figure 13 is a cross-sectional view along the channel direction after forming the bit line contact;

[0043] in the figure:

[0044] 1 - write channel layer 2 - sacrificial layer

[0045] 3 - isolation layer 4 - side wall layer

[0046] 5 - gate dielectric layer 6 - gate conductive layer

[0047] 7 - P-type semiconductor layer 8 - N-type semiconductor layer

[0048] 9 - contact metal 10 - storage dielectric layer

[0049] 11 - top metal electrode 12 - interconnection metal

[0050] 13 - WL 14 - BL

[0051] 15 - PL DETAILED DESCRIPTION

[0052] The application will be further described by examples. It should be noted that the purpose of the disclosed examples is to help further understand the application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the application and the appended claims. Therefore, the application should not be limited to the disclosed examples, and the scope of the application claimed is defined by the scope of the claims.

[0053] Figure 2 is one of the presentation effect schematic diagrams obtained by using the memory structure and the integrated method proposed by the application, wherein Figure 2 (b) is a schematic diagram of a single memory cell structure, Figure 2 (a) is a memory structure diagram after stacking a plurality of cell structures up and down. Figure 1 is to illustrate Figures 2 to 13 is a schematic diagram of a perspective view, wherein the directions of three perspective views of a section along a channel direction, a top view and an elevation view are marked. Figure 2 (a) shows a memory structure composed of a plurality of Figure 2 (b) shows a cell structure stacked from bottom to top, wherein Figure 2 In (b), the write tube is located on the left side and the storage capacitor is located on the right side. Each cell structure is composed of a write tube and a storage capacitor, and the source end of the write tube simultaneously serves as the bottom electrode of the storage capacitor, thereby realizing the connection of the write tube and the storage capacitor in the horizontal direction. In each cell structure, the write tube is a low-power bidirectional conduction device with a ring gate structure, and the specific features are as follows: the channel of the write tube is composed of a write tube channel layer 1 composed of lightly doped single crystal silicon, and the right side and the left side of the write tube channel are the source end and the drain end thereof, respectively. The gate end is composed of a laminated gate dielectric layer 5 composed of silicon dioxide and hafnium oxide and a gate conductive layer 6 composed of titanium nitride, with a length of 60 nm. The gate end surrounds the channel in the direction perpendicular to the channel, and the gate end is in contact with the channel in the horizontal direction. The storage capacitor is composed of a storage capacitor dielectric layer 10 composed of silicon dioxide and a storage capacitor electrode 9 composed of titanium nitride, with a length of 60 nm. The storage capacitor electrode 9 is in contact with the bottom electrode of the storage capacitor in the horizontal direction, and the storage capacitor dielectric layer 10 is in contact with the storage capacitor electrode 9 in the vertical direction. The bottom electrode of the storage capacitor is in contact with the source end of the write tube in the horizontal direction. Figure 2The gate end is located on both sides of the channel in the cross-sectional view along the channel direction. The source end is composed of the contact metal 9 composed of metal silicide and the N-type semiconductor layer 8 composed of arsenic-doped single crystal silicon. The source end is located on the right side of the channel, and the source end is next to the gate end in the horizontal direction. The drain end is composed of the contact metal 9 composed of metal silicide and the P-type semiconductor layer 7 composed of boron fluoride-doped single crystal silicon. The drain end is located on the left side of the channel, and the drain end is separated from the gate end by 40 nm in the horizontal direction. The storage capacitor is composed of a bottom electrode, a storage medium layer, and a top electrode. The specific features are as follows: the bottom electrode of the storage capacitor is composed of the contact metal 9 composed of the source end metal silicide of the write tube, the storage medium layer 10 wraps the contact metal 9 of the source end of the write tube, and the top metal electrode layer 11 wraps the storage medium layer 10.

[0054] Figure 2 (a) The memory structure shown can be obtained by stacking a plurality of Figure 2 (b) The unit structure shown is stacked up and down. The specific features are as follows: the write tube gate end of the same row of unit structures is connected together through the gate conductive layer 6 to form a word line WL13, the write tube drain end of the same column of unit structures is connected together through the contact metal 9 to form a bit line BL14, and the storage capacitor top electrode 11 of the same row of unit structures is connected together through the interconnection metal 12 to form a plate line PL15. In each unit structure, the source end of the write tube serves as the top electrode of the storage capacitor.

[0055] Figure 2 The memory shown can be prepared by the integrated method proposed in this patent. The specific method is shown in Figures 3 to 13 , and the steps are as follows:

[0056] First, deposit a sacrificial layer material composed of multiple layers of fluorine-doped silicon dioxide and a write channel layer material composed of amorphous silicon on the substrate, as shown in Figure 3 . The specific method is to deposit a layer of 200 nm fluorine-doped silicon dioxide, then deposit a layer of 100 nm amorphous silicon, then repeat the deposition of fluorine-doped silicon dioxide and amorphous silicon layers, a total of four layers of fluorine-doped silicon dioxide and three layers of amorphous silicon;

[0057] Second, define the active area, as shown in Figure 4 . The specific method is to pattern the active area by lithography, then etch the fluorine-doped silicon dioxide and amorphous silicon outside the active area to form the active area;

[0058] Next, form the active area isolation layer, as shown in Figure 5 . The specific method is to deposit an isolation layer material composed of 1300 nm of silicon dioxide, then pattern the storage array area by lithography, then etch the excess silicon dioxide outside the storage array, and then perform planarization by chemical mechanical polishing (CMP);

[0059] Next, form the side wall isolation layer, as shown in Figure 6 the specific method is to pattern the side wall area by lithography, then etch the fluorine-doped silicon dioxide and silicon dioxide of the side wall area, then deposit the side wall layer material composed of 1300nm silicon nitride, then planarize by CMP, then pattern the storage array area by lithography, then etch the excess silicon nitride outside the storage array;

[0060] Next, form the write tube gate end, as shown in Figure 7 the specific method is to pattern the area between the write tube gate and the gate by lithography, then etch the silicon dioxide isolation layer between the write tube gates, then deposit the silicon nitride side wall, then planarize by CMP, then pattern the area between the write tube gates by lithography, then etch the excess silicon nitride between the write tube gates, then prepare the gate dielectric layer and gate conductive layer using the standard HKMG process, then remove the photoresist and excess material, which forms the gate conductive layer connecting the gate ends of multiple unit structures together to form the WL.

[0061] Next, form the source-drain semiconductor layer, as shown in Figure 8 the specific method is to pattern the drain area of the write tube by lithography, then etch the fluorine-doped silicon dioxide inside the drain area, then ion implant boron fluoride, with implantation conditions of 5keV 5E15cm -2 , and an implantation angle of 10°, then pattern the source area of the write tube by lithography, then etch the fluorine-doped silicon dioxide inside the source area of the write tube, then ion implant arsenic, with implantation conditions of 12keV 5E15cm -2 , and an implantation angle of 10°;

[0062] Next, form the source-drain contact, as shown in Figure 9 the specific method is to pattern the source and drain of the write tube by lithography, then etch the silicon dioxide isolation layer inside the area between the sources of the write tube and the silicon dioxide isolation layer inside the area between the drains of the write tube, then deposit the silicon nitride side wall, then planarize by CMP, then pattern the source and drain of the write tube by lithography, then etch the excess silicon nitride material inside the area between the sources and the area between the drains of the write tube, then deposit 90nm nickel, then anneal at 500℃ for 15min to generate nickel-silicon alloy, then remove the unreacted nickel, then anneal at 600℃ for 30min to activate the impurities while converting the amorphous silicon of the write tube area into single crystal silicon;

[0063] Next, form the storage capacitor area, as shown in Figure 10 the specific method is to pattern the area outside the storage capacitor by lithography, then deposit 10nm hafnium oxide as the storage medium layer, then deposit 20nm titanium nitride as the top metal electrode layer;

[0064] Next, the storage capacitor interconnection region is cut off, as shown in Figure 11 The specific method is to pattern the storage capacitor region by photolithography, and then etch hafnium oxide and titanium nitride.

[0065] Next, the plate line interconnection line is formed, as shown in Figure 12 The specific method is to deposit 1300nm silicon nitride, define the region outside the plate line interconnection line by photolithography, etch the silicon nitride at the plate line interconnection line, then deposit 100nm tungsten as the interconnection metal layer, and then remove the extra photoresist and metal.

[0066] Next, the bit line contact is formed, as shown in Figure 13 The specific method is to photolithograph the region outside the bit line, etch the fluorine-doped silicon dioxide at the bit line, deposit 50nm nickel, anneal at 550℃ for 12min, remove the unreacted nickel, then anneal again at 550℃ for 30min, and form the contact metal composed of nickel-silicon alloy in the BL region, which can be used as the bit line contact.

[0067] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art, without departing from the scope of the present application, can make many possible changes and modifications to the present application, or modify it into equivalent embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the scope of the present application, shall still fall within the scope of protection of the present application.

Claims

1. An integrated method of a three-dimensional stacked access memory structure, comprising: The specific steps include: Step 1: depositing a plurality of layers of sacrificial layer material and write channel layer material on a substrate, specifically, depositing a layer of sacrificial layer material, then depositing a layer of write channel layer material, then repeating the deposition of the sacrificial layer material and the write channel layer material, and finally depositing the material as the sacrificial layer material, the number of layers of the write channel layer being the number of repetitions of the unit structure in the above-mentioned memory structure; Step 2: defining an active region, specifically, patterning the active region by lithography, then etching the sacrificial layer material and the write channel layer material outside the active region to form the active region; Step 3: forming an active region isolation, specifically, depositing an isolation layer material, then patterning the storage array area by lithography, then etching the excess isolation layer material outside the storage array, then planarizing by chemical mechanical polishing (CMP); Step 4: forming a side wall isolation, specifically, patterning the side wall area by lithography, then etching the sacrificial layer material and the isolation layer material in the side wall area, then depositing a side wall layer material, then planarizing by CMP, then patterning the storage array area by lithography, then etching the excess side wall layer material outside the storage array; Step 5: forming a write tube gate end, specifically, patterning the area between the write tube gates and the gates by lithography, then etching the isolation layer between the write tube gates, then depositing a side wall layer material, then planarizing by CMP, then patterning the area between the write tube gates by lithography, then etching the excess side wall layer material between the write tube gates, then preparing a gate stack by standard polySi-SiO2 process or HKMG process, then removing the photoresist and excess material; Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by lithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by lithography, then etching the sacrificial layer material in the source region of the write tube, then forming an N-type semiconductor layer by ion implantation; Step 7: forming a source-drain contact, specifically, patterning the source and drain of the write tube by lithography, then etching the isolation layer material in the area between the source and drain of the write tube and the isolation layer material in the area between the source and drain of the write tube, then depositing a side wall layer material, then planarizing by CMP, then patterning the source and drain of the write tube by lithography, then etching the excess side wall layer material in the area between the source and drain of the write tube and in the area between the source and drain of the write tube, then depositing a pre-contact metal, then reacting the pre-contact metal with the semiconductor by annealing to form a metal silicide as a contact metal, then removing the unreacted pre-contact metal, then activating the impurities by annealing; Step 8: forming a storage capacitor area, specifically, patterning the area outside the storage capacitor by lithography, then depositing a storage medium layer and a top metal electrode layer; Step 9: cutting off the storage capacitor interconnection area, specifically, patterning the storage capacitor area by lithography, then etching the storage medium layer and the top metal electrode layer; Step 10: Forming plate line interconnection, the specific method is to deposit side wall layer material, define the area outside the plate line interconnection by photolithography, then etch the side wall layer material at the plate line interconnection, then deposit interconnection metal layer, and then remove the excess photoresist and metal; Step 11: Forming bit line contact, the specific method is to photolithograph the area outside the bit line, then etch the sacrificial layer material at the bit line, then deposit pre-contact metal, then react the pre-contact metal with the semiconductor by annealing, then remove the unreacted pre-contact metal, and then anneal to form metal silicide in the bit line area as the bit line contact.

2. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The substrate in step 1 is a bare silicon wafer or a silicon wafer on which a front-end device and circuit have been prepared; the sacrificial layer material is a dielectric material with a dielectric constant not greater than that of silicon dioxide, such as fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a semiconductor material such as germanium-silicon; the thickness of the deposited single-layer sacrificial layer material is between 10 nm and 500 nm; the deposition method of the sacrificial layer material is PVD, CVD or epitaxy; and the write-in channel layer material is amorphous silicon or single-crystal silicon, and the thickness of the deposited single-layer write-in channel layer material is between 10 nm and 500 nm. The isolation material in step 3 is a dielectric material, such as silicon dioxide, and the deposition method of the isolation material is PVD, CVD or ALD, and the thickness of the isolation layer material is greater than the total thickness of the multilayer-stacked sacrificial layer material and write-in channel layer material.

3. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The side wall material in step 4 is a dielectric material, such as silicon nitride, and the deposition method of the side wall material is PVD, CVD or ALD, and the thickness of the side wall layer material is greater than the total thickness of the multilayer-stacked sacrificial layer material and write-in channel layer material.

4. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The pre-contact metal material in steps 7 and 11 is a metal, such as titanium, nickel or cobalt, and the contact metal material is a metal silicide material, such as titanium silicide, nickel silicide or cobalt silicide; the deposition method of the pre-contact metal material is PVD, and the thickness of the pre-contact metal material is between 10 nm and 1000 nm.

5. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The P-type impurity ion implanted in step 6 is boron or boron fluoride, the N-type impurity is phosphorus or arsenic, the ion implantation energy is between 1 keV and 100 keV, the ion implantation dose is between 1E13 cm -2 and 1E17 cm -2 , and the ion implantation angle is between 0° and 90°.

6. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The storage medium layer material in step 8 is a high-dielectric-constant layer and its stack, such as hafnium oxide, zirconium oxide or aluminum oxide, or a resistive switching medium layer, such as tantalum oxide, or a phase-change material, such as GeSbTe, or a ferroelectric medium layer, such as hafnium gallium oxide, hafnium lanthanum oxide or hafnium silicon oxide, and the top metal electrode layer material is a metal material, such as titanium nitride, tantalum nitride or tungsten.

7. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The interconnection metal material in step 10 is a metal material, such as tungsten, copper, titanium nitride or tantalum nitride, or a stack of several metals.

8. The method of integrating three-dimensional stacked access memory structures of claim 1, wherein, The plurality of unit structures are stacked from bottom to top, each unit structure comprising a write-in tube and a storage capacitor, the source end of the write-in tube simultaneously serving as the bottom electrode of the storage capacitor, thereby realizing the connection of the write-in tube and the storage capacitor in the horizontal direction; the gate ends of the write-in tubes of the same row of unit structures are connected together through a gate conductive layer to form a word line WL; the drain ends of the write-in tubes of the same column of unit structures are connected together through a contact metal to form a bit line BL; and the top electrodes of the storage capacitors of the same row are connected together through an interconnection metal to form a plate line PL.

9. A three-dimensional stacked access memory structure integrated using the integrated method of claim 1, wherein, ​ The write tube is a low-power bidirectional conduction device with a ring gate structure, the channel of the write tube has a source end and a drain end on both sides thereof, the gate end surrounds the channel in a direction perpendicular to the channel, the source end is adjacent to the gate end in a horizontal direction, and the drain end is separated from the gate end by a distance in the horizontal direction; the channel of the write tube is composed of a write channel layer, the gate end is composed of a gate dielectric layer and a gate conductive layer, the drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the semiconductor portions of the source end and the drain end are opposite; The storage capacitor is composed of a bottom electrode, a storage medium and a top electrode, the bottom electrode is composed of the contact metal of the source end of the write tube, the storage medium layer surrounds the bottom electrode, and the top electrode surrounds the storage medium layer.

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