Read-only memory array, integrated circuit device and manufacturing method thereof

Abstract

A read only memory (ROM) array includes first to fourth rows of ROM bits including respective adjacent first to fourth active regions. Each of the first to fourth rows of ROM bits includes a total of four adjacent ROM bits positioned along a respective one of the first to fourth active regions, each of the total of four of each row of ROM bits includes two source / drain (S / D) regions of the respective active region, and three S / D regions of each row of ROM bits are shared by the four ROM bits. The embodiment of the invention also discloses an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a read-only memory array, an integrated circuit device, and a method for manufacturing the same. Background Art

[0002] The ongoing trend toward integrated circuit (IC) miniaturization has resulted in devices that are progressively smaller, consume less power, yet provide more functionality at higher speeds than earlier technologies. This miniaturization has been enabled by design and manufacturing innovations tied to increasingly stringent specifications. A variety of electronic design automation (EDA) tools are used to generate, modify, and verify the design of semiconductor devices while ensuring that IC structural design and manufacturing specifications are met. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a read-only memory (ROM) array is provided, comprising: first to fourth rows of ROM bits, including corresponding adjacent first to fourth active regions, wherein each of the first to fourth rows of ROM bits includes a total of four adjacent ROM bits positioned along a corresponding one of the first to fourth active regions, each of the total four ROM bits of each ROM bit includes two source / drain (S / D) regions in the corresponding active region, and three S / D regions of each row of ROM bits are shared by four ROM bits.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit (IC) device is provided, comprising: adjacent first to fourth active regions extending between a first dummy gate structure and a second dummy gate structure; a first gate electrode extending through each of the first to fourth active regions and offsetting the gate pitch from the first dummy gate structure; a second gate electrode extending through each of the first to fourth active regions and offsetting the gate pitch from the first gate electrode; a third gate electrode extending through each of the first and second active regions and offsetting the gate pitch from the second gate electrode; a fourth gate electrode extending through each of the first and second active regions and offsetting the gate pitch from the third gate electrode and each of the second dummy gate structures; a fifth gate electrode extending through each of the third and fourth active regions, offsetting the gate pitch from the second gate electrode, and separated from the third gate electrode by a first isolation structure; and a sixth gate electrode extending through each of the third and fourth active regions, offsetting the gate pitch from the fifth gate electrode and each of the second dummy gate structures, and separated from the fourth gate electrode by a second isolation structure.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing an integrated circuit (IC) device is provided, the method comprising: forming adjacent first to fourth active regions in a semiconductor substrate; and constructing a plurality of gate structures, the constructing of the plurality of gate structures comprising: constructing a first dummy gate structure and a second dummy gate structure above an end point of each of the first to fourth active regions; constructing a first gate structure offset from the first dummy gate structure by a gate pitch, constructing the first gate structure comprising forming a first gate electrode extending above the first to fourth active regions; constructing a second gate structure offset from the first gate structure by a gate pitch, constructing the second gate structure comprising forming a first gate electrode extending above the first to fourth active regions a second gate electrode; constructing a third gate structure with a gate pitch offset from the second gate electrode, constructing the third gate structure including: forming a third gate electrode extending over the first active area and the second active area; forming a fourth gate electrode extending over the third active area and the fourth active area; and forming a first isolation structure between the third gate electrode and the fourth gate electrode; and constructing a fourth gate structure with a gate pitch offset from each of the third gate structure and the second dummy gate structure, constructing the fourth gate structure including: forming a fifth gate electrode extending over the first active area and the second active area; forming a sixth gate electrode extending over the third active area and the fourth active area; and forming a second isolation structure between the fifth gate electrode and the sixth gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B 2 are a plan view and a side view, respectively, of an IC device and a layout diagram according to some embodiments.

[0008] Figure 2A and Figure 2B Schematic diagram and plan view, respectively, of an IC device and a layout diagram according to some embodiments.

[0009] Figure 3A and Figure 3B Schematic diagram and plan view, respectively, of an IC device and a layout diagram according to some embodiments.

[0010] Figure 4A and Figure 4B Schematic diagram and plan view, respectively, of an IC device and a layout diagram according to some embodiments.

[0011] Figure 5A and Figure 5BSchematic diagram and plan view, respectively, of an IC device and a layout diagram according to some embodiments.

[0012] Figure 6 are plan views and layout views of an IC device according to some embodiments.

[0013] Fig. 7A and Figure 7B Schematic diagram and plan view, respectively, of an IC device and a layout diagram according to some embodiments.

[0014] Figure 8 is a flow chart of a method of manufacturing an IC according to some embodiments.

[0015] Fig. 9 is a flow chart of a method of generating an IC layout diagram according to some embodiments.

[0016] Fig.10 is a block diagram of an IC layout generation system according to some embodiments.

[0017] Fig.11 is a block diagram of an IC manufacturing system and its related IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0020] In various embodiments, a read-only memory (ROM) integrated circuit (IC) device and corresponding layout diagram and manufacturing method include four rows of ROM bits located on four adjacent active areas, each row having a total of four ROM bits, each ROM bit including a gate portion in the corresponding active area and two adjacent source / drain (S / D) regions. Three of the four S / D regions in each row are shared by the four ROM bits, such that the row length corresponds to five times the gate pitch.

[0021] Compared to other methods, for example, a method in which a total of two S / D regions shared among four ROM cells correspond to a row length six times the gate pitch, the ROM device can have a smaller area, shorter bit line length, and less variable bit line leakage.

[0022] As described below, according to various embodiments, Figure 1A and Figure 1B is a plan view and a side view of a NOR (non-or) type ROM IC device and a layout diagram 100, Figure 2A-Figure 5B depicts schematic diagrams representing non-limiting examples of programming states of an IC device / layout 100 and corresponding IC device / layouts 200-500, Figure 6 is a plan view of a NOR ROM device / layout diagram 600 including multiple instances of IC device / layout diagram 100, Fig. 7A and Figure 7B depicts a schematic diagram and plan view of a NOR-type IC device / configuration 700 including at least one example of an IC device or layout 100, Figure 8 is a flow chart of a method 800 for manufacturing a NOR-type ROM IC based on one or more of the IC layout diagrams 100-700, Fig. 9 For example, using the following Fig.10 The system 1000 discussed and e.g. Fig.10 Flowchart of method 900 of generating one or more of IC layout diagrams 100-700 by system 1000 in Fig.11 The IC manufacturing system 1100 is discussed in connection with an IC manufacturing process.

[0023] For the purpose of illustration, the examples in this article are Figure 1A-Figure 7B All are simplified. Figure 1A-Figure 7B is a diagram of an IC structure, device, and layout diagram, including and excluding various features to facilitate the following discussion. In various embodiments, except Figure 1A-Figure 7B In addition to the features shown in , the IC structure, device and / or layout diagram also includes one or more features corresponding to distribution structures, metal interconnects, contacts, through-holes, gate structures, source / drain (S / D) structures, body connections or other transistor elements, isolation structures, etc.

[0024] In each of the IC device / layout diagrams 100-700, reference numerals denote IC device features and IC layout features that are used to at least partially define the corresponding IC device features during the manufacturing process, for example, as described below with respect to Figure 8 Method 800 discussed below and / or with respect to Fig.11 The IC manufacturing flow is discussed in relation to the IC manufacturing system 1100. Thus, each of the IC device / layout diagrams 100-700 represents a view of an IC layout diagram 100-700 and a corresponding IC device 100-700.

[0025] Figure 1A An IC device / layout diagram 100 is shown, in accordance with some embodiments, along with X and Y directions and diagrams corresponding to features discussed below.

[0026] The IC device / layout 100 includes active areas / regions A0 - A3 extending in the X-direction, based on the fact that the IC device / layout 100 does not include additional active areas / regions between the active areas / regions A0 - A3 , referred to as adjacent active areas / regions.

[0027] Each active region / area A0-A3 extends from the dummy gate region / structure D1 to the dummy gate region / structure D2, each dummy gate region / structure D2 extends in the Y direction, and the gate regions / gate structures G0-G5 extend in the Y direction between the dummy gate regions and the dummy gate regions / structures D1 and D2. Each of the gate regions / structures G0 and G1 intersects / overlaps with each of the active regions / areas A0-A3, each of the gate regions / structures G2 and G3 intersects / overlaps with each of the active regions / areas A0 and A1, and each of the gate regions / structures G4 and G5 intersects / overlaps with each of the active regions / areas A2 and A3.

[0028] The gate region / structure G0 is offset from the dummy gate region / structure D1 in the positive X direction by a pitch CPP, also referred to in some embodiments as a contact polysilicon (poly) pitch CPP. The gate region / structure G1 is offset from the gate region / structure G0 in the positive X direction by a pitch CPP, each of the gate regions / structures G2 and G4 is offset from the gate region / structure G1 in the positive X direction by a pitch CPP, the gate region / structure G3 is offset from the gate region / structure G2 in the positive X direction by a pitch CPP, the gate region / structure G5 is offset from the gate region / structure G4 in the positive X direction by a pitch CPP, and the dummy gate region / structure D2 is offset from each of the gate regions / structures G3 and G5 in the positive X direction by a pitch CPP.

[0029] IC layout 100 includes a boundary PR, also referred to as a layout and routing boundary PR or prBoundaryPR in some embodiments, corresponding to a closed area in the IC layout that can be used to route signals and power connections, for example as part of an automatic layout and routing (APR) algorithm. Pseudo-gate regions D1 and D2 extend along a vertical portion of boundary PR.

[0030] The IC layout 100 also includes a cut gate region CG (labeled as a single instance for clarity) extending along the X direction. The location where the cut gate region CG intersects the gate region in the IC layout 100 corresponds to the isolation structure ISO (labeled as a single instance for clarity) in the corresponding IC device 100.

[0031] Each gate region G0 and G1 has two endpoints at an instance of the cut gate region CG extending along the horizontal portion of the boundary PR, and these endpoints correspond to two instances of the isolation structure ISO. Gate regions G2 and G4 have a single endpoint at an instance of the same cut gate region CG, and this instance corresponds to an instance of a single isolation structure ISO, and gate regions G3 and G5 have a single endpoint at an instance of the same cut gate region CG, and this instance corresponds to an instance of a single isolation structure ISO.

[0032] Near each location where gate regions / structures G0-G5 intersect / overlap with active regions / areas A1-A4, the corresponding active regions / areas A0-A3 include two instances of source / drain (S / D) regions / structures SD and overlying MD regions / segments MD (for clarity, the single instances are collectively referred to as SD / MD). As used herein, the term S / D regions / structures may refer to a source or a drain, either individually or collectively, depending on the context.

[0033] The four instances of bit lines BL0-BL3 and source line VSS are metal regions / segments extending in the X direction in the first metal layer and intersecting / overlapping with the corresponding active regions / areas A0-A3. Figure 1A As shown, additional metal regions / segments (not labeled for clarity), such as signal lines or power lines, extend in the first metal layer along the X direction between corresponding pairs of bit lines BL0-BL3 and source line VSS.

[0034] The via region / structure VG (labeled as a single instance for clarity) intersects / overlaps each of the gate regions / structures G0, G1, G3, and G4. The metal region / segment WL0 intersects / overlaps the gate region / structure G0 and the corresponding via region / structure VG, the metal region / segment WL1 intersects / overlaps the gate region / structure G1 and the corresponding via region / structure VG, the metal region / segment WL2 intersects / overlaps the gate region / structure G4 and the corresponding via region / structure VG, and the metal region / segment WL3 intersects / overlaps the gate region / structure G3 and the corresponding via region / structure VG.

[0035] Each of the metal regions / segments WL0, WL1, WL2, and WL3 and the corresponding via region / structure VG is part of a corresponding word line (collectively referred to as word lines WL) electrically connected to the corresponding gate region / structure G0, G1, G3, or G4. In some embodiments, metal regions / segments WL0-WL3 are referred to as word lines WL0-WL3.

[0036] In some embodiments, for example, the following Figure 6-7B In the discussed IC device / layout 600 or 700, the gate region / structure G2 extends beyond the IC device / layout 100 in the positive Y direction ( Figure 1A ), instances of metal region / segment WL2 intersect / overlap with extended portions of gate region / structure G2 and corresponding via region / structure VG, and / or gate region / structure G5 extends beyond IC device / layout 100 in the negative Y direction ( Figure 1A (not shown), an instance of metal region / segment WL3 intersects / overlaps an extension of gate region / structure G5 and a corresponding via region / structure VG.

[0037] An active area / region, such as active areas / regions A0-A3, is an area in an IC layout diagram that is included in the manufacturing process as part of defining an active area, also known as an oxide diffusion or definition (OD), located in a semiconductor substrate, either directly or in an n-well or p-well region / region (not shown for clarity), where one or more IC device features, such as S / D structures, are formed. In some embodiments, the active area is an n-type or p-type active region of a planar transistor, a FinFET (fin field effect transistor), or a GAA (all-around gate) transistor. In various embodiments, the active area (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga), or another suitable material).

[0038] In some embodiments, the active region is a region that is included in the IC layout as part of the manufacturing process to define the nanosheet structure, e.g., a continuous volume having one or more layers of semiconductor material doped with n-type or p-type. In various embodiments, a single nanosheet layer includes a single layer or multiple layers of a given semiconductor material.

[0039] In the embodiments discussed herein, each instance of active area / region A0-A3 is the same one of an n-type or p-type active area / region, for example, a p-type active area / region corresponding to the n-type ROM bits discussed below.

[0040] An S / D region / structure, such as an S / D region / structure SD, is an area in an IC layout diagram that is configured to have a doping type opposite to that of a corresponding active region as part of defining an S / D structure, also referred to in some embodiments as a semiconductor structure. In some embodiments, the S / D region / structure is configured to have a lower resistivity than an adjacent channel component (e.g., a portion of a corresponding active region / region of a planar FET, a fin structure of a FinFET, or a gate structure of a GAA transistor). In some embodiments, the S / D region / structure includes one or more portions having a doping concentration greater than one or more doping concentrations present in a corresponding channel component. In some embodiments, the S / D region / structure includes an epitaxial region of a semiconductor material, such as Si, SiGe, and / or silicon carbide SiC.

[0041] An MD region / segment, such as an MD region / segment MD, is a conductive area in an IC layout diagram that is included in the manufacturing process as part of defining an MD segment, also referred to as a conductive segment or an MD conductive line or conductive trace, located on and / or on a semiconductor substrate. In some embodiments, the MD segment includes a portion of at least one metal layer, such as a contact layer, that covers and contacts the substrate and has a thickness that is small enough to form an insulating layer between the MD segment and the overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low resistance electrical connection between IC structural elements, i.e., a resistance level below a predetermined threshold corresponding to one or more tolerance levels of resistance-based circuit performance impacts.

[0042] In various embodiments, the MD segment includes a portion of the semiconductor substrate and / or epitaxial layer, whose doping level, for example, based on an implantation process, is sufficient to give the segment a low resistance level. In various embodiments, the doped MD segment includes one or more dopant materials, whose doping concentration is about 1*10 16 / cubic centimeter (cm -3 ) or higher.

[0043] In some embodiments, the manufacturing process includes two MD layers, and the MD zone / segment, eg, MD zone / segment MD, refers to two MDs in the manufacturing process.

[0044] A gate region / structure, such as gate regions / structures G0-G5, is an area in an IC layout diagram that is included in a manufacturing process as part of defining a gate structure. A gate structure is a volume that includes one or more conductive segments (e.g., a gate electrode) that includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, whereby the one or more conductive segments are configured to control a voltage provided to an adjacent gate dielectric layer.

[0045] A gate dielectric layer, such as the gate dielectric layer of gate structures G0-G5, is a volume including one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4) and / or one or more other suitable materials, such as a low-k material having a k value less than 3.8 or a high-k material having a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5) or titanium oxide (TiO2), suitable for providing high resistance between IC structure elements, i.e., a resistance level above a predetermined threshold corresponding to one or more tolerance levels of resistance-based circuit performance.

[0046] A cut gate region, such as a cut gate region CG, also referred to in some embodiments as a cut polysilicon (CPO) region CG, is a region included in an IC layout diagram in a manufacturing process as a portion defining a portion of a gate electrode, which portion is removed and replaced with one or more dielectric materials in an operation after the gate electrode is formed, thereby electrically isolating adjacent portions of the gate electrode from each other.

[0047] An isolation feature / structure, such as isolation feature / structure ISO, is a feature of one or more regions in an IC layout diagram included in a manufacturing process as part of defining an isolation structure that is configured to electrically isolate adjacent features (e.g., adjacent gate electrode portions) from each other based on a cut gate region of the IC layout diagram. In some embodiments, an isolation feature / structure, such as isolation feature / structure ISO, includes a dielectric region / volume located between adjacent features, such as gate regions / structures G2 and G4 or G3 and G5. A dielectric region is a region in an IC layout diagram included in a manufacturing process as part of defining a volume that includes one or more insulating materials.

[0048] In some embodiments, the isolation feature / structure includes a dielectric region corresponding to a dummy (e.g., electrically isolated) gate region / structure (e.g., dummy gate region / structure D1 or D2). In some embodiments, the dummy gate region / structure includes a gate region / structure electrically connected (e.g., tied) to one or more features (e.g., adjacent instances of S / D region / structure SD) to turn off the corresponding transistor. In some embodiments, the dummy gate region / structure that overlaps / overlaps the edge of the active region / area, such as dummy gate region / structure D1 or D2, is referred to as a continuous polysilicon oxide defined edge (CPODE) region / structure.

[0049] A metal line or region, such as a power line VSS or a bit line BL, is an area in an IC layout diagram included in a manufacturing process as part of defining a metal line structure that includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, in a given metal layer of the manufacturing process. In various embodiments, the metal region / segment corresponds to the first metal layer of the manufacturing process (also referred to as metal zero layer M0 in some embodiments), or a second or higher level metal layer, such as metal layer M1 discussed below.

[0050] A via region / structure, such as via region / structure VG or VD discussed below, is an area in an IC layout diagram included in the manufacturing process as part of defining a via structure, which via structure includes one or more conductive materials and is configured to provide an electrical connection between an overlying conductive structure (e.g., metal segments WL0-WL3 or metal lines VSS or BL) and an underlying conductive structure (e.g., a gate electrode of a gate structure G0-G5) or an MD segment (such as an example of MD segment MD) or an S / D structure (such as an example of S / D structure SD).

[0051] Figure 1B A portion of an element of IC device / layout 100 , an X direction, and a Z direction are depicted in accordance with some embodiments. Figure 1B The elements shown in FIG. 1 are not necessarily included in the same XZ plane or arranged in the X direction as shown in the figure, and are arranged as shown in the figure only to illustrate the relative positions in the Z direction.

[0052] like Figure 1BAs shown, the active region / area OD represents one of the active regions / areas A0-A3. The MD region / segment MD is located on the active region / area OD, the via region / structure VD is located on the MD region / area MD, and the first metal region / segment M0 representing one of the bit lines BL0-BL3 or the source line VSS is located in the first metal layer and on the via region / structure VD. The first via region / structure VIA0 located on the first metal region / segment M0 and the first metal region / segment M1 located on the second metal layer and the first via region / structure VIA0 represent further electrical connections to one of the bit lines BL0-BL3 or the source line VSS.

[0053] The gate region / structure PO located on the active region / area OD represents one of the gate regions / structures G0-G5. The via region / structure VG is located on the gate electrode of the gate region / structure PO, and the second metal region / segment M0 located on the first metal layer and the via region or structure VG represents one of the metal regions / segments WL0-WL3. The second via region / structure VIA0 located on the second metal region / segment M0 and the second metal region / segment M1 located in the second metal layer and on the second via region / structure VIA0 represent further electrical connections to a word line corresponding to one of the metal regions / segments WL0-WL3.

[0054] With the above configuration, the IC device / layout 100 (also referred to as ROM array 100 in some embodiments) includes an array of four rows R0-R3 of ROM bits B(0,0)-B(3,3), each row including a total of four ROM bits (a single row is highlighted and labeled for clarity). Each ROM bit B(0,0)-B(3,3) (corresponding to B(word line number, row number)) includes a gate region / structure G0-G5 (electrically connected to a corresponding word line WL, such as including metal regions / segments WL0-WL3) and an intersection / overlap of active regions / areas A0-A3, as well as two adjacent S / D regions / structures SD and an overlying MD region / segment MD.

[0055] By further including electrical connections between two adjacent S / D regions / structures and each of the corresponding overlying bit lines BL0-BL3 and source line VSS, such as through the MD region / segment MD and the corresponding via region / structure VD, a given ROM bit is considered to have a first logic state, such as logic 1, corresponding to a functional transistor, as described below with respect to Figure 2A-Figure 5B By further including a single electrical connection or no electrical connection between two adjacent S / D regions / structures and the corresponding overlying bit lines BL0-BL3 or source line VSS, or an electrical connection between each adjacent S / D region / structure and a single one of the overlying bit lines BL0-BL3 or source line VSS, a given ROM bit is considered to have a second logic state, e.g., logic zero, corresponding to a non-functional transistor.

[0056] exist Figure 1A In the illustrated embodiment, the IC device / layout 100 does not include an instance of a via region / structure VD, and therefore each ROM bit B(0,0)-B(3,3) has a second logic state corresponding to no electrical connection to the corresponding overlying bit lines BL0-BL3 or source line VSS. In some embodiments, for example, the following description of Figure 2A-Figure 5B As a non-limiting example of the discussed IC devices / layouts 200-500, the IC device / layout 100 includes one or more ROM bits B(0,0)-B(3,3) having a first logic state, corresponding to an electrical connection including a via region / structure VD connected to each corresponding overlying bit line BL0-BL3 and a source line VSS.

[0057] like Figure 1A As shown, the four ROM bits B(0,0)-B(3,0) of row R0 include a total of five S / D regions / structures SD, corresponding to three S / D regions / structures SD shared between adjacent ROM bits of the four ROM bits B(0,0)-B(3,0). The configurations of ROM bits B(0,1)-B(3,1) of row R1, B(0,2)-B(3.2) of row R2, and B(0,3)-B(3.3) (not marked) of row R3 are similar.

[0058] The IC device / layout 100 is thus configured to include an array of ROM bits B(0,0)-B(3,3) including each of rows R0-R3, the ROM bits including a total of four ROM bits extending between dummy gate regions / structures D1 and D2, the extension distance corresponding to five times the pitch CPP. The IC device / layout 100 is thus able to have a smaller area, shorter bit line length, and less variable bit line leakage than other approaches, such as those where a total of two S / D regions shared between four ROM cells correspond to a row length of six times the gate pitch.

[0059] Figure 2A-Figure 5B 1 is a schematic diagram and plan view of IC devices / layouts 200-500 according to some embodiments. Each of the IC devices / layouts 200-500 is a non-limiting example of an IC device / layout 100 including a ROM bit having a first logic state corresponding to a logic 1 (logic 1 ROM bit) and a second logic state corresponding to a logic 0 (logic 0 ROM bit).

[0060] Figure 2B , Figure 3B , Figure 4B and Figure 5B Each of the Figure 1A and Figure 1B Various features are labeled in the Figures, but for clarity these features are not labeled. Figure 2B , Figure 3B , Figure 4B and Figure 5B Each of also includes an instance of a via region / structure VD as described below (labeled as a single instance for clarity).

[0061] Instead of bit lines BL0-BL3, Figure 3A and Figure 3B Including bit lines BL4-BL7, Figure 4A and Figure 4B Including bit lines BL8-BL11, Figure 5A and Figure 5B Including bit lines BL12-BL15. As described below, Figure 2A-Figure 5B Each of the corresponding four ROM bits in the bit lines BL0-BL15 depicted in represents a non-limiting example of bytes having values ​​increasing from 0000 to 1111.

[0062] like Figure 2A As shown, IC device / layout 200 includes logic 1 ROM bits located at locations corresponding to intersections of word line WL2 with each of bit lines BL2 and BL3 and intersections of word line WL3 with each of bit lines BL1 and BL3, and logic 0 bits located at other locations. Figure 2B As shown, each logic 1 ROM bit includes a through-hole region / structure VD located between the adjacent MD region / segment MD (and the underlying S / D region / structure SD) and the corresponding overlying bit lines BL1-BL3 and the source line VSS, and each logic 0 ROM bit includes zero through-hole regions / structure VD or a single through-hole region / structure VD corresponding to the S / D region / structure SD shared with the adjacent logic 1 ROM bit.

[0063] Figure 3A As shown, IC device / layout 300 includes a logic 1 ROM bit located at a position corresponding to the intersection of word line WL1 and each bit line BL4-BL7, the intersection of word line WL2 and each bit line BL6 and BL7, and the intersection of word line WL3 and each bit line BL5 and BL7, and a logic 0 bit at other positions. Figure 3B As shown, each logic 1 ROM bit includes a through-hole region / structure VD located between the adjacent MD region / segment MD (and the underlying S / D region / structure SD) and the corresponding overlying bit lines BL4-BL7 and the source line VSS, and each logic 0 ROM bit includes zero through-hole regions / structure VD, a single through-hole region / structure VD corresponding to the S / D region / structure SD shared with the adjacent logic 1 ROM bit, or in the case of position B (WL2, BL5), includes a through-hole region / structure VD located between each adjacent MD region / segment MD and the bit line BL5.

[0064] like Figure 4AAs shown, IC device / layout 400 includes logic 1 ROM bits at locations corresponding to intersections between word line WL0 and each of bit lines BL8-BL11, intersections between word line WL2 and each of bit lines BL10 and BL11, and intersections between word line WL3 and each of bit lines BL9 and BL11, and logic zero bits at other locations. Figure 4B As shown, each logic 1 ROM bit includes a via region / structure VD located between the adjacent MD region / segment MD (and the underlying S / D region / structure SD) and the corresponding overlying bit lines BL8-BL11 and the source line VSS, and each logic 0 ROM bit includes zero via regions / structure VD, a single via region / structure VD corresponding to the S / D region / structure SD shared with the adjacent logic 1 ROM bit, or in the case of positions B (WL1, BL10) and B (WLI, BL11), a via region / structure VD located between each adjacent MD region / segment MD and the source line VSS.

[0065] like Figure 5A As shown, IC device / layout 500 includes logic 1 ROM bits at locations corresponding to intersections of word lines WL0 and WL1 with bit lines BL12-BL15, intersections of word line WL2 with bit lines BL14 and BL15, and intersections of word line WL3 with bit lines BL13 and BL15, and logic 0 bits at other locations. Figure 5B As shown, each logic 1 ROM bit includes a via region / structure VD located between the adjacent MD region / segment MD (and the underlying S / D region / structure SD) and the corresponding overlying bit lines BL12-BL15 and the source line VSS, and each logic 0 ROM bit includes zero via regions / structure VD, a single via region / structure VD corresponding to the S / D region / structure SD shared with the adjacent logic 1 ROM bit, or in the case of position B (WL2, BL13), includes a via region / structure VD located between each adjacent MD region / segment MD and the source line VSS.

[0066] Figure 2A-Figure 5B A non-limiting example of an IC device / layout 100 is depicted that is configured to include logic 1 and logic 0 ROM bits to program byte values ​​of 0000-1111. Other configurations in which the IC device / layout 100 includes logic 1 and logic 0 ROM bits to program byte values ​​of 0000-1111 are also within the scope of the present disclosure.

[0067] Figure 6 Depicted is an IC device / layout 600 according to some embodiments. IC device / layout 600, also referred to as ROM array 600 in some embodiments, includes IC device / layout 100 and multiple instances in the X and Y directions, as described above with respect to Figure 1A-Figure 5BFor the sake of clarity, Figure 1A and Figure 1B The various features marked in are not marked.

[0068] exist Figure 6 In the illustrated embodiment, for illustrative purposes, the IC device / layout diagram 600 includes a total of four instances (two columns and two rows) of the IC device layout / diagram 100, each instance being a schematic diagram of the IC device layout / diagram 100 according to the above description. Figure 2A and Figure 2B The discussed non-limiting example configurations of IC device layout or diagram 200. IC device / layout diagram 600 including other numbers of columns and rows, such as more than two columns and / or rows, and one or more configurations other than IC device layout / diagram 200 are within the scope of the present disclosure.

[0069] Each instance of IC device / layout 100 includes electrical connections to each of word lines WL0-WL3. In some embodiments, IC device / layout 600 includes electrical connections from each instance of a corresponding one of word lines WL0-WL3 to a shared upper layer feature (not shown), such as an input / output (I / O) pad.

[0070] Examples of IC devices / layouts 100 adjacent to each other along the Y direction include those described above with respect to Figure 1A and Figure 1B The adjacent and thus shared gate regions / structures are, for example, gate regions G2 and G4 included in the instance of word line WL2, or gate regions G3 and G5 included in the instance of word line WL3. Therefore, the lengths of the corresponding instances of gate regions / structures G2 / G4 and G3 / G5 included in word lines WL2 and WL3 in the Y direction are equal to the lengths of the instances of gate regions / structures G0 and G1 included in word lines WL0 and WL1.

[0071] Thus, instances of gate regions / structures G2 / G4 and G3 / G5 included in word lines WL2 and WL3 also have staggered positions in the Y direction relative to instances of gate regions / structures G0 and G1 included in word lines WL0 and WL1, wherein instances of metal regions / segments WL1 and WL3 are aligned with each other in the X direction, and instances of metal regions / segments WL0 and WL2 are aligned with each other in the X direction.

[0072] IC device / layout diagram 600 is thus configured to include multiple instances of IC device / layout diagram 100, including gate regions / structures corresponding to a single word line electrical connection, which regions / structures have equal lengths and therefore have more uniform parasitic capacitance, resistance, and leakage characteristics than other approaches (e.g., approaches in which the lengths of gate regions / segments corresponding to a single word line electrical connection vary significantly).

[0073] Fig. 7A and Figure 7B 1 and 2 are schematic diagrams and plan views of an IC device / layout diagram 700 according to some embodiments. The IC device / layout diagram 700, also referred to as a ROM array 700 in some embodiments, includes the IC device / layout diagram 100 and the IC device / layout diagram 100 described above. Figure 1A-Figure 6 The X and Y directions of the discussion are shown for clarity. Figure 1A and Figure 1B The various features marked in are not marked.

[0074] IC device / layout 700 also includes a dummy array DA1 adjacent to IC device / layout 100 in the positive Y direction and a dummy array DA2 adjacent to IC device / layout 100 in the negative Y direction. Each of dummy arrays DA1 and DA2 includes two instances of active areas / regions corresponding to active areas / regions A0-A3 (not labeled for clarity), two instances of overlapping / overlapping metal regions / segments corresponding to bit lines BL0-BL3, and two instances of overlapping / overlapping source line VSS, each instance extending in the X direction between instances of dummy gate regions / structures D1 and D2 (not labeled for clarity), as described above with respect to FIG. Figure 1A-Figure 6 described.

[0075] The dummy array DA1 also includes an instance of gate region / structure G0 (not labeled for clarity) and corresponding metal region / segment WL0, a dummy gate region / structure D3, an extension of gate region / structure G2 and corresponding metal region / segment WL2, and an extension of gate region / structure G3. Fig. 7A and Figure 7B As shown, dummy array DA1 includes electrical connections between each S / D region / structure adjacent to each gate region / structure G0, G2 and G3 and a corresponding source line VSS (through instances of via regions / structures VD, labeled as single instances for clarity).

[0076] The dummy array DA2 also includes a dummy gate region / structure D4, an instance of gate region / structure G1 (not labeled for clarity) and corresponding metal region / segment WL1, an extension of gate region / segment G4, and gate region / segment G5 and an extension of corresponding metal region / segment WL3. Fig. 7A and Figure 7B As shown, dummy array DA2 includes electrical connections between each S / D region / structure adjacent to each gate region / structure G1, G4 and G5 and a corresponding source line VSS (through instances of via regions / structures VD, labeled as single instances for clarity).

[0077] exist Fig. 7A and Figure 7BIn the illustrated embodiment, for purposes of illustration, IC device / layout 700 includes a single instance of each of IC device / layout 100 (including all logical 0 ROM bits) and dummy arrays DA1 and DA2. In some embodiments, IC device / layout 700 includes multiple instances of one or more of IC device / layout 100 and / or dummy arrays DA1 and / or DA2. In some embodiments, IC device / layout 700 includes one or more instances of IC device / layout 100 that include one or more logical 1 ROM bits in addition to or as an alternative to logical 0 ROM bits, for example, as described above with respect to Figure 2A-Figure 5B discussed.

[0078] By including one or more instances of pseudo-arrays DA1 and / or DA2, the IC device / layout diagram 700 includes gate regions / structures corresponding to single word line electrical connections having equal lengths and terminations based on source line connections, thereby achieving the uniform parasitic capacitance, resistance, and leakage characteristics discussed above with respect to the IC device / layout diagram 600.

[0079] Figure 8 8 is a flow chart of a method 800 for manufacturing an IC device according to some embodiments. The method 800 may be operated to form the above-mentioned Figure 1A-Figure 7B Some or all of one or more of the IC devices 100-700 discussed.

[0080] In some embodiments, performing some or all of the operations of method 800 is performed by constructing a portion of multiple integrated circuit devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing multiple manufacturing operations (e.g., one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing multiple IC devices in a semiconductor wafer).

[0081] In some embodiments, the operations of method 800 are as follows: Figure 8 In some embodiments, the operations of method 800 are performed in the order shown. Figure 8 In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 800. In some embodiments, performing some or all of the operations of method 800 includes performing the following steps with respect to IC manufacturing system 1100 and Fig.11 The operation or operations being discussed.

[0082] At operation 802, first to fourth adjacent active regions are formed in a semiconductor substrate. In some embodiments, forming the first to fourth adjacent active regions includes forming Figure 1A-Figure 7B The active areas A0-A3 are discussed.

[0083] Forming the first to fourth adjacent active regions includes forming adjacent first to fourth active regions having a length in the first direction equal to five times the gate pitch, for example, a distance in the X direction equal to the distance in the X direction described above with respect to Figure 1A-Figure 7B Five times the gate pitch CPP discussed.

[0084] In some embodiments, forming the first to fourth adjacent active regions includes performing one or more deposition and / or implantation processes in regions of the semiconductor substrate corresponding to one or more instances of IC 100-700. In some embodiments, forming the first to fourth adjacent active regions includes forming S / D structures and / or MD segments, such as described above with respect to Figure 1A-Figure 7B The S / D structure SD and / or MD segment MD is discussed.

[0085] In some embodiments, forming the first to fourth adjacent active regions includes forming active regions other than the first to fourth active regions, for example, as described above with respect to Figure 6 The fifth to eighth active regions aligned with the first to fourth active regions in the X or Y direction, or as described above with respect to Fig. 7A and Figure 7B As described, the fifth to eighth active areas are configured according to the dummy arrays DA1 and / or DA2.

[0086] At operation 804, a plurality of gate structures are constructed on the first to fourth adjacent active regions. Constructing the plurality of gate structures includes constructing first and second dummy gate structures that are separated by five times the gate pitch and are located above the endpoints of the first to fourth adjacent active regions. In some embodiments, constructing the plurality of gate structures includes constructing the gate structures described above. Figure 1A-Figure 7B The dummy gate structures D1 and D2 are discussed.

[0087] In some embodiments, constructing the first and second dummy gate structures includes constructing one or more dummy gate structures in addition to the first and second dummy gate structures, for example, as described above with respect to Figure 6-7B described.

[0088] In some embodiments, constructing a plurality of gate structures includes constructing first to sixth gate electrodes on first to fourth active regions, for example, including gate structures G0-G5 on active regions A0-A3, as described above with respect to Figure 1A-Figure 7B In some embodiments, constructing the first to sixth gate electrodes includes forming an isolation structure adjacent to each of the first to sixth gate electrodes, such as the isolation structure described above. Figure 1A-Figure 7B An example of an isolation structure ISO is discussed.

[0089] In some embodiments, constructing the plurality of gate structures includes constructing one or more gate structures other than the gate structure including the first to sixth gate electrodes, for example, as described above with respect to Figure 6-7B described.

[0090] In some embodiments, constructing the plurality of gate structures includes performing a plurality of fabrication operations, such as one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing the plurality of gate structures, as described above with respect to Figure 1A-Figure 7B described.

[0091] At operation 806, in some embodiments, electrical connections are formed from the four gate electrodes to the first through fourth word lines of the ROM circuit. In some embodiments, forming the electrical connections includes forming the Figure 1A-Figure 7B Metal segments WL0 - WL3 of word lines WL0 - WL3 are discussed.

[0092] In some embodiments, forming an electrical connection, for example by performing operations 806 and / or 808, includes forming one or more via structures and / or metal segments by performing multiple manufacturing operations, the manufacturing operations including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form a continuous low resistance structure.

[0093] At operation 808, in some embodiments, electrical connections are formed from the first and / or second active regions adjacent to one of the gate electrodes to bit lines and source lines of the ROM circuit. In some embodiments, forming electrical connections from the first and / or second active regions includes forming electrical connections based on a ROM bit programming mode.

[0094] In some embodiments, forming electrical connections from the first and / or second active regions adjacent to one of the gate electrodes to the bit lines and source lines of the ROM circuit includes forming a via structure VD on an instance of the S / D structure SD to one or more of the bit lines BL0-BL15 and / or the source line VSS, as described above with respect to Figure 1A-Figure 7B described.

[0095] By performing some or all of the operations of method 800, an IC device is manufactured in which the ROM bit array includes four rows, each row including a total of four ROM bits extending between dummy gate structures, the extension distance corresponding to five times the gate pitch, thereby enabling the benefits discussed above with respect to IC devices 100-700 to be achieved.

[0096] Fig. 9 is a flowchart of a method 900 for generating an IC layout diagram according to some embodiments, for example, Figure 1A-Figure 7B One or more of the IC layout diagrams 100-700 are discussed.

[0097] In some embodiments, generating an IC layout diagram includes generating an IC device (eg, the IC device described above) manufactured based on the generated IC layout diagram. Figure 1A-Figure 7B FIG. 7 is an illustration of an IC layout corresponding to the IC devices 100 - 700 discussed above.

[0098] In some embodiments, some or all of method 900 is performed by a processor of a computer, for example, as described below with reference to Fig.10 The processor 1002 of the IC layout generation system 1000 is discussed.

[0099] Some or all of the operations of method 900 can be performed as in a design studio (e.g., see below). Fig.11 It is performed as part of a design process performed in the design studio 1120 discussed above.

[0100] In some embodiments, the operations of method 900 are as follows: Fig. 9 In some embodiments, the operations of method 900 are performed simultaneously and / or in a sequence similar to that shown in FIG. Fig. 9 In some embodiments, one or more operations of method 900 are performed before, between, during, and / or after one or more operations of method 900 are performed.

[0101] At operation 902, in the IC layout diagram, the first to fourth adjacent active regions are arranged between dummy gate regions, and the dummy gate regions are spaced five times the gate pitch. Figure 1A-Figure 7B As described, arranging the first to fourth adjacent active regions between the dummy gate regions includes arranging the active regions A0 - A3 between the dummy gate regions D1 and D2 separated by the five-fold pitch CPP.

[0102] In some embodiments, arranging the first to fourth adjacent active regions includes arranging active regions other than the first to fourth adjacent active regions, for example, as described above with respect to Figure 6-7B described.

[0103] At operation 904, the first to fourth gate regions are arranged between the dummy gate regions and intersect the first to fourth active regions. In some embodiments, arranging the first to fourth gate regions includes arranging the gate regions G0, G1, G2 / G4, and G3 / G5 between the dummy gate regions D1 and D2 and intersecting the active regions A0-A3, as described above with respect to Figure 1A-Figure 7B described.

[0104] In some embodiments, arranging the first to fourth gate regions includes intersecting the first to fourth gate regions with the cut gate region, such as described above with respect to Figure 1A-Figure 7B The cut gate region CG discussed.

[0105] In some embodiments, arranging the first to fourth gate regions includes arranging gate regions other than the first to fourth gate regions, for example, as described above with respect to Figure 6-7B described.

[0106] At operation 906, electrical connections from the four gate regions to the first to fourth word lines of the ROM circuit are configured in the IC layout. In some embodiments, configuring the electrical connections from the four gate regions to the first to fourth word lines includes configuring the metal regions WL0-WL4 and the via region VG as described above with respect to Figure 1A-Figure 7B described.

[0107] In some embodiments, configuring electrical connections from the four gate regions to the first to fourth word lines includes configuring electrical connections from one or more gate regions (other than the four gate regions) to the first to fourth word lines, for example, as described above with respect to Figure 6-7B described.

[0108] At operation 908, in some embodiments, electrical connections are configured in the IC layout from the first and / or second active regions adjacent to one of the gate regions to the bit lines and / or source lines of the ROM circuit. In some embodiments, configuring the electrical connections from the first and / or second active regions adjacent to one of the gate regions to the bit lines and / or source lines of the ROM circuit includes configuring instances of via regions VD from one or more S / D regions of active regions A0-A3 to one or more of bit lines BL0-BL15 and / or source line VSS, as described above with respect to Figure 1A-Figure 7B described.

[0109] In some embodiments, configuring electrical connections from the first and / or second active regions adjacent to one of the gate regions to the bit lines and / or source lines of the ROM circuit includes configuring electrical connections from one or more active regions other than the first and / or second active regions to the bit lines and / or source lines of the ROM circuit, for example, as described above with respect to Figure 2A-Figure 7B discussed.

[0110] In some embodiments, configuring electrical connections from the first and / or second active regions adjacent to one of the gate regions to a bit line and / or a source line of the ROM circuit includes performing a ROM programming operation.

[0111] At operation 910, in some embodiments, an IC layout diagram including first to fourth adjacent active regions and first to fourth gate regions is stored in a memory device. In some embodiments, storing the IC layout diagram in the memory device includes storing the IC layout diagram described above in connection with Figure 1A-Figure 7B One or more of the discussed IC layouts 100 - 700 are stored in a memory device.

[0112] In various embodiments, storing the IC layout in the memory device includes storing the IC layout in a non-volatile, computer-readable memory or a cell library, such as a database, and / or includes storing the IC layout over a network.

[0113] At operation 912, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout diagram. Figure 8 Combined with the following Fig.11 Performing one or more manufacturing operations, such as one or more photolithography exposures, based on the IC layout is discussed.

[0114] By performing some or all of the operations of method 900, an IC layout diagram corresponding to an IC device is generated, wherein the ROM bit array includes four rows, each row including a total of four ROM bits extending between dummy gate structures, and the extension distance corresponds to five times the gate pitch, thereby achieving the benefits discussed above with respect to IC devices 100-700.

[0115] Fig.10 is a block diagram of an IC layout generation system 1000 according to some embodiments. According to one or more embodiments, the method of designing an IC layout described herein may be implemented, for example, using the IC layout generation system 1000 according to some embodiments.

[0116] In some embodiments, IC layout generation system 1000 is a general purpose computing device including hardware processor 1002 and non-transitory computer readable storage medium 1004. Storage medium 1004 is encoded with, among other things, computer program code 1006, i.e., a set of executable instructions. Execution of instructions 1006 by hardware processor 1002 represents (at least in part) an electronic design automation (EDA) tool that implements part or all of the method, such as described above with respect to Fig. 9 A method 900 for generating an IC layout diagram (hereinafter referred to as the process and / or method) is described.

[0117] The processor 1002 is electrically coupled to the computer-readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an I / O interface 1010 via the bus 1008. The network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014 so that the processor 1002 and the computer-readable storage medium 1004 can be connected to external elements via the network 1014. The processor 1002 is configured to execute a computer program code 1006 encoded in the computer-readable storage medium 1004 so that the IC layout diagram generation system 1000 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0118] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1004 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0119] In one or more embodiments, the computer-readable storage medium 1004 stores computer program code 1006 configured to enable the IC layout diagram generation system 1000 (where such execution represents (at least in part) an EDA tool) to perform some or all of the processes and / or methods. In one or more embodiments, the computer-readable storage medium 1004 also stores information that facilitates the execution of some or all of the processes and / or methods.

[0120] In one or more embodiments, computer readable storage medium 1004 stores a cell library 1007 including cells disclosed herein, such as those described above with respect to Figure 1A-Figure 5B Discuss IC layouts 100-500.

[0121] In one or more embodiments, the computer readable storage medium 1004 stores a layout diagram 1009, including an IC layout diagram disclosed herein, such as the IC layout diagram disclosed above. Figure 6-7B The IC layouts discussed are shown in Figures 600 and 700 .

[0122] IC layout generation system 1000 includes an I / O interface 1010. I / O interface 1010 is coupled to external circuits. In one or more embodiments, I / O interface 1010 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to processor 1002.

[0123] The IC layout diagram generation system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more IC layout diagram generation systems 1000.

[0124] The IC layout generation system 1000 is configured to receive information through the I / O interface 1010. The information received through the I / O interface 1010 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 via the bus 1008. The IC layout generation system 1000 is configured to receive information related to the UI through the I / O interface 1010. The information is stored in the computer readable medium 1004 as a user interface (UI) 1042.

[0125] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the IC layout drawing generation system 1000. In some embodiments, the IC layout drawing generation system 1000 is implemented using a software application such as that available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0126] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROMs), RAMs, memory cards, etc. One or more.

[0127] Fig.11 1 is a block diagram of an IC manufacturing system 1100 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, the manufacturing system 1100 is used to manufacture at least one of the following based on the IC layout diagram: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0128] exist Fig.11 In the present invention, the IC manufacturing system 1100 includes entities that interact in the design, development and manufacturing cycles and / or services related to manufacturing IC devices 1160, such as a design room 1120, a mask room 1130, and an IC manufacturing plant / manufacturer ("Fab") 1150. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1120, the mask room 1130, and the IC manufacturing plant 1150 are owned by a single larger company. In some embodiments, two or more of the design room 1120, the mask room 1130, and the IC manufacturing plant 1150 coexist in a common facility and use common resources.

[0129] The design office (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns, such as Figure 1A-Figure 7BOne or more of the IC layout diagrams 100-700 discussed. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers of the various components that constitute the IC device 1160 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1122 includes various IC features, such as active areas, gate electrodes, source and drain, metal lines or vias for interlayer interconnection, and bonding pad openings formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room 1120 implements an appropriate design process to form the IC design layout diagram 1122. The design process includes one or more of logic design, physical design or layout and wiring. The IC design layout diagram 1122 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout diagram 1122 can be represented in a GDSII file format or a DFII file format.

[0130] The mask chamber 1130 includes data preparation 1132 and mask manufacturing 1144. The mask chamber 1130 uses the IC design layout drawing 1122 to manufacture one or more masks 1145 for manufacturing various layers of the IC device 1160 according to the IC design layout drawing 1122. The mask chamber 1130 performs mask data preparation 1132, wherein the IC design layout drawing 1122 is converted into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask manufacturing 1144. The mask manufacturing 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1145 or a semiconductor wafer 1153. The design layout drawing 1122 is manipulated by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 1150. In Fig.11 , mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0131] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0132] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout 1122 that has been processed by OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure that there are sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the constraints during mask fabrication 1144, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0133] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC), which simulates a process to be performed by the IC fabrication plant 1150 to fabricate the IC device 1160. The LPC simulates the process based on the IC design layout 1122 to create a simulated fabricated device, such as the IC device 1160. The processing parameters in the LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to the tools used to fabricate the IC, and / or other aspects of the fabrication process. The LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after the LPC creates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0134] It should be understood that the above description of mask data preparation 1132 has been simplified for the sake of clarity. In some embodiments, data preparation 1132 includes additional features, such as modifying the logic operations (LOPs) of IC design layout 1122 according to manufacturing rules. In addition, the processes applied to IC design layout 1122 during data preparation 1132 can be performed in a variety of different orders.

[0135] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 are manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more photolithography exposures based on the IC design layout 1122. In some embodiments, a pattern is formed on a mask (photomask or reticle) 1145 using an electron beam (e-beam) or a plurality of electron beams based on the modified IC design layout 1122. Mask 1145 can be formed using various techniques. In some embodiments, mask 1145 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) or EUV beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque area of ​​the binary mask. In another example, a mask 1145 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1145, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 1144 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1153, the mask is used in an etching process to form various etched regions in the semiconductor wafer 1153, and / or used in other suitable processes.

[0136] IC manufacturing plant 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1150 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end process BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0137] IC fabrication facility 1150 includes wafer fabrication tools 1152 configured to perform various fabrication operations on semiconductor wafer 1153 to fabricate IC devices 1160 based on masks (e.g., mask 1145). In various embodiments, fabrication tools 1152 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0138] IC manufacturing plant 1150 uses mask 1145 manufactured by mask chamber 1130 to manufacture IC device 1160. Therefore, IC manufacturing plant 1150 at least indirectly uses IC design layout 1122 to manufacture IC device 1160. In some embodiments, semiconductor wafer 1153 is manufactured by IC manufacturing plant 1150 using mask 1145 to form IC device 1160. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1122 at least indirectly. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0139] In some embodiments, the ROM array includes: first to fourth rows of ROM bits including corresponding adjacent first to fourth active regions, wherein each of the first to fourth rows of ROM bits includes a total of four adjacent ROM bits located along a corresponding one of the first to fourth active regions, each of the total four ROM bits of each ROM bit includes two source / drain (S / D) regions in the corresponding active region, and the three S / D regions of each row of ROM bits are shared by the four ROM bits. In some embodiments, the ROM array includes: a first gate electrode shared by a first ROM bit of each of the first to fourth rows of ROM bits; a second gate electrode shared by a second ROM bit of each of the first to fourth rows of ROM bits; a third gate electrode shared by a third ROM bit of each of the first and second rows of ROM bits; a fourth gate electrode shared by a fourth ROM bit of each of the first and second rows of ROM bits; a fifth gate electrode shared by a third ROM bit of each of the third and fourth rows of ROM bits; and a sixth gate electrode shared by a fourth ROM bit of each of the third and fourth rows of ROM bits. In some embodiments, each of the first to fourth active regions extends between a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure and the first to sixth gate electrodes are spaced apart according to a gate pitch, and the distance between the first dummy gate structure and the second dummy gate structure corresponds to five times the gate pitch. In some embodiments, the ROM array includes: a first isolation structure located between the third gate electrode and the fifth gate electrode; and a second isolation structure located between the fourth gate electrode and the sixth gate electrode. In some embodiments, the first gate electrode is exclusively electrically connected to the first word line through a first gate via located between the third active region and the fourth active region, the second gate electrode is exclusively electrically connected to the second word line through a second gate via located between the first active region and the second active region, the fifth gate electrode is exclusively electrically connected to the third word line through a third gate via located between the third active region and the fourth active region, and the sixth gate electrode is exclusively electrically connected to the fourth word line through a fourth gate via located between the first active region and the second active region.In some embodiments, the fifth to eighth rows of ROM bits include corresponding adjacent fifth to eighth active regions, wherein the fifth active region is adjacent to the fourth active region, each of the fifth to eighth rows of ROM bits includes a total of four adjacent ROM bits positioned along a corresponding one of the fifth active regions and the eighth active region, the fifth gate electrode is also shared by the third ROM bit in each of the fifth and sixth rows of ROM bits, and the sixth gate electrode is also shared by the fourth ROM bit in each of the fifth and sixth rows of ROM bits; the seventh gate electrode is shared by the first ROM bit in each of the fifth to eighth rows of ROM bits; the eighth gate electrode is shared by the second ROM bit in each of the fifth to eighth rows of ROM bits; the ninth gate electrode is shared by the third ROM bit in each of the seventh and eighth rows of ROM bits; and the tenth gate electrode is shared by the fourth ROM bit in each of the seventh and eighth rows of ROM bits. In some embodiments, the ROM array includes: a first row and a second row of pseudo ROM bits, including corresponding adjacent fifth and sixth active regions, wherein the fifth active region is adjacent to the fourth active region, each of the first row and the second row of pseudo ROM bits includes a total of three pseudo ROM bits positioned along a corresponding one of the fifth active region or the sixth active region, the fifth gate electrode is also shared by the second pseudo ROM bit of each of the first row and the second row of pseudo ROM bits, and the sixth gate electrode is also shared by the third pseudo ROM bit of each of the first row and the second row of pseudo ROM bits; and a seventh gate electrode, shared by the first pseudo ROM bit of each of the first row and the second row of pseudo ROM bits. In some embodiments, a ROM array includes fifth to eighth rows of ROM bits including respective adjacent fifth to eighth active regions aligned with respective first to fourth active regions, wherein each of the fifth to eighth rows of ROM bits includes a total of four adjacent ROM bits positioned along a respective one of the fifth to eighth active regions, each of the total of four ROM bits in each of the fifth to eighth rows of ROM bits includes two S / D regions in a respective active region, and three S / D regions in each of the fifth to eighth rows of ROM bits are shared by four ROM bits. In some embodiments, the ROM array includes: first to fourth bit lines and first to fourth source lines overlying the first to fourth rows of corresponding ROM bits, wherein at least one ROM bit of the four ROM bits in the first to fourth rows of ROM bits includes: a first via extending from one of two S / D regions to a corresponding one of the first to fourth bit lines; and a second via extending from the other of the two S / D regions to a corresponding one of the first to fourth source lines.

[0140] In some embodiments, the IC device includes: adjacent first to fourth active regions extending between a first dummy gate structure and a second dummy gate structure; a first gate electrode extending through each of the first to fourth active regions and offset by a gate pitch from the first dummy gate structure; a second gate electrode extending through each of the first to fourth active regions and offset by a gate pitch from the first gate electrode; a third gate electrode extending through each of the first and second active regions and offset by a gate pitch from the second gate electrode; a fourth gate electrode extending through each of the first and second active regions and offset by a gate pitch from the third gate electrode and each of the second dummy gate structures; a fifth gate electrode extending through each of the third and fourth active regions, offset by a gate pitch from the second gate electrode, and separated from the third gate electrode by a first isolation structure; and a sixth gate electrode extending through each of the third and fourth active regions, offset by a gate pitch from the fifth gate electrode and each of the second dummy gate structures, and separated from the fourth gate electrode by a second isolation structure. In some embodiments, the IC device includes: a first metal segment located in the first metal layer between the third active area and the fourth active area, and electrically connected to the first gate electrode through a first gate via; a second metal segment located in the first metal layer between the third active area and the fourth active area, and electrically connected to the fifth gate electrode through a second gate via; a third metal segment located in the first metal layer between the first active area and the second active area, and electrically connected to the second gate electrode through a third gate via; and a fourth metal segment located in the first metal layer between the first active area and the second active area, and electrically connected to the fourth gate electrode through a fourth gate via.In some embodiments, the IC device includes: adjacent fifth to eighth active regions extending between the first dummy gate structure and the second dummy gate structure, wherein the fifth active region is adjacent to the fourth active region, and each of the fifth gate electrode and the sixth gate electrode extends through the fifth active region and the sixth active region; a seventh gate electrode extending through each of the fifth to the eighth active regions, aligned with the first gate electrode, and separated from the first gate electrode by a third isolation structure; an eighth gate electrode extending through each of the fifth to the eighth active regions, aligned with the second gate electrode, and separated from the second gate electrode by a fourth isolation structure; a ninth gate electrode extending through each of the seventh and the eighth active regions, aligned with the fifth gate electrode, and separated from the fifth gate electrode by a fifth isolation structure; a tenth gate electrode extending through through each of the seventh active area and the eighth active area, aligned with the sixth gate electrode, and separated from the sixth gate electrode by the sixth isolation structure; a fifth metal segment, located between the seventh active area and the eighth active area in the first metal layer, and electrically connected to the first metal segment and the seventh gate electrode through the fifth gate via; a sixth metal segment, located between the seventh active area and the eighth active area in the first metal layer, and electrically connected to the second metal segment and the ninth gate electrode through the sixth gate via; a seventh metal segment, located between the fifth active area and the sixth active area in the first metal layer, and electrically connected to the third metal segment and the eighth gate electrode through the seventh gate via; and an eighth metal segment, located between the fifth active area and the sixth active area in the first metal layer, and electrically connected to the fourth metal segment and the sixth gate electrode through the eighth gate via. In some embodiments, the IC device includes: adjacent fifth and sixth active regions extending between a first dummy gate structure and a second dummy gate structure, wherein the fifth active region is adjacent to the fourth active region, and each of a fifth gate electrode and a sixth gate electrode extends through the fifth and sixth active regions; a third dummy gate structure extending through each of the fifth and sixth active regions and aligned with the first gate electrode; a seventh gate electrode extending through each of the fifth and sixth active regions, aligned with the second gate electrode, and separated from the second gate electrode by a third isolation structure; a fifth metal segment located between the fifth and sixth active regions in the first metal layer, and electrically connected to the third metal segment and the seventh gate electrode through the fifth gate via; the sixth metal segment, located between the fifth active area and the sixth active area in the first metal layer, and electrically connected to the fourth metal segment and the sixth gate electrode through the sixth gate via; the first source line and the second source line, located in the first metal layer, overlying the corresponding fifth active area and the sixth active area; the first via to the fourth via, extending from the first source line to the fifth active area adjacent to each of the second gate electrode, the fifth gate electrode and the sixth gate electrode; and the fifth via to the eighth via, extending from the second source line to the sixth active area adjacent to each of the second gate electrode, the fifth gate electrode and the sixth gate electrode.In some embodiments, the IC device includes: adjacent fifth to eighth active regions extending between the third dummy gate structure and the fourth dummy gate structure and aligned with the corresponding first to fourth active regions; a seventh gate electrode extending through each of the fifth to eighth active regions and offset from the third dummy gate structure by a gate pitch; an eighth gate electrode extending through each of the fifth to eighth active regions and offset from the seventh gate electrode by a gate pitch; a ninth gate electrode extending through each of the fifth and sixth active regions and offset from the eighth gate electrode by a gate pitch; a gate pitch; a tenth gate electrode extending through each of the fifth active region and the sixth active region, and offset by a gate pitch from the ninth gate electrode and each of the fourth dummy gate structures; an eleventh gate electrode extending through each of the seventh active region and the eighth active region, offset by a gate pitch from the eighth gate electrode, and separated from the ninth gate electrode by a third isolation structure; and a twelfth gate electrode extending through each of the seventh active region and the eighth active region, offset by a gate pitch from the eleventh gate electrode and each of the fourth dummy gate structures, and separated from the tenth gate electrode by a fourth isolation structure. In some embodiments, the IC device includes: a first bit line to a fourth bit line and a first source line to a fourth source line, located in a first metal layer and overlying corresponding first to fourth active areas; a first through-hole extending from one of the first to fourth bit lines to a corresponding one of the first to fourth active areas adjacent to a first side of one of the first to sixth gate electrodes; and a second through-hole extending from a corresponding one of the first to fourth source lines to a corresponding one of the first to fourth active areas adjacent to a second side of one of the first to sixth gate electrodes.

[0141] In some embodiments, a method for manufacturing an IC device includes: forming adjacent first to fourth active regions in a semiconductor substrate; and constructing a plurality of gate structures, the constructing the plurality of gate structures including: constructing a first dummy gate structure and a second dummy gate structure above an end point of each of the first to fourth active regions; constructing a first gate structure offset from the first dummy gate structure by a gate pitch, constructing the first gate structure including forming a first gate electrode extending above the first to fourth active regions; constructing a second gate structure offset from the first gate structure by a gate pitch, constructing the second gate structure including forming a second gate electrode extending above the first to fourth active regions; constructing A third gate structure having a gate pitch offset from the second gate electrode, wherein the third gate structure is constructed by: forming a third gate electrode extending above the first active area and the second active area; forming a fourth gate electrode extending above the third active area and the fourth active area; and forming a first isolation structure between the third gate electrode and the fourth gate electrode; and constructing a fourth gate structure having a gate pitch offset from each of the third gate structure and the second dummy gate structure, wherein the fourth gate structure is constructed by: forming a fifth gate electrode extending above the first active area and the second active area; forming a sixth gate electrode extending above the third active area and the fourth active area; and forming a second isolation structure between the fifth gate electrode and the sixth gate electrode. In some embodiments, forming adjacent first to fourth active regions includes forming adjacent fifth to eighth active regions adjacent to the fourth active region in the semiconductor substrate, constructing first dummy gate structures and second dummy gate structures includes constructing first dummy gate structures and second dummy gate structures over endpoints of each of the fifth to eighth active regions, constructing the first gate structure also includes forming a seventh gate electrode extending over the fifth to eighth active regions and a third isolation structure between the first gate electrode and the seventh gate electrode, constructing the second gate structure also includes forming a seventh gate electrode extending over the fifth to eighth active regions. an eighth gate electrode and a fourth isolation structure between the second gate electrode and the eighth gate electrode, constructing the third gate structure also includes: forming a fourth gate electrode further extending on the fifth active area and the sixth active area; forming a ninth gate electrode extending on the seventh active area and the eighth active area; and forming a fourth isolation structure between the fourth gate electrode and the ninth gate electrode, and constructing the fourth gate structure also includes: forming a sixth gate electrode further extending above the fifth active area and the sixth active area; forming a tenth gate electrode extending above the seventh active area and the eighth active area; and forming a fifth isolation structure between the sixth gate electrode and the tenth gate electrode.In some embodiments, forming adjacent first to fourth active regions includes forming adjacent fifth and sixth active regions adjacent to the fourth active region in the semiconductor substrate, constructing a first dummy gate structure and a second dummy gate structure includes constructing a first dummy gate structure and a second dummy gate structure above an endpoint of each of the fifth and sixth active regions, constructing the first gate structure also includes forming a third dummy gate structure extending above the fifth and sixth active regions, constructing the second gate structure also includes forming a seventh gate electrode extending above the fifth and sixth active regions, and forming a third isolation structure between the second gate electrode and the seventh gate electrode, constructing the third gate structure also includes forming a fourth gate electrode further extending above the fifth and sixth active regions, and constructing the fourth gate structure also includes forming a sixth gate electrode further extending above the fifth and sixth active regions. In some embodiments, the method includes: forming an electrical connector, the electrical connector including: a first dedicated electrical connector from a first gate electrode to a first word line of a read-only memory (ROM) circuit; a second dedicated electrical connector from a second gate electrode to a second word line of the ROM circuit; a third dedicated electrical connector from a fourth gate electrode to a third word line of the ROM circuit; and a fourth dedicated electrical connector from a fifth gate electrode to a fourth word line of the ROM circuit. In some embodiments, the method includes forming an electrical connector, the electrical connector including: a first through hole located on a first region of one of the first to fourth active regions, adjacent to a first side of one of the first to sixth gate electrodes; a second through hole located on a second region of one of the first to fourth active regions, adjacent to a second side of one of the first to sixth gate electrodes; a first electrical connector from the first through hole to a bit line of the read-only memory (ROM) circuit; and a second electrical connector from the second through hole to a source line of the ROM circuit.

[0142] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A read-only memory array, comprising: The first to fourth rows of read-only memory bits include corresponding adjacent first to fourth active regions, in, each of the first to fourth rows of read-only memory bits includes a total of four adjacent read-only memory bits located along a corresponding one of the first to fourth active regions, Each of the four total ROM bits includes two source / drain regions in a corresponding active region, and The three source / drain regions of each row of ROM bits are shared by four ROM bits.

2. The read-only memory array according to claim 1 , further comprising: a first gate electrode shared by a first ROM bit in each of the first to fourth rows of ROM bits; a second gate electrode shared by a second ROM bit in each of the first to fourth rows of ROM bits; a third gate electrode shared by a third ROM bit in each of the first and second rows of ROM bits; a fourth gate electrode shared by a fourth ROM bit in each of the first and second rows of ROM bits; a fifth gate electrode shared by the third row of ROM bits and the third ROM bit in each of the fourth row; and A sixth gate electrode is shared by a fourth ROM bit in each of the third and fourth rows of ROM bits.

3. The read-only memory array according to claim 2, wherein: Each of the first to fourth active regions extends between a first dummy gate structure and a second dummy gate structure, The first dummy gate structure and the second dummy gate structure and the first to sixth gate electrodes are spaced apart according to a gate pitch, and A distance between the first dummy gate structure and the second dummy gate structure corresponds to five times the gate pitch.

4. The read-only memory array according to claim 2, wherein: The first gate electrode is exclusively electrically connected to the first word line through a first gate through hole located between the third active area and the fourth active area, The second gate electrode is exclusively electrically connected to a second word line through a second gate through hole located between the first active region and the second active region, The fifth gate electrode is exclusively electrically connected to a third word line through a third gate through hole located between the third active region and the fourth active region, and The sixth gate electrode is exclusively electrically connected to a fourth word line through a fourth gate via located between the first active region and the second active region.

5. The read-only memory array according to claim 2, further comprising: The fifth to eighth rows of read-only memory bits include corresponding adjacent fifth to eighth active regions, wherein: The fifth active region is adjacent to the fourth active region, each of the fifth to eighth rows of read-only memory bits includes a total of four adjacent read-only memory bits positioned along a corresponding one of the fifth active region and the eighth active region, The fifth gate electrode is also shared by the third ROM bit in each of the fifth and sixth rows of ROM bits, and The sixth gate electrode is also shared by the fourth ROM bit of each of the fifth and sixth rows of ROM bits; a seventh gate electrode shared by a first ROM bit in each of the fifth to eighth rows of ROM bits; an eighth gate electrode shared by a second ROM bit in each of the fifth to eighth rows of ROM bits; a ninth gate electrode shared by a third ROM bit in each of the seventh and eighth rows of ROM bits; and A tenth gate electrode is shared by the fourth ROM bit in each of the seventh and eighth rows of ROM bits.

6. The read-only memory array according to claim 2, further comprising: The first row and the second row of pseudo read-only memory bits include corresponding adjacent fifth active regions and sixth active regions, wherein The fifth active region is adjacent to the fourth active region, each of the first row and the second row of dummy read-only memory bits includes a total of three dummy read-only memory bits located along a respective one of the fifth active region or the sixth active region, The fifth gate electrode is also shared by a second pseudo ROM bit in each of the first and second rows of pseudo ROM bits, and the sixth gate electrode is also shared by a third dummy ROM bit of each of the first and second rows of dummy ROM bits; and A seventh gate electrode is shared by the first pseudo ROM bits in each of the first and second rows of pseudo ROM bits.

7. An integrated circuit device comprising: The adjacent first active region to the fourth active region extend between the first dummy gate structure and the second dummy gate structure; a first gate electrode extending through the first active region to each of the fourth active regions and offset from the first dummy gate structure by a gate pitch; a second gate electrode extending through the first active region to each of the fourth active regions and offset from the first gate electrode by the gate pitch; a third gate electrode extending through each of the first active region and the second active region and offset from the second gate electrode by the gate pitch; a fourth gate electrode extending through each of the first active region and the second active region and offset from each of the third gate electrode and the second dummy gate structure by the gate pitch; a fifth gate electrode extending through each of the third active region and the fourth active region, offset from the second gate electrode by the gate pitch, and separated from the third gate electrode by a first isolation structure; as well as A sixth gate electrode extends through each of the third active region and the fourth active region, is offset from each of the fifth gate electrode and the second dummy gate structure by the gate pitch, and is separated from the fourth gate electrode by a second isolation structure.

8. The integrated circuit device according to claim 7, further comprising: a first metal segment located in the first metal layer between the third active region and the fourth active region and electrically connected to the first gate electrode through a first gate via; a second metal segment located in the first metal layer between the third active area and the fourth active area and electrically connected to the fifth gate electrode through a second gate via; a third metal segment located in the first metal layer between the first active area and the second active area and electrically connected to the second gate electrode through a third gate via; as well as A fourth metal segment is located in the first metal layer between the first active area and the second active area and is electrically connected to the fourth gate electrode through a fourth gate via.

9. The integrated circuit device according to claim 8, further comprising: The adjacent fifth active region to the eighth active region extend between the first dummy gate structure and the second dummy gate structure, wherein The fifth active region is adjacent to the fourth active region, and Each of the fifth gate electrode and the sixth gate electrode extends through the fifth active region and the sixth active region; a seventh gate electrode extending through the fifth active region to each of the eighth active regions, aligned with the first gate electrode, and separated from the first gate electrode by a third isolation structure; an eighth gate electrode extending through the fifth active region to each of the eighth active regions, aligned with the second gate electrode, and separated from the second gate electrode by a fourth isolation structure; a ninth gate electrode extending through each of the seventh active region and the eighth active region, aligned with the fifth gate electrode, and separated from the fifth gate electrode by a fifth isolation structure; a tenth gate electrode extending through each of the seventh active region and the eighth active region, aligned with the sixth gate electrode, and separated from the sixth gate electrode by a sixth isolation structure; a fifth metal segment located in the first metal layer between the seventh active region and the eighth active region and electrically connected to the first metal segment and the seventh gate electrode through a fifth gate via; a sixth metal segment located in the first metal layer between the seventh active region and the eighth active region and electrically connected to the second metal segment and the ninth gate electrode through a sixth gate via; a seventh metal segment, located in the first metal layer between the fifth active region and the sixth active region, and electrically connected to the third metal segment and the eighth gate electrode through a seventh gate via; as well as An eighth metal segment is located in the first metal layer between the fifth active region and the sixth active region and is electrically connected to the fourth metal segment and the sixth gate electrode through an eighth gate via.

10. A method of manufacturing an integrated circuit device, the method comprising: forming adjacent first to fourth active regions in a semiconductor substrate; as well as Constructing a plurality of gate structures, wherein constructing the plurality of gate structures comprises: constructing a first dummy gate structure and a second dummy gate structure over an end point of each of the first active region to the fourth active region; Constructing a first gate structure having a gate pitch offset from the first dummy gate structure, wherein constructing the first gate structure includes forming a first gate electrode extending above the first active region to the fourth active region; Constructing a second gate structure offset from the first gate structure by the gate pitch, wherein constructing the second gate structure includes forming a second gate electrode extending above the first active region to the fourth active region; Constructing a third gate structure that is offset from the second gate electrode by the gate pitch, wherein constructing the third gate structure comprises: forming a third gate electrode extending over the first active region and the second active region; forming a fourth gate electrode extending over the third active region and the fourth active region; and forming a first isolation structure between the third gate electrode and the fourth gate electrode; and Constructing a fourth gate structure that is offset from each of the third gate structure and the second dummy gate structure by the gate pitch, wherein constructing the fourth gate structure comprises: forming a fifth gate electrode extending over the first active region and the second active region; forming a sixth gate electrode extending over the third active region and the fourth active region; and A second isolation structure is formed between the fifth gate electrode and the sixth gate electrode.

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