Nonvolatile memory device and electronic system including the same

Abstract

A nonvolatile memory device and an electronic system including the same are provided. The nonvolatile memory device includes a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region; a molding structure including a plurality of gate electrodes stacked in a step pattern in the pad region; a trench on the pad region along a contour of the molded structure, the trench including a bottom surface having a stepped shape and a first sidewall on a boundary between the pad region and the wall region; a liner film on a first sidewall of the trench; a recess in the trench and exposing a pad portion of the gate electrode; a unit contact disposed at the recess and connected with the pad portion; and a cover insulating layer disposed at the trench. The liner film has a different etching selectivity with respect to the cover insulating layer.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0135450 filed on October 11, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a nonvolatile memory device and an electronic system including the nonvolatile memory device. Background Art

[0003] In order to meet the consumer's demand for high performance and low price, it is expected to improve the integration of non-volatile memory devices. In particular, since the integration of non-volatile memory devices is an important factor determining product prices, it is necessary to increase the integration of non-volatile memory devices.

[0004] The integration degree of a two-dimensional (2D) nonvolatile memory device or a planar nonvolatile memory device is mainly determined by the area of ​​the memory cell unit and is therefore greatly affected by the level of micropatterning technology. However, because expensive equipment is required to miniaturize the pattern, the integration degree of 2D nonvolatile memory devices, although increasing, is still limited. Therefore, a three-dimensional (3D) nonvolatile memory device including memory cells arranged three-dimensionally has been proposed. Summary of the invention

[0005] The present disclosure relates to a nonvolatile memory device with reduced manufacturing process difficulty, an electronic system with reduced manufacturing process difficulty, a nonvolatile memory device capable of improving device performance and reliability, and an electronic system capable of improving device performance and reliability.

[0006] The present disclosure is not limited to the above-mentioned contents, and those skilled in the art will clearly understand the present disclosure from the following description.

[0007] In some embodiments, a nonvolatile memory device includes: a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers sequentially stacked on the substrate, the plurality of gate electrodes being stacked on a pad region of the connection region in a staircase pattern, and the plurality of mold insulating layers being alternately stacked with the plurality of gate electrodes; a channel structure on the first cell region and the second cell region, the channel structure penetrating the mold structure and intersecting the plurality of gate electrodes; a groove on the pad region of the connection region along a contour of the mold structure, the groove including a bottom surface having a staircase shape and a first sidewall located on a boundary between the pad region of the connection structure and a wall region of the connection structure; a liner film on the first sidewall of the groove; a recess in the groove and exposing a pad portion of one of the plurality of gate electrodes and the liner film on the first sidewall of the groove; a cell contact filling the recess and connected to the pad portion of the one gate electrode; and a capping insulating layer filling the trench, wherein the liner film has an etching selectivity different from that of the capping insulating layer.

[0008] In some embodiments, a nonvolatile memory device includes: a peripheral circuit substrate; a peripheral circuit device on the peripheral circuit substrate; a cell substrate on the peripheral circuit substrate and including a first cell region, a second cell region separated from the first cell region in a first horizontal direction, and a connection region between the first cell region and the second cell region, the connection region including a pad region and a wall region arranged in a second horizontal direction intersecting the first horizontal direction; a molding structure including a plurality of gate electrodes stacked in a staircase pattern on the pad region of the connection region and a plurality of molding insulating layers alternately stacked with the plurality of gate electrodes, and the molding structure including a wall structure on the wall region of the connection region; a channel structure in the first cell region; The invention relates to a first cell region, a cell contact, a first cell contact having a first sidewall on a sidewall of the wall structure and connected to a pad portion of one of the plurality of gate electrodes, and a first portion extending in a first horizontal direction on the first sidewall of the cell contact; a covering insulating layer, a second sidewall of the cell contact opposite to the first sidewall of the cell contact, and a dam structure between the second sidewall of the cell contact and the covering insulating layer, wherein the liner film contacts the first sidewall of the cell contact and the dam structure has an etching selectivity different from that of the covering insulating layer.

[0009] In some embodiments, an electronic system includes a main substrate, a nonvolatile memory device on the main substrate, and a controller on the main substrate, wherein the controller is electrically connected to the nonvolatile memory device, wherein the nonvolatile memory device includes: a unit substrate including a first unit region, a second unit region, and a connection region between the first unit region and the second unit region; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers sequentially stacked on the unit substrate, wherein the plurality of gate electrodes are stacked on a pad region of the connection region in a staircase pattern, and the plurality of mold insulating layers are alternately stacked with the plurality of gate electrodes; and a channel structure, on the first unit region and the second unit region, the channel structure penetrating the mold structure and being in contact with the The multiple gate electrodes are crossed; a cell contact, on the pad area of ​​the connection area, the cell contact includes a bottom surface and a first side wall, the first side wall is located on the boundary between the pad area of ​​the connection area and the wall area of ​​the connection area, and the bottom surface is connected to the pad portion of one of the multiple gate electrodes; a liner film, including a first portion arranged on the first side wall of the cell contact; a covering insulating layer, on the pad area of ​​the connection area, the covering insulating layer surrounds a second side wall of the cell contact opposite to the first side wall of the cell contact; and a dam structure, located between the second side wall of the cell contact and the covering insulating layer, wherein the liner film contacts the first side wall of the cell contact, and the liner film has an etching selectivity different from that of the covering insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram of an example of a nonvolatile memory device.

[0012] Figure 2 is an equivalent circuit diagram of a memory cell array which is an example of a nonvolatile memory device.

[0013] Figure 3 is a perspective view of a representative configuration of an example of a nonvolatile memory device.

[0014] Figure 4 yes Figure 3 An example plan view of a non-volatile memory device.

[0015] Figure 5 It is along Figure 4 An example cross-sectional view taken along line X1-X1' in FIG.

[0016] Figure 6 It is along Figure 4 An example cross-sectional view taken along line Y1-Y1' in FIG.

[0017] Figure 7 It is along Figure 4An example cross-sectional view taken along line Y2-Y2' in FIG.

[0018] Figure 8 yes Figure 7 Example enlarged view of area EX1 in FIG.

[0019] Fig.9A , Fig. 9B and Fig. 9C is an example cross-sectional view of a nonvolatile memory device.

[0020] Fig.10 , Fig.11 , Fig.12 and Fig.13 is an example plan view of a nonvolatile memory device.

[0021] Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A and Fig.21B is a cross-sectional view illustrating an example of a method of manufacturing a nonvolatile memory device.

[0022] Fig. 22 is a schematic diagram of an example of a data storage system including a non-volatile memory device.

[0023] Fig.23 is a schematic perspective view of an example of a data storage system including a non-volatile memory device.

[0024] Fig.24 is a schematic cross-sectional view of an example of a semiconductor package. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of an example of a nonvolatile memory device 10 .

[0027] Reference Figure 1, the nonvolatile memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of memory cell blocks, for example, a first memory cell block BLK1 to an nth memory cell block BLKn. Each of the first memory cell block BLK1 to the nth memory cell block BLKn may include a plurality of memory cells. The first memory cell block BLK1 to the nth memory cell block BLKn may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, a string selection line SSL, and a ground selection line GSL.

[0028] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, and control logic 38. Although not shown in FIG. Figure 1 Although not shown in FIG. 1 , the peripheral circuit 30 may also include an I / O interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, and the like.

[0029] The memory cell array 20 may be connected to the page buffer 34 through the bit lines BL and connected to the row decoder 32 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. The memory cells included in the first to nth memory cell blocks BLK1 to BLKn of the memory cell array 20 may include flash memory cells, respectively. The memory cell array 20 may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells, respectively connected to a plurality of word lines WL vertically stacked on a substrate.

[0030] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the nonvolatile memory device 10 , and may exchange data with a device outside the nonvolatile memory device 10 .

[0031] In response to the address ADDR, the row decoder 32 may select at least one of the first to nth memory cell blocks BLK1 to BLKn, and may select a word line WL, a string selection line SSL, and a ground selection line GSL of the selected memory cell block. The row decoder 32 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0032] The page buffer 34 may be connected to the memory cell array 20 through the bit line BL. In a program operation, the page buffer 34 may operate as a write driver and may apply a voltage corresponding to data to be stored in the memory cell array 20 to the bit line BL. In a read operation, the page buffer 34 may operate as a sense amplifier and sense data stored in the memory cell array 20. The page buffer 34 may operate according to a control signal PCTL provided from the control logic 38.

[0033] The data I / O circuit 36 ​​may be connected to the page buffer 34 through the data lines DLs. In a program operation, the data I / O circuit 36 ​​may receive program data from the memory controller and provide the program data to the page buffer 34 based on the column address C_ADDR provided from the control logic 38. In a read operation, the data I / O circuit 36 ​​may provide read data stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38.

[0034] The data I / O circuit 36 ​​may send an address or a command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0035] The control logic 38 may receive a command CMD and a control signal CTRL from a memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data I / O circuit 36. The control logic 38 may generate various internal control signals used in the nonvolatile memory device 10 in response to the control signal CTRL. For example, the control logic 38 may adjust the voltage levels applied to the word lines WL and the bit lines BL in a memory operation such as a program operation or an erase operation.

[0036] Figure 2 is an equivalent circuit diagram of an example memory cell array of the nonvolatile memory device 10 .

[0037] Reference Figure 2 , the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (or bit lines BL1 to BLm), a plurality of word lines WL (or word lines WL1 to WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The memory cell string MS may be between the common source line CSL and the bit line BL. Although Figure 2 , each memory cell string MS includes two string selection lines SSL, but the present disclosure is not limited thereto. For example, each memory cell string MS may include one string selection line SSL.

[0038] Each memory cell string MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1 to MCn. The drain region of the string selection transistor SST may be connected to a bit line BL corresponding to the string selection transistor SST among the bit lines BL, and the source region of the ground selection transistor GST may be connected to a common source line CSL. The corresponding source regions of the plurality of ground selection transistors GST may be commonly connected to the common source line CSL.

[0039] The string selection transistor SST may be connected to a string selection line SSL, and the ground selection transistor GST may be connected to a ground selection line GSL. The memory cell transistors MC1 to MCn may be connected to word lines WL1 to WLn, respectively.

[0040] Figures 3 to 8 1 is an exemplary diagram for describing the nonvolatile memory device 100. Specifically, Figure 3 is a perspective view of a representative configuration of an example of the nonvolatile memory device 100 . Figure 4 yes Figure 3 FIG. 1 is a plan view of an example of a nonvolatile memory device 100 . Figure 5 It is along Figure 4 An example cross-sectional view taken along line X1-X1' in FIG. Figure 6 It is along Figure 4 An example cross-sectional view taken along line Y1-Y1' in FIG. Figure 7 It is along Figure 4 An example cross-sectional view taken along line Y2-Y2' in FIG. Figure 8 yes Figure 7 Example enlarged view of area EX1 in FIG.

[0041] Reference Figures 3 to 7 , the nonvolatile memory device 100 may include a cell array structure CS and a peripheral circuit structure PS stacked on each other in a vertical direction (Z direction). The cell array structure CS may include a reference Figure 1 The memory cell array 20 described above, the peripheral circuit structure PS may include reference Figure 1 The peripheral circuit 30 is described.

[0042] The cell array structure CS may include first to n-th memory cell blocks BLK1 to BLKn. Each of the first to n-th memory cell blocks BLK1 to BLKn may include three-dimensionally arranged memory cells.

[0043] The substrate 50 may include a first cell region MCR1, a connection region CON, and a second cell region MCR2 arranged horizontally. Specifically, the first cell region MCR1, the connection region CON, and the second cell region MCR2 may be arranged in a first horizontal direction (X direction). The first cell region MCR1 may be separated from the second cell region MCR2 by the connection region CON in the first horizontal direction (X direction). The connection region CON may include a pad area PR and a wall area WR arranged in a second horizontal direction (Y direction). In some embodiments, a memory cell block (e.g., a first memory cell block BLK1) may include a pad area PR and a wall area WR between the first cell region MCR1 and the second cell region MCR2.

[0044] In some embodiments, the corresponding pad regions PR of two adjacent memory cell blocks may be adjacent to each other. Specifically, the pad region PR of the first memory cell block BLK1 and the pad region PR of the second memory cell block BLK2 may be adjacent to each other in the second horizontal direction (Y direction). In some embodiments, the trenches TR in the corresponding pad regions PR of the two adjacent memory cell blocks may be adjacent to each other. For example, the trench TR of the first memory cell block BLK1 may be adjacent to the trench TR of the second memory cell block BLK2 in the second horizontal direction (Y direction).

[0045] The substrate 50 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In some embodiments, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0046] The peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 on a substrate 50. An active region may be defined in the substrate 50 by an isolation film 52. A plurality of peripheral circuit transistors 60TR may be on the active region. Each peripheral circuit transistor 60TR may include a peripheral circuit gate 60G and a source / drain region in a portion of the substrate 50, the source / drain region being at each of the opposite sides of the peripheral circuit gate 60G.

[0047] The peripheral circuit wiring structure 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. An interlayer insulating film 80 may be on the substrate 50 and may cover the peripheral circuit transistor 60TR and the peripheral circuit wiring structure 70. The peripheral circuit wiring layer 74 may have a multi-layer structure including a plurality of metal layers at different vertical levels (or vertical heights).

[0048] The common source plate 110 may be disposed on the interlayer insulating film 80. In some embodiments, the common source plate 110 may be used as a source region for supplying current to vertical memory cells formed in the cell array structure CS. The common source plate 110 may be disposed across the first cell region MCR1, the connection region CON, and the second cell region MCR2 of the substrate 50.

[0049] In some embodiments, the common source plate 110 may include at least one selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The common source plate 110 may include a semiconductor doped with n-type impurities. The common source plate 110 may also have a crystalline structure including at least one selected from the group consisting of a single crystal structure, an amorphous structure, and a polycrystalline structure. In some embodiments, the common source plate 110 may include polycrystalline silicon doped with n-type impurities.

[0050] A mold structure ST in which a plurality of gate electrodes 130 and a plurality of mold insulating layers 132 are alternately arranged in a vertical direction (Z direction) may be located on the common source plate 110 in the first cell region MCR1 , the connection region CON, and the second cell region MCR2 .

[0051] The mold structure ST may include a wall structure ST_W in which gate electrodes 130 and mold insulating layers 132 are alternately arranged in the wall region WR of the connection region CON. The mold structure ST may include gate electrodes 130 and mold insulating layers 132 alternately arranged in a stair pattern on the pad region PR of the connection region CON.

[0052] Reference Figure 8 Each gate electrode 130 may include a buried conductive layer 130A and a conductive barrier layer 130B surrounding the top surface, bottom surface, and side surface of the buried conductive layer 130A. For example, the buried conductive layer 130A may include: a metal (such as tungsten, nickel, cobalt, or tantalum); a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide); doped polysilicon; or a combination thereof. In some embodiments, the conductive barrier layer 130B may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0053] In some embodiments, the gate electrodes 130 may be connected to the memory cell strings MS (see Figure 2), a ground selection line GSL, a word line WL or WL1 to WLn, and at least one string selection line SSL. For example, the bottom gate electrode 130 may be used as a ground selection line GSL, the top two gate electrodes 130 may be used as string selection lines SSL, and the remaining gate electrodes 130 may be used as word lines WL, respectively. Therefore, a memory cell string MS may be provided, in which a ground selection transistor GST, a string selection transistor SST, and memory cell transistors MC1 to MCn therebetween are connected in series with each other. In some embodiments, at least one of the gate electrodes 130 may be used as a dummy word line, but is not limited thereto.

[0054] like Figure 4 and Figure 7 As shown in , a plurality of gate stack isolation openings WLH may extend on the common source plate 110 in a first horizontal direction (X direction) parallel to the top surface of the common source plate 110. A plurality of gate electrodes 130 between two adjacent gate stack isolation openings WLH may form a single memory cell block. For example, Figure 4 A first memory cell block BLK1 and a second memory cell block BLK2 are shown in FIG.

[0055] The gate stack isolation insulating layer WLI may be in each gate stack isolation opening WLH on the common source plate 110. The gate stack isolation insulating layer WLI may include a silicon oxide film, a silicon nitride film, SiON, SiOCN, SiCN, or a combination thereof.

[0056] A plurality of channel structures 140 may be arranged on the first cell region MCR1 and the second cell region MCR2, and may extend through the gate electrode 130 and the mold insulating layer 132 in a vertical direction (Z direction). The channel structure 140 may intersect the gate electrode 130. The channel structures 140 may be separated from each other by a specific distance in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a third horizontal direction (e.g., an oblique line direction). The channel structures 140 may be arranged in a zigzag or staggered pattern.

[0057] Each channel structure 140 may be in the channel hole 140H in the first cell region MCR1 and the second cell region MCR2. Each channel structure 140 may include a gate insulating layer 142, a channel layer 144, a buried insulating layer 146, and a conductive plug 148. The gate insulating layer 142 and the channel layer 144 may be sequentially arranged on the sidewalls of the channel hole 140H. For example, the gate insulating layer 142 may conform to the sidewalls of the channel hole 140H, and the channel layer 144 may conform to the sidewalls and bottom of the channel hole 140H. The buried insulating layer 146 may be on the channel layer 144 to fill the remaining space of the channel hole 140H. The conductive plug 148 may be on the upper portion of the channel hole 140H to contact the channel layer 144 and block the channel hole 140H. In some embodiments, the buried insulating layer 146 may be omitted, and the channel layer 144 may have a pillar shape filling the remaining portion of the channel hole 140H.

[0058] like Figure 8 As shown in FIG. 1 , the gate insulating layer 142 may have a structure in which a tunneling dielectric film 142A, a charge storage film 142B, and a blocking dielectric film 142C are sequentially disposed on the channel layer 144. The relative thicknesses of the tunneling dielectric film 142A, the charge storage film 142B, and the blocking dielectric film 142C of the gate insulating layer 142 are not limited to Figure 8 The thickness is shown and can be changed in various ways.

[0059] The tunneling dielectric film 142A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film 142B may be a region storing electrons passing through the tunneling dielectric film 142A from the channel layer 144, and may include silicon nitride, boron nitride, silicon boron nitride, or impurity-doped polysilicon. The blocking dielectric film 142C may include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0060] In some embodiments, the source layer 112 and the source support layer 114 may be sequentially formed on the unit substrate 111. The source layer 112 and the source support layer 114 may be between the unit substrate 111 and the mold structure ST. For example, the source layer 112 and the source support layer 114 may extend along the top surface of the unit substrate 111.

[0061] In some embodiments, the unit substrate 111 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon germanium substrate). Alternatively, the unit substrate 111 may include an SOI substrate or a GeOI substrate. In some embodiments, the unit substrate 111 may include impurities. For example, the unit substrate 111 may include n-type impurities (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the unit substrate 111 may include single crystal silicon.

[0062] In some embodiments, the source layer 112 may be formed to be connected to the channel layer 144 of each channel structure 140. For example, Figure 7 As shown in , the source layer 112 may penetrate the gate insulating layer 142 and contact the channel layer 144. The source layer 112 may be provided as a common source line (eg, Figure 2 In some embodiments, the source layer 112 may include doped polysilicon. In some embodiments, the source layer 112 may include metal.

[0063] In some embodiments, the channel layer 144 may be connected to the source layer 112 and separated from the cell substrate 111. Specifically, the channel layer 144 may be separated from the cell substrate 111 by the source layer 112.

[0064] In some embodiments, each channel structure 140 may penetrate the source layer 112 and the source supporting layer 114. For example, a lower portion of the channel structure 140 may penetrate the source supporting layer 114 and the source layer 112, and may be in the unit substrate 111.

[0065] Although not shown, a base insulating film may also exist between the unit substrate 111 and the source layer 112. For example, the base insulating film may include at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

[0066] In some embodiments, a bottom surface of the channel layer 144 may be at a lower vertical level than a top surface of the unit substrate 111 , but embodiments are not limited thereto.

[0067] In some embodiments, a dielectric liner 149 may be between the channel structure 140 and each gate electrode 130. For example, the dielectric liner 149 may be between the channel structure 140 and each gate electrode 130, and on the bottom surface and the top surface of the gate electrode 130. For example, the dielectric liner 149 may be between the gate electrode 130 and the mold insulation layer 132. In some embodiments, the dielectric liner 149 may include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. In some embodiments, the dielectric liner 149 may be omitted.

[0068] In one memory cell block (e.g., the first memory cell block BLK1 or the second memory cell block BLK2), each of the top two gate electrodes 130 may be separated into two parts by a string separation opening SSLH according to a plan view. The string separation insulating layer SSLI may be arranged in the string separation opening SSLH. The two parts of each of the top two gate electrodes 130 may be spaced apart from each other in the second horizontal direction (Y direction), and the string separation insulating layer SSLI is located between the two parts. The two parts of each of the top two gate electrodes 130 may form a reference Figure 2 Describe the string selection line SSL.

[0069] The plurality of gate electrodes 130 on the pad region PR of the connection region CON may form a pad structure PAD. The pad structure PAD may refer to a portion of the gate electrode 130 arranged in a stepped shape. The pad structure PAD may include a plurality of pad portions 130P extending from the gate electrode 130, respectively. Each pad portion 130P may include a connection portion 130P_c in contact with the cell contact 180 and a non-connection portion 130P_n not in contact with the cell contact 180.

[0070] The cover insulating layer 134 may be disposed on the pad structure PAD. The upper insulating layer 136 may be disposed on the uppermost mold insulating layer 132 and the cover insulating layer 134 .

[0071] In the pad region PR of the connection region CON, the trench TR may expose the pad portion 130P. The trench TR may be arranged along the outline of the mold structure ST arranged in a step shape on the pad region PR of the connection region CON.

[0072] The trench TR may include a first sidewall TR_s1 extending in a first horizontal direction (X direction) and a second sidewall TR_s2 extending in a second horizontal direction (Y direction). The trench TR may include a bottom surface TR_b having a stepped shape. The trench TR may expose the pad portion 130P. The bottom surface TR_b of the trench TR may expose the pad portion 130P.

[0073] The first side wall TR_s1 of the trench TR may be on a boundary between the pad region PR and the wall region WR. Figure 6 As shown in , the first sidewall TR_s1 of the trench TR may expose a portion of the sidewall of the wall structure ST_W on the wall region WR.

[0074] The second side wall TR_s2 of the trench TR may include a portion on a boundary between the pad region PR and the first cell region MCR1 and a portion on a boundary between the pad region PR and the second cell region MCR2. The second side wall TR_s2 of the trench TR may include a portion arranged on the pad region PR. Figure 5As shown in , the second sidewall TR_s2 of the trench TR may be disposed on the sidewall of the mold structure ST having the step shape on the pad region PR. The second sidewall TR_s2 of the trench TR may have a plurality of portions that do not overlap each other in the vertical direction (Z direction).

[0075] The bottom surface TR_b of the trench TR may expose the pad portion 130P. Figure 6 As shown in , the bottom surface TR_b of the trench TR may include a plurality of portions having different vertical levels. The bottom surface TR_b of the trench TR may be arranged in a step shape in the first horizontal direction (X direction).

[0076] The liner film 160 , the cell contact 180 , a portion of the dam structure 170 , and the capping insulating layer 134 may be disposed in the trench TR.

[0077] On the pad region PR of the connection region CON, the liner film 160 may be disposed on the first sidewall TR_s1 , the second sidewall TR_s2 , and the bottom surface TR_b of the trench TR.

[0078] The liner film 160 may include a first portion 161 on the first side wall TR_s1 of the trench TR. The first portion 161 of the liner film 160 may extend on the first side wall TR_s1 of the trench TR in the first horizontal direction (X direction). The first portion 161 of the liner film 160 may be located on a boundary between the pad region PR and the wall region WR. The first portion 161 of the liner film 160 may be arranged on a portion of the side wall of the wall structure ST_W exposed by the first side wall TR_s1 of the trench TR. In some embodiments, the first portion 161 of the liner film 160 may contact a portion of the side wall of the wall structure ST_W exposed by the first side wall TR_s1 of the trench TR.

[0079] The liner film 160 may further include a second portion 162 on the bottom surface TR_b of the trench. The second portion 162 of the liner film 160 may be disposed on the non-connection portion 130P_n of the pad portion 130P. The second portion 162 of the liner film 160 may be between each non-connection portion 130P_n of the pad portion 130P and the cover insulating layer 134. The second portion 162 of the liner film 160 may not be disposed on the connection portion 130P_c of each pad portion 130P. Figure 5 As shown in FIG. 1 , the second portion 162 of the liner film 160 may include a plurality of portions at different vertical levels. The second portion 162 of the liner film 160 may be arranged in a step shape in the first horizontal direction (X direction).

[0080] The liner film 160 may further include a third portion 163 on the second sidewall TR_s2 of the trench TR. The third portion 163 of the liner film 160 may extend on the second sidewall TR_s2 of the trench TR in the second horizontal direction (Y direction). The third portion 163 of the liner film 160 may include a portion on a boundary between the pad region PR and the first cell region MCR1 and a portion on a boundary between the pad region PR and the second cell region MCR2. Figure 5 As shown in FIG, the third portion 163 of the liner film 160 may be disposed on the sidewall of the mold structure ST having the step shape on the pad region PR. The third portion 163 of the liner film 160 may include a plurality of portions that do not overlap each other in the vertical direction (Z direction).

[0081] The liner film 160 may include an oxide. The liner film 160 may have different etching selectivities relative to the capping insulating layer 134. For example, the liner film 160 may include a material having a low etching selectivity relative to the capping insulating layer 134. For example, the liner film 160 may include borophosphosilicate glass (BPSG). The liner film 160 may have a thickness of about 200Å to about 1000Å. For example, the liner film 160 may have a thickness of about 1000Å or more.

[0082] In the pad region PR of the connection region CON, the plurality of recesses R may respectively expose the pad portions 130P of the gate electrode 130. Specifically, the recesses R may partially expose the pad portions 130P. For example, the recesses R may expose the connection portions 130P_c of the pad portions 130P.

[0083] The recess R may expose the first portion 161 of the liner film 160 disposed on the first sidewall TR_s1 of the trench TR.

[0084] On the pad region PR of the connection region CON, a plurality of cell contacts 180 may be arranged to respectively fill the recesses R. Each cell contact 180 may be connected to one of the pad portions 130P of the gate electrodes 130. Each cell contact 180 may be connected to a connection portion 130P_c of the pad portion 130P of one of the gate electrodes 130.

[0085] The cell contact 180 may include a first sidewall 180_s1 on the first sidewall TR_s1 of the trench TR and a second sidewall 180_s2 opposite to the first sidewall 180_s1 .

[0086] The first side wall 180_s1 of the cell contact 180 may extend on the first side wall TR_s1 of the trench TR in the first horizontal direction (X direction). The first side wall 180_s1 of the cell contact 180 may be arranged on a portion of the side wall of the wall structure ST_W exposed by the first side wall TR_s1 of the trench TR. The first side wall 180_s1 of the cell contact 180 may be arranged on the first portion 161 of the liner film 160 on the first side wall TR_s1 of the trench TR. The first side wall 180_s1 of the cell contact 180 may contact the first portion 161 of the liner film 160.

[0087] The second sidewall 180_s2 of the cell contact 180 may be surrounded by the dam structure 170 . The second sidewall 180_s2 of the cell contact 180 may be in contact with the dam structure 170 .

[0088] In some embodiments, according to a plan view, the second sidewall 180_s2 of the cell contact 180 may be recessed relative to the first sidewall 180_s1 of the cell contact 180. The second sidewall 180_s2 of the cell contact 180 may be a curved surface recessed relative to the first sidewall 180_s1 of the cell contact 180.

[0089] In a plan view, the cell contact 180 may have an arcuate shape. The first side wall 180_s1 and the second side wall 180_s2 of the cell contact 180 may form an arcuate shape. Specifically, the first side wall 180_s1 of the cell contact 180 may form a chord of the arcuate shape. The second side wall 180_s2 of the cell contact 180 may form an arc of the arcuate shape. For example, the cell contact 180 may have a semicircular shape. The first side wall 180_s1 and the second side wall 180_s2 of the cell contact 180 may define a semicircular shape (e.g., a chord and an arc of a semicircular shape).

[0090] The cell contact 180 may not penetrate the mold structure ST. The cell contact 180 may extend in the recess R and reach the pad portion 130P of the gate electrode 130 .

[0091] The cell contact 180 may include: a metal (such as tungsten, nickel, cobalt, or tantalum); a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide); doped polysilicon; or a combination thereof.

[0092] In some embodiments, the cell contact 180 may transmit an electrical signal to the gate electrode 130. Specifically, when the electrical signal is applied to the cell contact 180, the electrical signal may be transmitted to the pad 130P connected to the cell contact 180. The electrical signal transmitted to the pad 130P may be transmitted to the wall structure ST_W on the wall region WR in the second horizontal direction (Y direction). Specifically, the electrical signal may be transmitted to the gate electrode 130 that is at the same vertical level as the pad 130P and connected to the pad 130P among the plurality of gate electrodes 130 of the wall structure ST_W. Subsequently, the electrical signal may be bidirectionally transmitted in the first horizontal direction (X direction). Specifically, the electrical signal may be transmitted to the gate electrode 130 on the first cell region MCR1 and the gate electrode 130 on the second cell region MCR2 in the first horizontal direction (X direction).

[0093] On the pad region PR of the connection region CON, the capping insulating layer 134 may be disposed to fill the trench TR. The capping insulating layer 134 may fill the trench TR except for the liner film 160 , the dam structure 170 , and the recess R.

[0094] The cover insulating layer 134 may be disposed on the pad portion 130P. Specifically, the cover insulating layer 134 may be disposed on the non-connection portion 130P_n of the pad portion 130P. The cover insulating layer 134 may be disposed on the mold structure ST with the liner film 160 therebetween.

[0095] The capping insulating layer 134 may surround the cell contact 180 with the dam structure 170 therebetween. Specifically, the capping insulating layer 134 may surround the second sidewall 180_s2 of the cell contact 180 with the dam structure 170 therebetween.

[0096] On the pad region PR of the connection region CON, the dam structure 170 may be arranged to penetrate the capping insulating layer 134, the plurality of gate electrodes 130, and the plurality of mold insulating layers 132. The dam structure 170 may penetrate the liner film 160 on the pad portion 130P. The dam structure 170 may penetrate the second portion 162 of the liner film 160. The dam structure 170 may surround the second side wall 180_s2 of the cell contact 180. The dam structure 170 may contact the second side wall 180_s2 of the cell contact 180. The dam structure 170 may be between the cell contact 180 and the capping insulating layer 134. The dam structure 170 may be between the second side wall 180_s2 of the cell contact 180 and the capping insulating layer 134.

[0097] The dam structure 170 may include oxide. The dam structure 170 may have a different etching selectivity with respect to the capping insulating layer 134. For example, the dam structure 170 may include a material having a low etching selectivity with respect to the capping insulating layer 134. The dam structure 170 may include the same material as the liner film 160.

[0098] Although not shown, in the pad region PR of the connection region CON, a plurality of support structures 150 may be arranged to penetrate the capping insulating layer 134, the gate electrode 130, and the mold insulating layer 132. In a plan view, each support structure 150 may be adjacent to the cell contact 180. The support structure 150 may include at least one of silicon oxide and silicon oxynitride. The support structure 150 may be formed to prevent the gate electrode 130 from being tilted or bent during the manufacturing process of the nonvolatile memory device 100 and to ensure the structural stability of the gate electrode 130.

[0099] In the first cell region MCR1 and the second cell region MCR2, the bit line contacts BLC may penetrate the upper insulating layer 136 and may make contact with the conductive plugs 148 of the channel structures 140. The bit lines may be disposed on the bit line contacts BLC.

[0100] In the connection region CON, the upper contact 185 may penetrate the upper insulating layer 136 and may make contact with the cell contact 180. The upper contact 185 may be disposed on a top surface of the cell contact 180.

[0101] Fig.9A , Fig. 9B and Fig. 9C is an exemplary cross-sectional view of nonvolatile memory devices 100A, 100B, and 100C. The following description focuses on the above-referenced Figures 3 to 8 The differences of the non-volatile memory device 100 are described.

[0102] Reference Fig.9A , a nonvolatile memory device 100A can be provided. Fig.9A is along with Figure 4 A sectional view corresponding to the section taken along the line Y1-Y1' in FIG.

[0103] The nonvolatile memory device 100A may include a cell contact 180A and a filling layer 186 in the recess R. The cell contact 180A may be conformally arranged on the sidewall and bottom surface of the recess R. The cell contact 180A may be connected to the connection portion 130P_c of the pad portion 130P on the bottom surface of the recess R. The filling layer 186 may be arranged on the cell contact 180A to fill the remaining space of the recess R. An upper contact 185A may be arranged on the top surface of the cell contact 180A. The upper contact 185A may penetrate the upper insulating layer 136 and contact the cell contact 180A.

[0104] Reference Fig. 9B , a nonvolatile memory device 100B is provided. Fig. 9B is along with Figure 4 A sectional view corresponding to the section taken along the line Y1-Y1' in FIG.

[0105] The nonvolatile memory device 100B may include a liner film 160 extending on the inner wall and the bottom surface of the trench TR. Specifically, the liner film 160 may include a first portion 161 extending on the first sidewall TR_s1 of the trench TR. The first portion 161 of the liner film 160 may include a protrusion 161_P extending on the pad portion 130P in the second horizontal direction (Y direction). The protrusion 161_P may extend from a lower portion of the first portion 161 of the liner film 160 in the second horizontal direction (Y direction).

[0106] Reference Fig. 9C , a nonvolatile memory device 100C is provided. Fig. 9C is along with Figure 4 A sectional view corresponding to the section taken along the line Y2-Y2' in FIG.

[0107] The nonvolatile memory device 100C may include a plurality of channel structures 140C extending from a top surface of the common source plate 110 in a vertical direction (Z direction) and penetrating the gate electrode 130 and the mold insulating layer 132 on the first and second cell regions MCR1 and MCR2 .

[0108] Each channel structure 140C may be in the channel hole 140CH on the first cell region MCR1 and the second cell region MCR2 . Each channel structure 140C may include a gate insulating layer 142 , a channel layer 144C, a buried insulating layer 146C, and a conductive plug 148C.

[0109] In some embodiments, the channel layer 144C may be in contact with the top surface of the common source plate 110 at the bottom of the channel hole 140CH. In some embodiments, the bottom surface of the channel layer 144C may be at a lower vertical level than the top surface of the common source plate 110, such as Fig. 9C However, the embodiment is not limited thereto.

[0110] Fig.10 , Fig.11 , Fig.12 and Fig.13 is an exemplary plan view of nonvolatile memory devices 101, 102, 103, and 104. The following description focuses on the above-referenced Figures 3 to 8 The differences of the non-volatile memory device 100 are described.

[0111] Reference Fig.10 , a nonvolatile memory device 101 may be provided. In some embodiments, corresponding pad regions PR of two adjacent memory cell blocks of the nonvolatile memory device 101 may be spaced apart from each other, and a wall region WR is placed between the corresponding pad regions PR of the two adjacent memory cell blocks. Specifically, the pad region PR of the first memory cell block BLK1 may be spaced apart from the pad region PR of the second memory cell block BLK2 in the second horizontal direction (Y direction), and the wall region WR of the first memory cell block BLK1 is between the pad region PR of the first memory cell block BLK1 and the pad region PR of the second memory cell block BLK2.

[0112] In some embodiments, the trenches TR1 on the corresponding pad regions PR of two adjacent memory cell blocks may be spaced apart from each other, and the wall region WR is between the trenches TR1 on the corresponding pad regions PR of the two adjacent memory cell blocks. For example, the trench TR1 of the first memory cell block BLK1 may be spaced apart from the trench TR1 of the second memory cell block BLK2 in the second horizontal direction (Y direction), and the wall region WR of the first memory cell block BLK1 is between the trench TR1 of the first memory cell block BLK1 and the trench TR1 of the second memory cell block BLK2.

[0113] Reference Fig.11, a nonvolatile memory device 102 may be provided. In some embodiments, a memory cell block of the nonvolatile memory device 102 may include one pad region PR and two wall regions (e.g., a first wall region WR1 and a second wall region WR2). Specifically, the pad region PR of the first memory cell block BLK1 may be between the first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1. The first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1 may be spaced apart from each other in the second horizontal direction (Y direction), and the pad region PR of the first memory cell block BLK1 is between the first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1. Specifically, the pad region PR of the second memory cell block BLK2 may be between the first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2. The first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2 may be spaced apart from each other in the second horizontal direction (Y direction), and the pad region PR of the second memory cell block BLK2 is between the first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2.

[0114] In some embodiments, the trench TR2 on the pad region PR of the memory cell block may be between the first wall region WR1 and the second wall region WR2 of the memory cell block. Specifically, the trench TR2 of the first memory cell block BLK1 may be between the first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1. The first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1 may be spaced apart from each other in the second horizontal direction (Y direction), and the trench TR2 of the first memory cell block BLK1 is between the first wall region WR1 and the second wall region WR2 of the first memory cell block BLK1. Specifically, the trench TR2 of the second memory cell block BLK2 may be between the first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2. The first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2 may be spaced apart from each other in the second horizontal direction (Y direction), and the trench TR2 of the second memory cell block BLK2 is between the first wall region WR1 and the second wall region WR2 of the second memory cell block BLK2.

[0115] Reference Fig.12, a nonvolatile memory device 103 may be provided. In some embodiments, a memory cell block of the nonvolatile memory device 103 may include one pad region PR and two wall regions (e.g., a first wall region WR1 and a second wall region WR2). Specifically, the pad region PR of each of the first memory cell block BLK1 and the second memory cell block BLK2 may be between the first wall region WR1 and the second wall region WR2 of each of the first memory cell block BLK1 and the second memory cell block BLK2. Specifically, the trench TR3 on the pad region PR of each of the first memory cell block BLK1 and the second memory cell block BLK2 may be between the first wall region WR1 and the second wall region WR2 of each of the first memory cell block BLK1 and the second memory cell block BLK2.

[0116] For example, the trench TR3 may include a first side wall TR3_s1 adjacent to the first wall region WR1 and a second side wall TR3_s2 adjacent to the second wall region WR2. The first side wall TR3_s1 of the trench TR3 may expose a portion of the side wall of the first wall structure on the first wall region WR1. The second side wall TR3_s2 of the trench TR3 may expose a portion of the side wall of the second wall structure on the second wall region WR2. The first side wall TR3_s1 and the second side wall TR3_s2 of the trench TR3 may extend in the first horizontal direction (X direction). The first side wall TR3_s1 and the second side wall TR3_s2 of the trench TR3 may face each other in the second horizontal direction (Y direction).

[0117] The liner film 165 of the nonvolatile memory device 103 may be disposed on the sidewalls and bottom surface of the trench TR3. Specifically, the liner film 165 may include a first sub-portion 165_1 disposed on the first sidewall TR3_s1 of the trench TR3 and a second sub-portion 165_2 disposed on the second sidewall TR3_s2 of the trench TR3.

[0118] In some embodiments, the trench TR3 may expose a plurality of pad portions 133P. Specifically, the bottom surface of the trench TR3 may expose the pad portion 133P. The pad portion 133P may include a first pad portion 133P1 adjacent to the first wall region WR1 and a second pad portion 133P2 adjacent to the second wall region WR2. The vertical levels of the first pad portion 133P1 and the second pad portion 133P2 overlapping each other in the second horizontal direction (Y direction) may be different from each other. The first pad portion 133P1 and the second pad portion 133P2 overlapping each other in the second horizontal direction (Y direction) may be connected to different gate electrodes 130, respectively (see FIG. 1 ). Figures 5 to 7 ).

[0119] In some embodiments, a plurality of cell contacts 183 may be arranged in the trench TR3 to be respectively connected to the pads 133P. The cell contacts 183 may include a first cell contact 183_1 adjacent to the first wall region WR1 and a second cell contact 183_2 adjacent to the second wall region WR2. The first cell contact 183_1 may be connected to the first pad 133P1. The second cell contact 183_2 may be connected to the second pad 133P2. An electrical signal applied to the first cell contact 183_1 may be transmitted to the first pad 133P1 through the wall structure on the first wall region WR1, and then to the gate electrode 130 on the first cell region MCR1 and the second cell region MCR2. An electrical signal applied to the second cell contact 183_2 may be transmitted to the second pad 133P2 through the wall structure on the second wall region WR2, and then to the gate electrode 130 on the first cell region MCR1 and the second cell region MCR2.

[0120] Reference Fig.13 , a nonvolatile memory device 104 may be provided. In some embodiments, the nonvolatile memory device 104 may include a plurality of cell contacts 184 and a dam structure 174 surrounding each cell contact 184 on the pad region PR.

[0121] In a plan view, each cell contact 184 may have a quadrilateral shape. The sidewall of the cell contact 184 may form a quadrilateral shape together with the liner film 160. For example, the cell contact 184 may have a rectangular shape. For example, the cell contact 184 may be square.

[0122] Similarly, the dam structure 174 may form a quadrilateral shape together with the liner film 160. For example, the dam structure 174 may form a rectangular shape together with the liner film 160. For example, the dam structure 174 may form a square shape together with the liner film 160.

[0123] In some embodiments, reference Figures 1 to 13 Each of the described nonvolatile memory devices 100, 100A, 100B, 100C, 101, 102, 103, and 104 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area on a first wafer, manufacturing a lower chip including a peripheral circuit area on a second wafer different from the first wafer, and then connecting the upper chip to the lower chip in a bonding manner. For example, the bonding manner may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding manner may be Cu-Cu bonding, and the bonding metal may also include aluminum (Al) or tungsten (W).

[0124] Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A and Fig.21B is a cross-sectional view showing an example of a method of manufacturing the nonvolatile memory device 100. Specifically, Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A is along with Figure 4 The cross-sectional view corresponding to the cross-sectional view taken by the X1-X1' line in the figure is: Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B is with Figure 4 The cross-sectional view corresponds to the cross-sectional view taken along the Y1-Y1' line in FIG.

[0125] Reference Fig.14A and Fig. 14B , a peripheral circuit structure PS may be formed on the substrate 50. In an embodiment, the substrate 50 may correspond to a single crystal silicon substrate. A plurality of peripheral circuit transistors 60TR may be formed on the substrate 50. A peripheral circuit wiring structure 70 and an interlayer insulating film 80 may be formed to be electrically connected to the peripheral circuit transistors 60TR.

[0126] Next, a common source plate 110 may be formed on the interlayer insulating film 80. In some embodiments, the common source plate 110 may be formed using a semiconductor doped with n-type impurities.

[0127] Then, a plurality of mold insulating layers 132 and a plurality of sacrificial layers S130 may be alternately formed on the common source plate 110. In some embodiments, the mold insulating layer 132 may include an insulating material such as silicon oxide or silicon oxynitride, and the sacrificial layer S130 may include silicon nitride, silicon oxynitride, or impurity-doped polysilicon.

[0128] The preliminary trench STR may be formed by sequentially patterning the mold insulation layer 132 and the sacrificial layer S130 on the connection region CON. Thus, a preliminary pad structure SPAD may be formed. In some embodiments, the preliminary pad structure SPAD may be formed to have steps having different top surface levels (or top surface heights) in a first horizontal direction (X direction). For example, the preliminary pad structure SPAD may include a plurality of preliminary pad portions S130P.

[0129] In some embodiments, the preliminary trench STR may include a first sidewall STR_s1 extending in the first horizontal direction (X direction), a second sidewall STR_s2 extending in the second horizontal direction (Y direction), and a bottom surface STR_b exposing the preliminary pad portion S130P. The first sidewall STR_s1 of the preliminary trench STR may partially expose the sidewalls of the mold insulating layer 132 and the sacrificial layer S130 on the wall region WR. The bottom surface STR_b of the preliminary trench STR may be arranged in a stepped shape in the first horizontal direction (X direction).

[0130] Reference Fig.15A and Fig. 15B , a liner film 160 may be formed on the first sidewall STR_s1 , the second sidewall STR_s2 , and the bottom surface STR_b of the preliminary trench STR.

[0131] The first portion 161 of the liner film 160 may extend on the first sidewall STR_s1 of the preliminary trench STR in the first horizontal direction (X direction). The first portion 161 of the liner film 160 may be partially disposed on the sidewalls of the mold insulating layer 132 and the sacrificial layer S130 exposed by the first sidewall STR_s1 of the preliminary trench STR on the boundary between the pad region PR and the wall region WR.

[0132] The second portion 162 of the liner film 160 may be disposed on the bottom surface STR_b of the preliminary trench STR. The second portion 162 of the liner film 160 may be disposed on the preliminary pad portion S130P. The second portion 162 of the liner film 160 may be arranged in a stepped shape in the first horizontal direction (X direction).

[0133] The third portion 163 of the liner film 160 may be disposed on the second sidewall STR_s2 of the preliminary trench STR. The third portion 163 of the liner film 160 may be partially disposed on the sidewalls of the mold insulating layer 132 and the sacrificial layer S130 exposed by the second sidewall STR_s2 of the preliminary trench STR on the boundary between the pad region PR and each of the first and second cell regions MCR1 and MCR2.

[0134] Reference Fig.16A and Fig. 16B, a capping insulating layer 134 may be formed to fill the preliminary trench STR. The capping insulating layer 134 may be disposed on the liner film 160 .

[0135] Reference Fig.17A and Fig. 17B The dam structure 170 may be formed to penetrate the capping insulating layer 134 , the sacrificial layer 130 , and the mold insulating layer 132 .

[0136] Specifically, a plurality of through holes penetrating the cover insulating layer 134, the sacrificial layer S130, and the mold insulating layer 132 may be formed to form the dam structure 170. For example, a plurality of through holes penetrating one preparatory pad portion S130P may be formed. Subsequently, a process of forming the dam hole may be performed by enlarging the through hole. Specifically, a dam hole may be formed by etching the cover insulating layer 134, the sacrificial layer S130, and the mold insulating layer 132 exposed by the sidewall of the through hole. Thus, a dam hole penetrating one preparatory pad portion S130P may be formed. Subsequently, the dam structure 170 may be formed by filling the dam hole with an insulating material. The dam structure 170 may include a material having a different etching selectivity relative to the cover insulating layer 134. The dam structure 170 may include a material having a low etching selectivity relative to the cover insulating layer 134. The dam structure 170 may include the same material as the liner film 160.

[0137] During the formation of the dam structure 170, the formation of a plurality of channel structures 140 may be performed on the first cell region MCR1 and the second cell region MCR2 (see Figure 4 and Figure 7 During the formation of the dam structure 170, a plurality of support structures 150 (see FIG. 1 ) penetrating the cover insulating layer 134, the sacrificial layer 130, and the mold insulating layer 132 may be formed. Figure 4 ) process.

[0138] In some embodiments, the process of forming the dam structure 170 may be performed separately from the process of forming the channel structure 140 on the first cell region MCR1 and the second cell region MCR2 and the process of forming the support structure 150 on the connection region CON. For example, the dam structure 170 may be formed on the pad region PR of the connection region CON after the channel structure 140 and the support structure 150 are formed. Alternatively, the channel structure 140 and the support structure 150 may be formed after the dam structure 170 is formed on the pad region PR of the connection region CON.

[0139] For example, to create a reference Fig.13The described nonvolatile memory device 104 may form the dam structure 170 on the pad region PR of the connection region CON after forming the channel structure 140 and the support structure 150 , or may form the channel structure 140 and the support structure 150 after forming the dam structure 170 on the pad region PR of the connection region CON.

[0140] Reference Fig.18A and Fig.18B , the sacrificial layer 130 may be removed, and a dielectric liner 149 may be conformally formed on the top and bottom surfaces of each mold insulating layer 132. Subsequently, the gate electrode 130 may be formed by applying a conductive material to the dielectric liner 149.

[0141] Reference Fig.19A and Fig.19B , the covering insulating layer 134 surrounded by the liner film 160 and the dam structure 170 may be partially etched. The covering insulating layer 134 may be partially etched using a wet etching process. Specifically, the covering insulating layer 134 surrounded by the liner film 160 and the dam structure 170 may be partially etched using an etchant. As described above, the covering insulating layer 134 may include a material having a different etching selectivity relative to the liner film 160 and the dam structure 170. Specifically, the covering insulating layer 134 may include a material having a high etching selectivity relative to the liner film 160 and the dam structure 170. For example, the covering insulating layer 134 may include a material having an etching selectivity of about 100 times or more relative to the liner film 160 and the dam structure 170. Therefore, when the covering insulating layer 134 is removed by a wet etching process using an etchant, the liner film 160 and the dam structure 170 may not be removed.

[0142] Through the above process, a plurality of recesses R each surrounded by the liner film 160 and the dam structure 170 may be formed. Each recess R may include a sidewall and a bottom surface surrounded by the liner film 160 and the dam structure 170. The first portion 161 of the liner film 160 and the inner wall of the dam structure 170 may be exposed by the sidewall of each recess R. The second portion 162 of the liner film 160 may be exposed by the bottom surface of each recess R.

[0143] Reference Fig. 20A and Fig. 20B, the second portion 162 of the liner film 160 exposed by each recess R may be partially removed. Specifically, a portion of the second portion 162 of the liner film 160 exposed by the bottom surface of each recess R may be removed. In some embodiments, when the dielectric liner 149 is between the gate electrode 130 and one of the mold insulating layers 132, a portion of the dielectric liner 149 below the bottom surface of the recess R may also be removed. Through the above process, the pad portion 130P of the gate electrode 130 may be partially exposed. Specifically, a portion of the pad portion 130P of the gate electrode 130 may be exposed by the bottom surface of the recess R. The exposed portion of the pad portion 130P may be referred to as a connection portion 130P_c. The portion of the pad portion 130P of the gate electrode 130 that is not exposed by the bottom surface of the recess R may be referred to as a non-connection portion 130P_n.

[0144] Reference Fig.21A and Fig.21B , the cell contact 180 may be formed to fill the recess R. Specifically, the cell contact 180 may be formed by filling the recess R with a conductive material. The cell contact 180 may be connected to the pad 130P located on the bottom surface of the recess R. Specifically, the cell contact 180 may be connected to the connection portion 130P_c of the pad 130P located on the bottom surface of the recess R.

[0145] Afterwards, you can Fig.21A and Fig.21B The resulting structure is then subjected to subsequent processing to produce a reference Figures 3 to 8 A nonvolatile memory device 100 is described.

[0146] In some embodiments, when the nonvolatile memory device 100 is manufactured using the liner film 160 and the capping insulating layer 134 having different etching selectivities relative to each other, the difficulty of the manufacturing process of the nonvolatile memory device 100 can be reduced. In some embodiments, when the nonvolatile memory device 100 is manufactured using the dam structure 170 and the capping insulating layer 134 having different etching selectivities relative to each other, the difficulty of the manufacturing process of the nonvolatile memory device 100 can be reduced. In other words, a nonvolatile memory device 100 having reduced process difficulty can be provided. In other words, an electronic system including the nonvolatile memory device 100 having reduced process difficulty can be provided.

[0147] In some embodiments, when the nonvolatile memory device 100 is manufactured using the liner film 160 and the capping insulating layer 134 having different etching selectivities relative to each other, failure of the nonvolatile memory device 100 can be reduced and performance of the nonvolatile memory device 100 can be improved. In some embodiments, when the nonvolatile memory device 100 is manufactured using the dam structure 170 and the capping insulating layer 134 having different etching selectivities relative to each other, failure of the nonvolatile memory device 100 can be reduced and performance of the nonvolatile memory device 100 can be improved. In other words, a nonvolatile memory device 100 having enhanced performance and reliability can be provided. In other words, an electronic system including a nonvolatile memory device 100 having enhanced performance and reliability can be provided.

[0148] Fig. 22 is a schematic diagram of an example of a data storage system 1000 including a non-volatile memory device.

[0149] Reference Fig. 22 , the data storage system 1000 may include at least one nonvolatile memory device 1100 and a memory controller 1200 electrically connected to the nonvolatile memory device 1100. For example, the data storage system 1000 may correspond to any one of a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, and a communication device, each of which includes the nonvolatile memory device 1100.

[0150] For example, the nonvolatile memory device 1100 may include a reference Figures 1 to 13 The nonvolatile memory device 100, 100A, 100B, 100C, 101, 102, 103, and 104 described herein is a NAND flash nonvolatile memory device. The nonvolatile memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may correspond to a peripheral circuit structure including a row decoder 1110, a page buffer 1120, and a logic circuit 1130.

[0151] The second structure 1100S may correspond to a memory cell structure including a bit line BL, a common source line CSL, a plurality of word lines WL, a first string selection line UL1, a second string selection line UL2, a first ground selection line LL1, a second ground selection line LL2, and a plurality of memory cell strings CSTR between the bit line BL and the common source line CSL.

[0152] In the second structure 1100S, each memory cell string CSTR may include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT located between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of the ground selection transistors LT1 and LT2 and the number of the string selection transistors UT1 and UT2 may vary depending on the implementation.

[0153] In some embodiments, the first ground selection line LL1 and the second ground selection line LL2 may be connected to the gate electrodes of the ground selection transistors LT1 and LT2, respectively. The word lines WL may be connected to the gate electrodes of the memory cell transistors MCT, respectively. The first string selection line UL1 and the second string selection line UL2 may be connected to the gate electrodes of the string selection transistors UT1 and UT2, respectively.

[0154] Common source lines CSL, first and second ground selection lines LL1 and LL2, word lines WL, first and second string selection lines UL1 and UL2 may be connected to the row decoder 1110. A plurality of bit lines BL may be electrically connected to the page buffer 1120.

[0155] The nonvolatile memory device 1100 may communicate with the memory controller 1200 through an I / O pad 1101 electrically connected to the logic circuit 1130. The I / O pad 1101 may be electrically connected to the logic circuit 1130.

[0156] The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 may include a plurality of nonvolatile memory devices 1100. In this case, the memory controller 1200 may control the plurality of nonvolatile memory devices 1100.

[0157] The processor 1210 may generally control the operation of the data storage system 1000 including the memory controller 1200. The processor 1210 may operate according to a specific firmware, and may control the NAND controller 1220 to access the nonvolatile memory device 1100. The NAND controller 1220 may include a NAND interface 1221 for communicating with the nonvolatile memory device 1100. A control command for controlling the nonvolatile memory device 1100, data to be written to the memory cell transistors MCT of the nonvolatile memory device 1100, data read from the memory cell transistors MCT of the nonvolatile memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a function for communication between the nonvolatile memory device 1100 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the nonvolatile memory device 1100 in response to the control command.

[0158] Fig.23 is a schematic perspective view of an example of a data storage system 2000 including a nonvolatile memory device.

[0159] Reference Fig.23 , the data storage system 2000 may include a main board 2001, a memory controller 2002 mounted on the main board 2001, at least one semiconductor package 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main board 2001.

[0160] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and layout of the pins in the connector 2006 may vary with the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to any one of interfaces such as USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-PHY for Universal Flash Storage (UFS). In some embodiments, the data storage system 2000 may be driven by power supplied from the external host through the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the memory controller 2002 and the semiconductor package 2003.

[0161] The memory controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operation speed of the data storage system 2000 .

[0162] The DRAM 2004 may be used as a buffer memory for alleviating a speed difference between an external host and the semiconductor package 2003 as a data storage space. The DRAM 2004 included in the data storage system 2000 may also operate as a high-speed cache memory and provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the data storage system 2000, the memory controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0163] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b separated from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the bottom surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0164] The package substrate 2100 may include a printed circuit board (PCB) including a plurality of package pads 2130. Each semiconductor chip 2200 may include an I / O pad 2210. The I / O pad 2210 may be connected to a Fig. 22 Each semiconductor chip 2200 may include a reference Figures 1 to 13 At least one of the nonvolatile memory devices 100, 100A, 100B, 100C, 101, 102, 103, and 104 described.

[0165] In some embodiments, the connection structure 2400 may include bonding wires that electrically connect the I / O pads 2210 to the package upper pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through bonding wires, and to the package upper pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through silicon vias (TSVs, or “through silicon vias”) instead of the connection structure 2400 using bonding wires.

[0166] In some embodiments, the memory controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the memory controller 2002 and the semiconductor chip 2200 may be mounted on an interposer separate from the main board 2001 and may be connected to each other through wiring formed on the interposer.

[0167] Fig.24 is a schematic cross-sectional view of an example of a semiconductor package. Specifically, Fig.24 It is along Fig.23 A cross-sectional view taken along line II-II'.

[0168] Reference Fig.24 In the semiconductor package 2003, the package substrate 2100 may be a PCB. The package substrate 2100 may include a package substrate body 2120, a plurality of package upper pads ( Fig.23 2130 in the package substrate body 2120), a plurality of lower pads 2125 arranged on the bottom surface of the package substrate body 2120 or exposed by the bottom surface of the package substrate body 2120, and a plurality of internal wires 2135 inside the package substrate body 2120 and electrically connecting the package upper pads 2130 to the lower pads 2125. Fig.23 As shown in , the package upper pad 2130 can be electrically connected to a plurality of connection structures 2400. Fig.24 As shown in FIG. 1 , the lower pad 2125 can be connected to the Fig.23 The wiring pattern 2005 on the main board 2001 of the data storage system 2000. Each semiconductor chip 2200 may include a reference Figures 1 to 13 At least one of the nonvolatile memory devices 100, 100A, 100B, 100C, 101, 102, 103, and 104 described.

[0169] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to specific implementations of specific inventions. Specific features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in a particular combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0170] While the present disclosure has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A non-volatile memory device, comprising: A substrate, comprising a first unit region, a second unit region and a connection region, wherein the connection region is between the first unit region and the second unit region; A mold structure comprising a plurality of gate electrodes and a plurality of mold insulating layers, the plurality of gate electrodes and the plurality of mold insulating layers being stacked on a substrate, the plurality of gate electrodes being stacked on a pad region of a connection region in a staircase pattern, and the plurality of mold insulating layers being alternately stacked with the plurality of gate electrodes; a channel structure on the first cell region and the second cell region, the channel structure extending through the mold structure and crossing the plurality of gate electrodes; a groove on the pad region of the connection region along the contour of the mold structure, the groove comprising a bottom surface and a first side wall, the bottom surface having a stepped shape, the first side wall being located on a boundary between the pad region of the connection region and the wall region of the connection region; a liner film on a first sidewall of the trench; a recessed portion in the trench, the recessed portion exposing a pad portion of a gate electrode among the plurality of gate electrodes and a liner film on a first sidewall of the trench; A cell contact is disposed at the recessed portion, the cell contact being connected to the pad portion of the gate electrode; as well as A covering insulating layer is provided at the groove, The liner film has an etching selectivity different from that of the cover insulating layer.

2. The nonvolatile memory device according to claim 1, wherein: The cell contact includes a first sidewall on the liner film, and the first sidewall of the cell contact contacts the liner film.

3. The nonvolatile memory device according to claim 1, wherein: The cell contact includes a second sidewall surrounded by the dam structure, and The dam structure is between the cover insulating layer and the cell contact.

4. The nonvolatile memory device according to claim 3, wherein: The second sidewall of the cell contact contacts the dam structure.

5. The nonvolatile memory device according to claim 3, wherein: The dam structure has a different etching selectivity from the capping insulating layer.

6. The nonvolatile memory device according to claim 5, wherein: The dam structure and the lining membrane comprise the same material.

7. The nonvolatile memory device according to claim 1, wherein: The molded structure includes a wall structure on the wall area, A first sidewall of the trench exposes a portion of a sidewall of the wall structure, and The liner film is in contact with the portion of the side wall of the wall structure.

8. The nonvolatile memory device according to any one of claims 1 to 7, wherein: The first unit region and the second unit region are spaced apart from each other in a first horizontal direction, and The pad region and the wall region are located on the connection region in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction.

9. A non-volatile memory device, comprising: Peripheral circuit substrate; A peripheral circuit device, on the peripheral circuit substrate; A unit substrate, on the peripheral circuit substrate, the unit substrate includes a first unit region, a second unit region and a connection region, the second unit region is spaced apart from the first unit region in a first horizontal direction, the connection region is located between the first unit region and the second unit region, the connection region includes a pad region and a wall region, the pad region and the wall region are located in a second horizontal direction intersecting the first horizontal direction; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, the plurality of gate electrodes being stacked in a staircase pattern on a pad region of a connection region, the plurality of mold insulating layers being alternately stacked with the plurality of gate electrodes, and the mold structure including a wall structure on a wall region of the connection region; a channel structure on the first cell region and the second cell region, the channel structure extending through the mold structure and crossing the plurality of gate electrodes; a cell contact on the pad region of the connection region, the cell contact comprising a first sidewall on the sidewall of the wall structure, the cell contact being connected to a pad portion of a gate electrode among the plurality of gate electrodes; a liner film on a first side wall of the cell contact, the liner film including a first portion extending in a first horizontal direction; a cover insulating layer, on the pad region, the cover insulating layer surrounding a second sidewall of the cell contact, the second sidewall of the cell contact being opposite to the first sidewall of the cell contact; as well as a dam structure between the second sidewall of the cell contact and the covering insulating layer, wherein the liner film contacts the first side wall of the cell contact, and The dam structure has an etching selectivity different from that of the capping insulating layer.

10. The nonvolatile memory device according to claim 9, wherein: In a plan view, the second side wall of the cell contact is recessed relative to the first side wall of the cell contact.

11. The nonvolatile memory device according to claim 10, wherein: In a plan view, the cell contact has an arcuate shape, and The first sidewall and the second sidewall of the cell contact define an arcuate shape.

12. The nonvolatile memory device according to any one of claims 9 to 11, wherein: The liner film has a different etching selectivity from the capping insulating layer.

13. The nonvolatile memory device according to claim 12, wherein: The dam structure and the lining membrane comprise the same material.

14. The nonvolatile memory device according to claim 9, wherein: The pad portion of the gate electrode includes a connection portion and a non-connection portion, the connection portion contacts the cell contact, the non-connection portion does not contact the cell contact, and The cover insulating layer is located on the non-connecting portion of the pad portion.

15. The nonvolatile memory device according to claim 14, wherein: The liner film includes a second portion between the capping insulating layer and the non-connecting portion of the pad portion of the gate electrode.

16. The nonvolatile memory device according to claim 15, wherein: The vertical level of the second portion of the liner film has a stepped shape in the first horizontal direction.

17. An electronic system, comprising: main base; a nonvolatile memory device on a primary substrate; as well as A controller, on the main substrate, the controller is electrically connected to the non-volatile memory device, Wherein, the non-volatile memory device comprises: A unit substrate, comprising a first unit region, a second unit region and a connection region, wherein the connection region is located between the first unit region and the second unit region; a mold structure comprising a plurality of gate electrodes and a plurality of mold insulating layers, the plurality of gate electrodes and the plurality of mold insulating layers being stacked on a unit substrate, the plurality of gate electrodes being stacked on a pad region of a connection region in a stair pattern, and the plurality of mold insulating layers being alternately stacked with the plurality of gate electrodes; a channel structure on the first cell region and the second cell region, the channel structure extending through the mold structure and crossing the plurality of gate electrodes; a cell contact on the pad region of the connection region, the cell contact comprising a bottom surface and a first sidewall, the first sidewall being located on a boundary between the pad region of the connection region and the wall region of the connection region, the bottom surface being connected to a pad portion of a gate electrode among the plurality of gate electrodes; A liner film including a first portion, the first portion being located on a first sidewall of the cell contact; a cover insulating layer, on the pad region of the connection region, the cover insulating layer surrounding a second sidewall of the cell contact, the second sidewall of the cell contact being opposite to the first sidewall of the cell contact; and A dam structure is located between the second side wall of the cell contact and the covering insulating layer, wherein the liner film contacts the first side wall of the cell contact, and The liner film has an etching selectivity different from that of the cover insulating layer.

18. The electronic system according to claim 17, wherein: The dam structure has a different etching selectivity from the capping insulating layer.

19. The electronic system according to claim 17, wherein: In a plan view, the second side wall of the cell contact is recessed relative to the first side wall of the cell contact.

20. The electronic system according to claim 19, wherein: In plan view, the cell contact has a semicircular shape, and The first side wall and the second side wall of the cell contact define a semicircular shape.

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