Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a variable resistance pattern configured to switch between different resistance states in response to an applied voltage or current; and a selector pattern disposed over the variable resistance pattern and having a lower surface in direct contact with an upper surface of the variable resistance pattern, the selector pattern configured to include an insulating material doped with a dopant, and exhibit a threshold switching behavior, the variable resistance pattern and the selector pattern are arranged to exhibit (1) a conductive state that provides a conductive path in the selector pattern and (2) a non-conductive state that turns off the conductive path in the selector pattern, and selectively switch between the two states in which sidewalls of the variable resistance pattern and sidewalls of the selector pattern are aligned with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0135130, filed on October 11, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent document relates to a semiconductor design technology, and more particularly, to a semiconductor device including a selector and a method of manufacturing the same. Background Art

[0004] As the electrical and electronic industries have recently moved toward miniaturization, low power consumption, high performance, and multifunctionality, semiconductor manufacturers are focusing on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include semiconductor devices capable of storing data by switching between different resistance states based on applied voltage or current, such as resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses (E-fuse). Summary of the invention

[0005] In one embodiment, a semiconductor device may include: a variable resistance pattern configured to switch between different resistance states in response to an applied voltage or current; and a selector pattern disposed above the variable resistance pattern and having a lower surface in direct contact with an upper surface of the variable resistance pattern, the selector pattern being constructed to include an insulating material doped with a dopant, and exhibiting threshold switching behavior to exhibit (1) a conductive state providing a conductive path in the selector pattern and (2) a non-conductive state that turns off the conductive path in the selector pattern, and selectively switch between the conductive state and the non-conductive state, wherein sidewalls of the variable resistance pattern and sidewalls of the selector pattern are aligned with each other.

[0006] In one embodiment, a method for manufacturing a semiconductor device may include: forming a variable resistance layer configured to switch between different resistance states in response to an applied voltage or current; forming an insulating pattern above the variable resistance layer; performing a first etching process using the insulating pattern as an etching barrier to etch a portion of the variable resistance layer; and performing a second etching process using the insulating pattern as an etching barrier to etch a remaining portion of the variable resistance layer to form a variable resistance pattern, wherein, during the second etching process, dopants are injected into the insulating pattern by flowing a gas containing dopants, and the insulating pattern injected with dopants forms a selector pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the disclosed technology.

[0008] Figure 2 is a cross-sectional view showing an example of a selector assembly based on an embodiment of the disclosed technology.

[0009] Figure 3 It is shown Figure 2 Figure 1. Example operation of the selector component.

[0010] FIG. 4A to FIG. 4C is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the disclosed technology.

[0011] Figure 5 yes Figure 4C An enlarged view of a portion of a semiconductor device.

[0012] Figure 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the disclosed technology. DETAILED DESCRIPTION

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] The drawings are not necessarily drawn to scale, and in some cases, the scale of at least some structures in the drawings may have been enlarged to clearly illustrate certain features of the described embodiments. When a specific example with two or more layers in a multilayer structure is presented in the drawings or descriptions, the relative positioning relationship of these layers as shown or the order in which these layers are arranged reflects the specific implementation of the described or shown example, and there may be different relative positioning relationships or the order in which these layers are arranged. In addition, the example of the described or shown multilayer structure may not reflect all the layers present in the specific multilayer structure (for example, there may be one or more additional layers between the two shown layers). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0015] ] Figure 1 is a perspective view of a semiconductor device according to an embodiment of the disclosed technology.

[0016] See also Figure 1, the semiconductor device according to the embodiment may include a substrate 100, a plurality of first conductive lines 110 disposed on the substrate 100 and extending in a first direction, a plurality of second conductive lines 120 disposed on the first conductive lines 110 and extending in a second direction intersecting the first direction, and a plurality of memory cells MC interposed between the first conductive lines 110 and the second conductive lines 120 and respectively overlapping with the intersection regions of the first conductive lines 110 and the second conductive lines 120. Here, the first direction and the second direction may be substantially parallel to the upper surface of the substrate 100. In some implementations, a direction substantially perpendicular to the upper surface of the substrate 100 may be referred to as a vertical direction.

[0017] The substrate 100 may include a semiconductor material such as silicon. In addition, the substrate 100 may include a desired lower structure (not shown). As an example, the substrate 100 may include an integrated circuit for driving (eg, controlling, selecting, activating, etc.) the first conductive line 110 and / or the second conductive line 120.

[0018] The first conductive lines 110 may be arranged to be spaced apart from each other in the second direction. The first conductive lines 110 may include at least one of a plurality of conductive materials, for example, a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti)), a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof, and may have a single-layer structure or a multi-layer structure.

[0019] The second conductive lines 120 may be arranged to be spaced apart from each other in the first direction. The second conductive lines 120 may include at least one of a plurality of conductive materials, for example, a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti)), a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof, and may have a single-layer structure or a multi-layer structure.

[0020] Each memory cell MC may include a memory component MU configured to store data and a selector component SU that controls access to the memory component MU. As an example, the memory cell MC may include a stacked structure including a lower electrode layer 130, a selector layer 140, an intermediate electrode layer 150, a variable resistance layer 160, and an upper electrode layer 170. Here, the selector component SU may include the lower electrode layer 130, the selector layer 140, and the intermediate electrode layer 150, and the memory component MU may include the intermediate electrode layer 150, the variable resistance layer 160, and the upper electrode layer 170. The intermediate electrode layer 150 may be shared by the selector component SU and the memory component MU.

[0021] The lower electrode layer 130 and the upper electrode layer 170 may be located at the bottom and top of the memory cell MC, respectively, and may be used as a channel for transmitting voltage or current. The intermediate electrode layer 150 may be used to electrically connect the selector layer 140 and the variable resistance layer 160 and physically separate them. The lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include at least one of a plurality of conductive materials, for example, a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti)), a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), or a combination thereof. In some embodiments, the lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include a carbon electrode.

[0022] The selector layer 140 can control access to the variable resistance layer 160 and prevent or reduce current leakage that may occur between the memory cells MC that share the first conductive line 110 or the second conductive line 120. To this end, the selector layer 140 can have a threshold switching characteristic in response to an applied voltage, and can exhibit (1) a conductive state that provides a conductive path in the selector layer 140, and (2) a non-conductive state that turns off the conductive path in the selector layer 140, and selectively switch between these states. For example, when the amplitude of the voltage applied to the selector layer 140 is less than a predetermined threshold voltage, the current is blocked or hardly flows in the selector layer 140 to turn off the conductive path, and at a voltage equal to or higher than the threshold voltage, a conductive path is provided to allow current to flow through the selector layer 140 and increase rapidly. That is, the selector layer 140 can be turned on when the applied voltage is higher than the threshold voltage, and turned off when the applied voltage is lower than the threshold voltage. In implementation, the selector layer 140 may include an insulating material injected with a dopant. The following will refer to Figure 2 and Figure 3 The selector components SU including the selector layer 140 and their operations are described in more detail.

[0023] Figure 2 is a cross-sectional view showing an example of a selector assembly based on an embodiment of the disclosed technology.

[0024] refer to Figure 2 The selector assembly SU may include a lower electrode layer 130 , a selector layer 140 , and an intermediate electrode layer 150 .

[0025] As described above, the lower electrode layer 130 and the intermediate electrode layer 150 may include at least one of a plurality of conductive materials, such as metals and metal nitrides. The lower electrode layer 130 and the intermediate electrode layer 150 may be formed of the same material and thus may have the same work function. As an example, the lower electrode layer 130 and the intermediate electrode layer 150 may include titanium nitride (TiN) having a work function of 4.4 to 4.6 eV. However, the disclosed technology is not limited to this example, and the lower electrode layer 130 and the intermediate electrode layer 150 may be formed of different materials and thus may have different work functions.

[0026] The selector layer 140 may include an insulating material layer 142 , and a dopant 144 implanted into the insulating material layer 142 .

[0027] The insulating material layer 142 may include an insulating material with a relatively wide band gap, for example, a band gap of 5.0 eV or greater. As an example, the insulating material layer 142 may include a silicon-containing insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride), an insulating metal oxide, an insulating metal nitride, or a combination thereof. Deep traps may exist within the insulating material layer 142. The energy level of the deep trap may be closer to the valence band energy level of the insulating material layer 142 than the conduction band energy level of the non-insulating material layer 142. The dopant 144 may be used to create a shallow trap, which provides a channel for conductive carriers (e.g., electrons or holes) to move within the insulating material layer 142. The energy level of the shallow trap may be closer to the conduction band energy level of the insulating material layer 142 than the valence band energy level of the non-insulating material layer 142. As an example, when the insulating material layer 142 includes silicon, the dopant 144 may include a metal having a different valence state from silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. In some embodiments, when the insulating material layer 142 includes a metal, the dopant 144 may include silicon or another metal having a valence state different from that of the metal. As an example, the insulating material layer 142 may include silicon oxide, such as silicon dioxide (SiO2), and the dopant 144 may include arsenic (As). That is, the selector layer 140 may include silicon dioxide (SiO2) doped with arsenic (As).

[0028] The following will refer to Figure 3 Describe the operation of the selector component SU.

[0029] Figure 3 It is shown Figure 2 Figure 1. Example operation of the selector component.

[0030] refer to Figure 3, in an “off” state where no voltage is applied to the selector component SU, conductive carriers (eg, electrons (e)) may be trapped in deep traps T1 of the selector layer 140 .

[0031] When a voltage higher than the threshold voltage is applied to the selector component SU in the off state through the lower electrode layer 130 and the middle electrode layer 150, an “on” state in which current flows through the selector component SU can be achieved. In some implementations, when a voltage higher than the threshold voltage is applied to the selector component SU, the conductive carriers trapped in the deep trap T1 can jump to the shallow trap T2 by thermal emission or tunneling, and the conductive carriers can move through the shallow trap T2, thereby forming a conductive path connecting the lower electrode layer 130 and the middle electrode layer 150.

[0032] When the voltage applied to the selector element SU in the on state is reduced, the number of conductive carriers moving from the deep trap T1 to the shallow trap T2 is reduced, and the selector element SU is turned off again.

[0033] In this way, the selector assembly SU can be turned on or off.

[0034] Reference again Figure 1 , the variable resistance layer 160 may be a portion storing data in the memory cell MC. To this end, the variable resistance layer 160 may have a variable resistance characteristic of switching between different resistance states based on a voltage or current applied thereto. The variable resistance layer 160 may have a single-layer structure or a multi-layer structure, which includes at least one of a variety of materials used in RRAM, PRAM, FRAM, MRAM, etc., such as metal oxides (such as transition metal oxides or perovskite-based materials), phase change materials (such as chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials. In addition, as an example, the variable resistance layer 160 may include a magnetic tunnel junction structure, which includes a pinned layer, a tunnel barrier layer, and a free layer.

[0035] The memory cell MC may have a columnar shape, which overlaps the intersection area of ​​the first conductive line 110 and the second conductive line 120. In this figure, the memory cell MC is shown as having a cylindrical shape, but the disclosed technology is not limited thereto, and the memory cell MC may have various shapes, such as a square column, a rectangular column, or an elliptical column, etc.

[0036] In some implementations, the layer structure of the memory cell MC is not limited to that shown in the figure. The stacking order of the layers of the memory cell MC may be changed, one or more of the layers of the memory cell MC may be omitted, or one or more additional layers may be added to the memory cell MC. As an example, one or more of the lower electrode layer 130, the middle electrode layer 150, and the upper electrode layer 170 may be omitted. Alternatively, the positions of the selector layer 140 and the variable resistance layer 160 may be reversed with each other. In some embodiments, one or more layers (not shown) may be added to the memory cell MC to improve the process or characteristics of the memory cell MC.

[0037] In an embodiment, when the variable resistance layer 160 has a multilayer structure such as a magnetic tunnel junction structure, it may be difficult to collectively etch the layers 130 to 170 forming the memory cell MC using a single mask. In this case, different masks may be used to pattern the selector layer 140 and the variable resistance layer 160, respectively, so they may have sidewalls that are not aligned with each other. When the selector layer 140 and the variable resistance layer 160 are patterned using different masks, the manufacturing process may become complicated and the production cost may increase. In addition, when the selector layer 140 and the variable resistance layer 160 are etched together using a single mask, the process difficulty may increase due to the increase in the thickness of the etching target, and the characteristics of the selector layer 140 and / or the variable resistance layer 160 may be degraded due to abnormal etching.

[0038] The disclosed technology may be implemented in some embodiments to provide a semiconductor device including an insulating material layer as a selector and a method of manufacturing the semiconductor device, as described below.

[0039] FIG. 4A to FIG. 4C is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the disclosed technology.

[0040] In an embodiment, the manufacturing method may include the following operations.

[0041] refer to Figure 4A The manufacturing method may include forming a substrate 200 including a predetermined lower structure. The substrate 200 may include a variety of circuits. For example, the substrate 200 may include a circuit similar to the above Figure 1 The first conductive wire 110 is a conductive wire.

[0042] Subsequently, a variable resistance layer 210 may be formed on the substrate 200. The variable resistance layer 210 may have a multilayer structure in which two or more layers are stacked. As an example, the variable resistance layer 210 may include a magnetic tunnel junction structure in which a lower conductive layer 211, a pinned layer 213, a tunnel barrier layer 215, a free layer 217, and an upper conductive layer 219 are stacked.

[0043] The pinned layer 213 may be a layer having a fixed magnetization direction and may be used as a reference layer for comparison with the magnetization direction of the free layer 217. The free layer 217 may be used as a storage layer, which may store different data bits by changing the magnetization direction. The tunnel barrier layer 215 may physically separate the pinned layer 213 from the free layer 217 and may enable electron tunneling between them. Each of the pinned layer 213 and the free layer 217 may have a single layer or multilayer structure including a ferromagnetic material. As an example, each of the pinned layer 213 and the free layer 217 may include an alloy including Fe, Ni or Co as a main component, such as a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, a Fe-Pd alloy and a Co-Fe-B alloy, or a stacked structure of Co / Pt or Co / Pd. In one example, the tunnel barrier layer 215 may have a single layer structure including an insulating material. In another example, the tunnel barrier layer 215 may have a multilayer structure including an insulating material. For example, the tunnel barrier layer 215 may include an insulating oxide such as MgO, CaO, SrO, TiO, VO, or NbO. Figure 4A-4C As shown, the free layer 217 may be located above the tunnel barrier layer 215, and the pinned layer 213 may be located below the tunnel barrier layer 215. In another example, the pinned layer 213 may be located above the tunnel barrier layer 215, and the free layer 217 may be located below the tunnel barrier layer 215.

[0044] The lower conductive layer 211 may be located at the bottom of the variable resistance layer 210 to achieve electrical connection between the substrate 200 and the variable resistance layer 210, and may perform a variety of functions to improve the characteristics of the variable resistance layer 210. For example, the lower conductive layer 211 may be used as a seed layer that helps the crystal growth of the magnetic layer (e.g., the pinning layer 213) located above the lower conductive layer 211. The lower conductive layer 211 may include a non-magnetic conductive material. As an example, the lower conductive layer 211 may include a metal (such as tungsten (W), ruthenium (Ru), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), or chromium (Cr)), a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), or a combination thereof. The lower conductive layer 211 may be omitted.

[0045] The upper conductive layer 219 may be located on the top of the variable resistance layer 210 to achieve the connection between the variable resistance layer 210 and the selector pattern (see Figure 4C220B in the upper conductive layer 219), and may perform a variety of functions to improve the characteristics of the variable resistance layer 210. For example, the upper conductive layer 219 may be used as a capping layer that protects a magnetic layer, such as the free layer 217, located below the upper conductive layer 219. In addition, the upper conductive layer 219 may play a role in preventing dopants from diffusing into magnetic materials, such as the free layer 217, as described below. The upper conductive layer 219 may include a non-magnetic conductive material. As an example, the upper conductive layer 219 may include a metal, such as tungsten (W), ruthenium (Ru), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), or chromium (Cr), a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof.

[0046] Subsequently, an insulating material layer 220 may be formed on the variable resistance layer 210. The insulating material layer 220 may be used to form a selector and may be formed by depositing an insulating material. As an example, the insulating material layer 220 may include a silicon-containing insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride), an insulating metal oxide, an insulating metal nitride, or a combination thereof. In one example, the insulating material layer 220 may include silicon dioxide.

[0047] Subsequently, the mask pattern 230 is used to form a pillar over the insulating material layer 220 by patterning the variable resistance layer 210 and the insulating material layer 220. The mask pattern 230 may include at least one of various materials such as metal, and may have a single layer structure or a multi-layer structure.

[0048] refer to Figure 4B , the insulating material layer 220 may be etched using the mask pattern 230 as an etch barrier to form an insulating pattern 220A.

[0049] The disclosed technology can be implemented in some embodiments to etch the variable resistance layer 210 by using the insulating pattern 220A as an etching barrier to solve the problems discussed above. In one example, a portion of the variable resistance layer 210 can be etched to form an initial variable resistance pattern 210A. When the portion of the variable resistance layer 210 is etched, the remaining portion of the variable resistance layer 210 can be retained without being etched. The partial etching process of the variable resistance layer 210 for forming the initial variable resistance pattern 210A will be referred to as the first etching process hereinafter. The first etching process can be performed using an ion beam etching (IBE) process. When performing the formation process of the insulating pattern 220A and / or the first etching process, the mask pattern 230 can be removed. The disclosed technology can be implemented in some embodiments to use the insulating pattern 220A as a hard mask for partial etching of the variable resistance layer 210 even after removing the mask pattern 230.

[0050] In an embodiment, during the first etching process, a portion of the upper conductive layer 219, the free layer 217, the tunnel barrier layer 215, the pinned layer 213, and the lower conductive layer 211 may be etched. The etched upper conductive layer 219, the etched free layer 217, the etched tunnel barrier layer 215, the etched pinned layer 213, and the etched lower conductive layer 211 will be referred to as an upper conductive pattern 219A, a free pattern 217A, a tunnel barrier pattern 215A, a pinned pattern 213A, and an initial lower conductive pattern 211A, respectively. The initial variable resistance pattern 210A may include an upper conductive pattern 219A, a free pattern 217A, a tunnel barrier pattern 215A, a pinned pattern 213A, and an initial lower conductive pattern 211A. However, the disclosed technology is not limited to this example, and the etching depth during the first etching process may vary. That is, during the first etching process, the first thickness TH1 of the etched portion of the variable resistance layer 210 and the second thickness TH2 of the remaining portion of the variable resistance layer 210 may vary. In one example, the first thickness TH1 may be greater than the second thickness TH2 because the first etching process is the main process of the etching process of the variable resistance layer 210. The sum of the first thickness TH1 and the second thickness TH2 may correspond to the total thickness of the variable resistance layer 210 or the initial variable resistance pattern 210A.

[0051] refer to Figure 4C , the remaining portion of the initial variable resistance pattern 210A exposed by the insulating pattern 220A to form the variable resistance pattern 210B may be etched. The partial etching process of the initial variable resistance pattern 220B for forming the variable resistance pattern 210B will be referred to as the second etching process hereinafter. The second etching process may be performed using IBE. The second etching process may be performed in situ with the first etching process after the first etching process.

[0052] In some embodiments, by flowing a dopant-containing gas during the second etching process, a dopant may be doped / injected into the insulating pattern 220A to form a selector pattern 220B. The dopant may include an element capable of creating a shallow trap that provides a channel for conductive carriers (e.g., electrons or holes) within the insulating pattern 220A. The dopant may include an element having a valence state different from that of the constituent elements of the insulating pattern 220A, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. When the insulating pattern 220A includes silicon dioxide, the dopant may include arsenic, and thus a selector pattern 220B including silicon dioxide injected with arsenic may be formed. In this case, the dopant-containing gas may be, for example, arsenic gas.

[0053] During the second etching process, the insulating pattern 220A and / or the selector pattern 220B may be used as a hard mask for the second etching process. In an embodiment, during the second etching process, the remaining portion of the initial lower conductive pattern 211A that is not etched in the first etching process may be etched. The etched initial lower conductive pattern 211A etched by the second etching process may be referred to as a lower conductive pattern 211B, and the variable resistance pattern 210B may include an upper conductive pattern 219A, a free pattern 217A, a tunnel barrier pattern 215A, a pinning pattern 213A, and a lower conductive pattern 211B. The second etching process may be an additional etching process performed in addition to the first etching process. In other words, the first thickness TH1 of the portion etched during the first etching process may be greater than the second thickness TH2 of the portion etched during the second etching process. Therefore, the time required to perform the second etching process may be shorter than the time required to perform the first etching process. The conditions of the second etching process may be substantially the same as those of the first etching process, except for flowing more dopant-containing gas and a shorter process time during the second etching process.

[0054] In some embodiments, the dopant of the second etching process can be injected not only into the insulating pattern 220A, but also into the variable resistance pattern 210B. Since the upper surface of the variable resistance pattern 210B is covered during the second etching process, the dopant can be injected into a portion of a predetermined width from the side wall of the variable resistance pattern 210B. Hereinafter, the region from the side wall of the variable resistance pattern 210B into which the dopant is injected will be referred to as the first dopant region P1. Since the time period for which the second etching process is performed is relatively short, the size of the first dopant region P1 may not be large. Therefore, even if the first dopant region P1 exists in a portion of the side wall of the variable resistance pattern 210B, it will not significantly affect the characteristics of the variable resistance pattern 210B.

[0055] In addition, the dopant of the selector pattern 220B can diffuse through the upper surface of the variable resistance pattern 210B, so the dopant can be injected into a portion of a predetermined depth from the upper surface of the variable resistance pattern 210B. Hereinafter, the region from the upper surface of the variable resistance pattern 210B into which the dopant is injected will be referred to as the second dopant region P2. Since the time period in which the second etching process is performed is relatively short, the degree of diffusion of the dopant may not be relatively large, and therefore the size of the second dopant region P2 may not be very large. Therefore, even if the second dopant region P2 exists in a portion of the upper surface of the variable resistance pattern 210B, it will not significantly affect the characteristics of the variable resistance pattern 210B. Specifically, the second dopant region P2 can be formed in a portion of a predetermined depth from the upper surface of the upper conductive pattern 219A. That is, the second dopant region P2 can be disposed in the upper conductive pattern 219A disposed at the uppermost portion of the variable resistance pattern 210B. Since the upper conductive pattern 219A acts as a diffusion barrier for dopants, the second dopant region P2 may not be formed in a magnetic material (such as a free pattern 217A) that directly affects the variable resistance characteristics of the variable resistance pattern 210B, thereby preventing degradation of the characteristics of the variable resistance pattern 210B caused by dopants.

[0056] The semiconductor device according to the embodiment can be manufactured through the above-mentioned process.

[0057] Reference again Figure 4C , a semiconductor device according to an embodiment may include a substrate 200, a variable resistance pattern 210B formed on the substrate 200, and a selector pattern 220B formed on the variable resistance pattern 210B. The selector pattern 220B may include an insulating material implanted with a dopant.

[0058] Here, since the variable resistance pattern 210B is formed by an etching process using the selector pattern 220B and / or the insulating pattern 220A as a hard mask, the sidewall of the variable resistance pattern 210B may be aligned with the sidewall of the selector pattern 220B. In addition, the upper surface of the variable resistance pattern 210B, for example, the upper surface of the upper conductive pattern 219A, may directly contact the lower surface of the selector pattern 220B. In other words, the electrode layer between the variable resistance pattern 210B and the selector pattern 220B, for example, the intermediate electrode layer (see Figure 1 150 in , can be omitted.

[0059] The first dopant region P1 may be formed in a portion from a sidewall of the variable resistance pattern 210B. The second dopant region P2 may be formed in a portion from an upper surface of the variable resistance pattern 210B, for example, a portion from an upper surface of the upper conductive pattern 219A. The first dopant region P1 and the second dopant region P2 may include dopants injected into the selector pattern 220B.

[0060] Based on the semiconductor device and the manufacturing method thereof, since the selector pattern 220B and the insulating pattern 220A are used as hard masks for the first and second etching processes, the process can be simplified and the process cost can be reduced. In addition, by reducing the process difficulty, it is beneficial to ensure the characteristics of the selector pattern 220B and the variable resistance pattern 210B.

[0061] In addition, since the dopant is injected through the sidewall and the upper surface of the insulating pattern 220A, there may be an advantage of improving the dopant distribution. Figure 5 This is described in more detail.

[0062] Figure 5 yes Figure 4C An enlarged view of a portion of a semiconductor device.

[0063] refer to Figure 5 In the dopant distribution shown on the right side of the selector pattern 220B, it can be seen that the dopant concentration based on depth in the vertical direction is substantially constant (see ①).

[0064] This may be because, in the second etching process, a dopant-containing gas, such as arsenic gas, flows in a state where the sidewalls and the upper surface of the insulating pattern 220A are exposed, and thus, the dopant is injected in a direction toward the sidewalls and the upper surface of the insulating pattern 220A. In other words, the dopant may be injected in a direction indicated by an arrow to form the selector pattern 220B.

[0065] If the selector is formed by implanting a dopant into the upper surface of the insulating material layer using an ion implantation method as in the prior art, the dopant concentration according to the depth in the vertical direction may not be constant and may vary greatly. This may be because, in the ion implantation process, a Gaussian distribution occurs in which the dopant concentration is the largest at a specific depth of the selector and decreases rapidly as the distance from the specific depth in the vertical direction increases.

[0066] Therefore, in one embodiment, since the dopant concentration in the selector pattern 220B is substantially constant according to the depth, the switching characteristics of the selector pattern 220B may be improved.

[0067] In addition, in the above-mentioned embodiments, the case where the variable resistance pattern includes a magnetic tunnel junction structure has been described, but the disclosed technology is not limited thereto. The variable resistance pattern may include a variety of materials and may have a variety of layer structures as long as the variable resistance pattern can store different data by switching between different resistance states according to a voltage or current applied thereto. Figure 6 This is described exemplarily.

[0068] Figure 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the disclosed technology.

[0069] refer to Figure 6 , a semiconductor device according to an embodiment may include a substrate 300, a variable resistance pattern 310 formed on the substrate 300, and a selector pattern 320 formed on the variable resistance pattern 310. The selector pattern 320 may include an insulating material implanted with a dopant.

[0070] Here, the variable resistance pattern 310 may include a lower conductive pattern 311, a variable resistance material layer 313, and an upper conductive pattern 315. As an example, the variable resistance material layer 313 may include a phase change material. At this time, the crystalline state of the phase change material may be switched between an amorphous state and a crystalline state according to a voltage or current applied to the variable resistance pattern 310, so that the resistance state of the variable resistance pattern 310 may be switched between a high resistance state and a low resistance state. Alternatively, as an example, the variable resistance material layer 313 may include a metal oxide. In this case, according to a voltage or current applied to the variable resistance pattern 310, a conductive path caused by metal ions or oxygen vacancies may be created or destroyed, so that the resistance state of the variable resistance pattern 310 may be switched between a high resistance state and a low resistance state.

[0071] The first dopant region P1' may be formed in a portion from a sidewall of the variable resistance pattern 310. The second dopant region P2' may be formed in a portion from an upper surface of the variable resistance pattern 130, for example, from an upper surface of the upper conductive pattern 315. The first dopant region P1' and the second dopant region P2' may include dopants implanted into the selector pattern 320.

[0072] The semiconductor device and the manufacturing method thereof based on the embodiments of the above-mentioned disclosed technology can facilitate the manufacturing process and improve the characteristics.

[0073] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined by the following claims.

Claims

1. A semiconductor device, comprising: a variable resistance pattern that switches between different resistance states in response to an applied voltage or current; as well as a selector pattern disposed above the variable resistance pattern and having a lower surface directly contacting the upper surface of the variable resistance pattern, the selector pattern being configured to include an insulating material doped with a dopant, and exhibiting a threshold switching behavior to exhibit (1) a conductive state providing a conductive path in the selector pattern and (2) a non-conductive state shutting off the conductive path in the selector pattern, and selectively switching between the conductive state and the non-conductive state, Wherein, a sidewall of the variable resistance pattern and a sidewall of the selector pattern are aligned with each other.

2. The semiconductor device according to claim 1, wherein The variable resistance pattern includes a portion including the dopant and extending from the sidewall of the variable resistance pattern toward an inner portion of the variable resistance pattern.

3. The semiconductor device according to claim 1, wherein The variable resistance pattern includes a portion including the dopant and extending from the upper surface of the variable resistance pattern directly contacting the selector pattern toward the inside of the variable resistance pattern.

4. The semiconductor device according to claim 1, wherein: The variable resistor pattern comprises: a conductive pattern disposed at the uppermost portion of the variable resistance pattern, and A portion includes the dopant and extends from an upper surface of the conductive pattern toward an interior of the variable resistance pattern.

5. The semiconductor device according to claim 4, wherein: The variable resistance pattern includes a magnetic tunnel junction structure disposed under the conductive pattern and including a pinned layer having a fixed magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer between the pinned layer and the free layer.

6. A method for manufacturing a semiconductor device, comprising: forming a variable resistance layer that switches between different resistance states in response to an applied voltage or current; forming an insulating pattern on the variable resistance layer; performing a first etching process using the insulating pattern as an etching barrier to etch a portion of the variable resistance layer; as well as performing a second etching process using the insulating pattern as an etching barrier to etch a remaining portion of the variable resistance layer to form a variable resistance pattern, wherein during the second etching process, dopants are injected into the insulating pattern by flowing a gas containing dopants, and The insulating pattern into which the dopant is implanted forms a selector pattern.

7. The method according to claim 6, wherein: The thickness of the portion of the variable resistance layer is greater than the thickness of the remaining portion of the variable resistance layer.

8. The method according to claim 6, wherein: The time required to perform the first etching process is greater than the time required to perform the second etching process.

9. The method according to claim 6, wherein: The dopant is implanted through an upper surface and a sidewall of the insulating pattern.

10. The method according to claim 6, wherein: The first etching process and the second etching process are performed by an IBE method, where IBE refers to ion beam etching.

11. The method according to claim 6, wherein: The first etching process and the second etching process are performed in-situ.

12. The method according to claim 6, wherein: The dopant is implanted into a portion of the variable resistance pattern from a sidewall of the variable resistance pattern.

13. The method according to claim 6, wherein: The dopant is injected into a portion of the variable resistance pattern from an upper surface of the variable resistance pattern.

14. The method according to claim 13, wherein: The variable resistance layer includes a conductive layer disposed at the uppermost portion of the variable resistance layer, and The dopant is implanted into a portion of the conductive layer.

15. The method according to claim 14, wherein: The variable resistance pattern includes a magnetic tunnel junction structure disposed below the conductive layer, the magnetic tunnel junction structure including a pinned layer having a fixed magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer between the pinned layer and the free layer.

16. The method according to claim 6, wherein: An upper surface of the variable resistance pattern is in direct contact with a lower surface of the selector pattern.

17. The method according to claim 6, wherein: A sidewall of the variable resistance pattern is aligned with a sidewall of the selector pattern.

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